United States Patent [191
`Motonami
`
`[54]
`
`175]
`[73]
`
`[21]
`[22]
`
`Inventor:
`Assignee:
`
`METHOD OF MANUFACTURING
`SEMICONDUCTOR DEVICE COMPRISING
`INTERCONNECT ION
`Kaoru Motonami, Hyogo, Japan
`Mitsubishi Denki Kabushiki Kaisha,
`Tokyo, Japan
`‘
`234,806
`Apr. 28, 1994
`
`Appl. No:
`Filed:
`
`[62]
`
`Related US. Application Data
`Division of Ser. No. 875,185, Apr. 28, 1992, Pat. No.
`5,323,049.
`Foreign Application Priority Data
`[30]
`May 10, 1991 [JP]
`Japan ................................ .. 3-105719
`
`[51] Int. Cl.6 ................. .. H01L 21/283; H01L 21/312
`[52] US. Cl. .................................... .. 437/195; 437/52;
`437/187; 437/229
`[53] Field of Search ............... .. 437/195, 52, 229, 187,
`437/228
`
`[56]
`
`References Cited
`
`U'S‘ PATENT DOCUMENTS
`4,317,276 3/1982 Heeren 61 al. ...................... .. 437/41
`gamck ------------ "
`5,091,761 2/1992 Hiraiwa et a1. .
`5,135,891 8/1992 Ikeno et a1. ....................... .. 437/228
`5,177,575 l/1993 Ikeda .
`
`,
`
`,
`
`ma .................................... ..
`
`llllllllllllllllllllllllllllllllllllllllllllllllllll|l|||Illlllllllllllllll
`
`USOO5441916A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,441,916
`Aug. 15, 1995
`
`5,196,910 3/1993 Moriuchi et a1. .
`5,258,329 11/1993 Shibata .............................. .. 437/195
`
`FOREIGN PATENT DOCUMENTS
`
`0423814 4/1991 European Pat. Off. .
`4034169A1 5/1991 Germany .
`
`Primary Examiner-T. N. Quach
`Attorney, Agent, or Firm-Lowe, Price, LeBlanc &
`Becker
`
`ABSTRACT
`[57]
`In a semiconductor device, a ?rst conductive intercon
`nection layer and a second conductive interconnection
`layer are formed respectively on a lower surface and a
`higher surface of an interlayer insulation ?lm interpos
`ing a step-like portion therebetween by employing dif
`ferent photolithography and etching. A dummy inter
`connection is provided directly beneath the second
`conductive interconnection layer in the vicinity of the
`step-like portion. The ?rst and second conductive inter
`connection layers and are electrically connected to each
`other by a conductive layer formed directly on the
`dummy interconnection in a region including the step
`like portion to extend over the surface of a silicon sub
`strate. Consequently, even if the step-like portion is
`larger than depth of focus, the ?rst and Second conduc
`tive interconnection layers are precisely patterned
`W‘thm depth of focus‘
`
`-
`
`-
`
`6 Claims, 12 Drawing Sheets
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`NVIDIA Corp.
`Exhibit 1106
`Page 001
`
`

`

`US. Patent
`
`Aug. 15, 1995
`
`Sheet 1 of 12
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`5,441,916
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`NVIDIA Corp.
`Exhibit 1 106
`Page 002
`
`NVIDIA Corp.
`Exhibit 1106
`Page 002
`
`

`

`US. Patent
`
`Aug. 15, 1995
`
`Sheet 2 0f 12
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`5,441,916
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`NVIDIA Corp.
`Exhibit 1106
`Page 003
`
`

`

`US. Patent
`
`Aug. 15, 1995
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`Sheet 3 0f 12
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`5,441,916
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`NVIDIA Corp.
`Exhibit 1106
`Page 004
`
`

`

`US. Patent
`
`Aug. 15, 1995
`
`Sheet 4 0f 12
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`5,441,916
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`
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`229
`
`NVIDIA Corp.
`Exhibit 1106
`Page 005
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`

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`US. Patent
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`Aug. 15, 1995
`
`Sheet 5 of 12
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`5,441,916
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`NVIDIA Corp.
`Exhibit 1106
`Page 006
`
`

`

`U.S. Patent
`
`Aug. 15, 1995
`
`I" I
`
`FIG.6A
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`FIG.6B
`
`NVIDIA Corp.
`Exhibit 1106
`Page 007
`
`

`

`US. Patent
`
`Aug. 15, 1995
`
`Sheet 7 of 12
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`5,441,916
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`NVIDIA Corp.
`Exhibit 1106
`Page 008
`
`

`

`US. Patent
`
`Aug. 15, 1995
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`Sheet 8 of 12
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`5,441,916
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`NVIDIA Corp.
`Exhibit 1106
`Page 009
`
`

`

`US. Patent
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`Aug. 15, 1995
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`Sheet 9 of 12
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`5,441,916
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`NVIDIA Corp.
`Exhibit 1106
`Page 010
`
`

`

`US. Patent
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`Aug. 15, 1995
`
`Sheet 10 of 12
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`NVIDIA Corp.
`Exhibit 1106
`Page 011
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`

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`U.S. Patent
`
`Aug. 15, 1995
`
`Sheet 11 of 12
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`5,441,916
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`
`NVIDIA Corp.
`Exhibit 1106
`Page 012
`
`

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`US. Patent D
`
`Aug. 15, 1995
`
`Sheet 12 of 12
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`5,441,916
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`FIGJZ PRIOR ART
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`NVIDIA Corp.
`Exhibit 1106
`Page 013
`
`

`

`METHOD OF MANUFACTURING
`SEMICONDUCTOR DEVICE COMPRISING
`INTERCONNECI'ION
`
`This application is a division of application Ser. No.
`07/875,185 ?led Apr. 28, 1992 US. Pat. No. 5,323,049.
`
`5
`
`15
`
`30
`
`35
`
`BACKGROUND OF THE INVENTION
`l. Field of the Invention
`The present invention relates generally to semicon
`ductor device and manufacturing methods thereof and,
`more particularly, to a technique for formation of a
`desired conductive interconnection pattern without
`being affected by step-like portions formed in an inter
`layer insulation ?lm.
`2. Description of the Background Art
`Mostly, an integrated circuit (hereinafter referred to
`as “IC”) memory such as a DRAM (Dynamic Random
`Access Memory) is comprised of a memory cell array
`including a large number of storage elements and a
`peripheral circuit necessary for input/output, and the
`memory cell array and the peripheral circuit are formed
`on the same substrate.
`25
`FIG. 12 is a block diagram showing one example of
`structure of a general DRAM. With reference to FIG.
`12, a memory cell array 1 includes a plurality of word
`lines and a plurality of bit lines arranged to cross over
`each other therein. Memory cells are provided at re
`spective cross-over points of the word lines and the bit
`lines. Each of the memory cells is selected by selecting
`a corresponding one of the word lines by an X address
`buffer decoder 2 and a corresponding one of the bit lines
`by a Y address buffer decoder 3. Data is written into a
`selected one of the memory cells, or data stored in the
`selected memory cell is read. Instruction of such data
`writing/reading is made by a read/ write control signal
`(R/W) which can be applied by a R/W control circuit
`4. In data writing, input data (Din) is applied as an input
`to the selected memory cell via R/W control circuit 4.
`In data reading, data stored in the selected memory cell
`is detected and then ampli?ed by a sense ampli?er 5.
`The ampli?ed data is output as output data (Dout) via a
`data output buffer 6 to the outside.
`FIG. 13 is an equivalent circuit diagram of a dynamic
`type memory cell for use in explaining a writing/read
`ing operation of the memory cell.
`Referring to FIG. 13, the dynamic type memory cell
`includes a set of ?eld effect transistor 7 and capacitor 8.
`A gate electrode of ?eld effect transistor 7 is connected
`to a word line 9. A source/drain electrode of ?eld effect
`transistor 7 connected to capacitor 8 is connected to a
`bit line 10. A predetermined potential is applied to word
`line 9 in data writing. This renders field effect transistor
`55
`7 conductive, so that charges applied to bit line 10 are
`stored in capacitor 8. In data reading, a predetermined
`potential is applied to word line 9. This renders transis
`tor 7 conductive, so that the charges‘stored in capacitor
`8 are extracted via bit line 10.
`A description will now be made on one example of
`structure of a conventional IC memory with reference
`to FIGS. 11A and 11B. FIG. 11A is a cross-sectional
`view showing a part of a' conventional memory cell
`array 102 and peripheral circuitry 101, and FIG. 11B is
`a plan lay~out of the corresponding part. Here, a stacked
`capacitor is shown as an example of a capacitor of a
`memory cell.
`
`40
`
`45
`
`65
`
`1
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`5,441,916
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`2
`.
`In this memory cell, with reference to FIGS. 11A and
`11B, a ?eld effect transistor 18 is formed on a silicon
`substrate 11. Field effect transistor 18 includes a gate
`oxide ?lm 19, a gate electrode 20, an overlying insulator
`?lm 21 and a sidewall insulator ?lm 22. While gate
`electrode 20 is not shown in the ?gures due to structure
`of the memory cell array, the gate electrode is disposed
`also on a ?eld oxide ?lm 12 for isolation. A diffusion
`layer 13 for reinforcing isolation is formed beneath ?eld
`oxide ?lm 12. Also, diffusion layers 14 and 15 serving as
`a source/drain region of ?eld effect transistor 18 are
`formed.
`As the one corresponding to capacitor 8 of FIG. 13,
`a capacitor including a storage node 29, a capacitor
`insulation ?lm 31 and a cell plate 32 is formed. This
`capacitor is electrically connected through a contract
`hole 27 to the aforementioned diffusion layer 15. As the
`one corresponding to bit line 10 of FIG. 13, a bit line 40
`is formed. This bit line 40 now has polycide structure
`formed of a polycrystalline silicon layer 38 and a tung
`sten silicide layer 39. This bit line 40 is electrically con
`nected through a contact hole 34 to the aforementioned
`diffusion layer 14. A diffusion layer 17 is formed in a
`peripheral circuit 102 and electrically connected
`through a contact hole 37 to bit line 40. Insulation be
`tween the capacitor and bit line 40 is achieved by an.
`interlayer insulation ?lm 33.
`At present, IC memories employ the above-described
`stacked capacitors in order to increase integration den
`sity and capacitance. Thus, there arises a problem with
`respect to step-like portions due to a difference in height
`between a portion on an IC chip where a capacitor is
`disposed and a portion where no capacitor is disposed.
`Particularly, in a case where bit line 40 is formed in an
`upper portion of the capacitor as shown in the forego
`ing conventional example, if depth of focus in resist
`pattern formation is smaller than the above-described
`step-like portions in photolithography using a photore
`sist mask for use in formation of bit line 40, it has been
`very dif?cult to precisely process all bit lines 40 on chip
`to a desired dimension in comply with the photoresist
`mask.
`
`SUMMARY OF THE INVENTION
`An object of the present invention is to provide a
`structure of and a manufacturing method of a semicon
`ductor device in which when a conductive interconnec
`tion is formed on an interlayer insulation film having a
`step-like portion, a desired conductive interconnection
`pattern can be formed without being affected by the
`step-like portion.
`A semiconductor device of the present invention
`accomplishing the foregoing object includes: an inter
`layer insulation ?lm formed on a substrate and having a
`step-like portion; a ?rst conductive interconnection
`layer formed in a lower surface of both surfaces inter
`posing the step-like portion therebetween on the inter
`layer insulation ?lm; a second conductive interconnec
`tion layer formed in a higher surface of the both sur
`faces; a dummy interconnection provided directly be
`neath the second conductive interconnection layer in
`the vicinity of the step-like portion, having approxi
`mately the same height as that of the step-like portion in
`the interlayer insulation ?lm and not serving as a con
`ductive interconnection per se; a conductive layer
`formed directly on the dummy interconnection and
`extending to substrate surface in a region including the
`step-like portion; and so on. The ?rst conductive inter
`
`NVIDIA Corp.
`Exhibit 1106
`Page 014
`
`

`

`5
`
`5,441,916
`3
`connection layer is electrically connected through a
`contact hole provided in the interlayer insulation ?lm to
`a portion of the conductive layer located in the sub
`strate surface. The second conductive interconnection
`layer is electrically connected through a contact hole
`provided in the interlayer insulation ?lm to a portion of
`the conductive layer located directly on the dummy
`interconnection.
`In accordance with the semiconductor device thus
`structured, since the conductive interconnection layer
`is not successively formed in the step-like portion of the
`interlayer insulation ?lm, disconnection of the conduc
`tive interconnection or the like which is liable to occur
`in patterning of the step-like portion is prevented.
`A method of manufacturing a semiconductor device
`according to the present invention includes the steps of:
`forming an interlayer insulation ?lm having a step-like
`portion on a substrate; depositing a conductive ?lm on
`the surface of the interlayer insulation ?lm; and pattern
`ing the conductive ?lm and forming a ?rst conductive
`interconnection layer in a lower surface of both surfaces
`of the interlayer insulation ?lm interposing the step-like
`portion therebetween and a second conductive inter
`connection layer in a higher surface of the both sur
`faces. The ?rst and second conductive interconnection
`layer forming step includes the steps of: forming a pho
`toresist mask having a pattern covering all regions
`where the second conductive interconnection layer is to
`be formed, in addition to the same pattern as that of the
`?rst conductive interconnection layer, and carrying out
`etching by using the photoresist mask as a mask; and
`forming a photoresist mask having a pattern covering
`all regions where the ?rst conductive interconnection
`layer is to be formed, in addition to the same pattern as
`that of the second conductive interconnection layer,
`and carrying out etching by using the photoresist mask
`as a mask.
`In accordance with the manufacturing method in
`cluding the above steps, when the conductive intercon
`nection layer is formed on the interlayer insulation ?lm
`having a step-like portion, the conductive interconnec
`tion layer is divided into a lower surface and a higher
`surface of the interlayer insulation ?lm with the step
`like portion interposed therebetween, and etching is
`carried out by patterning the photoresist mask for each
`region of each height. Accordingly, even if depth of
`focus in resist pattern formation is smaller than the
`step-like portion of the interlayer insulation ?lm, a con
`ductive interconnection layer of a desired shape and
`50
`size in comply with the pattern of the photoresist mask
`can be obtained for each region of each height.
`The foregoing and other objects, features, aspects
`and advantages of the present invention will become
`more apparent from the following detailed description
`of the present invention when taken in conjunction with
`the accompanying drawings.
`'
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1A is a cross-sectional view showing structure
`of a semiconductor device of a ?rst embodiment of the
`present invention.
`FIG. 1B is a plan view showing a lay-out of FIG. 1A.
`FIGS. 2A-2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A
`and 7B are cross-sectional views showing in turn the
`65
`steps of a method of manufacturing a semiconductor
`device according to the ?rst embodiment of the present
`invention.
`
`60
`
`4
`FIGS. 8A and 8B are plan views showing a lay-out of
`patterns of a photoresist mask of two stages for pattern
`ing bit lines after the step of FIG. 7B.
`FIG. 9A is a cross-sectional view showing structure
`of a memory cell of a DRAM according to a second
`embodiment of the present invention.
`FIG. 9B is a plan view showing a lay-out of FIG. 9A.
`FIG. 10A is a cross-sectional view showing structure
`of a memory cell of a DRAM according to a third
`embodiment of the present invention.
`FIG. 10B is a plan view showing a lay-out of FIG.
`10A.
`FIG. 11A is a cross-sectional view showing one ex
`ample of structure of a memory cell of a conventional
`DRAM.
`FIG. 11B is a plan view showing a lay-out of FIG.
`11A.
`FIG. 12 is a block diagram of a general RAM.
`FIG. 13 is an equivalent circuit diagram of a memory
`cell of a DRAM.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`A description will now be made on structure of a
`semiconductor device of a ?rst embodiment of the pres
`ent invention with reference to FIGS. 1A and 1B.
`The semiconductor apparatus of the present embodi
`ment is an embodiment in which the present invention is
`applied to a DRAM. In this semiconductor device, a
`?eld oxide ?lm 12 for isolation is formed in a surface of
`a p type silicon substrate 11. A p type diffusion layer 13
`for reinforcing isolation is provided in contact with a
`lower surface of ?eld oxide ?lm 12. In the surface of
`silicon substrate 11 isolated by ?eld oxide ?lm 12 are
`formed a diffusion layer being a source/drain region of
`a MOS ?eld effect transistor of a memory cell, a diffu
`sion layer 17 of a peripheral circuit and a conductive
`diffusion layer 16. The MOS ?eld effect transistor has a
`gate 18 including a gate oxide ?lm 19, a gate electrode
`20 and an overlying insulation ?lm. A sidewall insula
`tion ?lm 22 is formed on each of opposite sidewalls of
`gate 18. Gate 18 is also formed on ?eld oxide ?lm 12. On
`?eld oxide ?lm 12 is formed a dummy interconnection
`44 including an oxide ?lm 23, a polycrystalline silicon
`layer 24 and an overlying insulation ?lm 25. A sidewall
`insulation ?lm 26 is formed on sidewalls of dummy
`interconnection 44.
`A capacitor of the memory cell is formed to extend
`over both adjacent gates 18. This capacitor comprises a
`storage node 29 electrically connected to a diffusion
`layer 15 in a contact 27, a capacitor insulation ?lm 31
`formed to cover the surface of storage node 29, and a
`cell plate 32 formed to cover capacitor insulation ?lm
`31.
`A conductive polycrystalline silicon layer 30 is
`formed on dummy interconnection 44 and sidewall
`insulation ?lm 26. This conductive polycrystalline sili
`con layer 30 is connected to conductive diffusion layer
`16 in a contact 28.
`Further, an interlayer insulation ?lm 33 is formed
`over the entire surface of silicon substrate 11. Contact
`holes 34, 35, 36 and 37 are provided in interlayer insula
`tion ?lm 33. In the surface of interlayer insulation ?lm
`33 are formed a bit line 40 formed of a polycrystalline
`silicon layer 38 and a tungsten silicide layer 39, and a bit
`line 43 formed of a polycrystalline silicon layer 41 and
`a tungsten silicide layer 42. Bit line 40 is connected to a
`diffusion layer 14 in contact hole 34 and to conductive
`
`NVIDIA Corp.
`Exhibit 1106
`Page 015
`
`

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`10
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`35
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`45
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`5,441,916
`5
`polycrystalline silicon layer 30 in contact hole 35. Bit
`line 43 is connected to conductive diffusion layer 16 in
`contact hole 36 and diffusion layer 17 in contact hole 37.
`In accordance with the semiconductor device of this
`embodiment thus structured, bit lines 40 and 43 are
`separated from each other to interpose the step-like
`portion of interlayer insulation ?lm 33 therebetween,
`and those bit lines are connected with each other
`through contact holes 35 and 36 formed in interlayer
`insulation ?lm 33 and through conductive polycrystal
`line silicon layer 30 below interlayer insulation ?lm 33
`and conductive diffusion layer 16. Thus, it is unneces
`sary to successively form the bit lines in the step por
`tion, thereby eliminating such a disadvantage as discon
`nection of the bit lines which is liable to occur in pat
`terning of the step portion.
`A manufacturing method of this embodiment will
`now be described with reference to FIGS. 2A-8B. Re
`ferring ?rst to FIG. 2A, a ?eld oxide ?lm 12 for isola
`tion is formed in a p type silicon substrate 11 by employ
`ing a so-called LQCOS (Local Oxidation of Silicon)
`method, and a diffusion layer 13 for reinforcing isola
`tion is formed by implantation of boron ions. Referring
`then to FIG. 2B, a gate oxide ?lm layer 219, a gate
`electrode layer 220 and an overlying insulation ?lm
`25
`layer 221 are formed, respectively. After that, in order
`to carry out a photolithography processing using a
`photoresist mask, a photoresist pattern 118 for forming
`a gate 18 of a ?eld effect transistor and a photoresist
`pattern 144 for forming a dummy interconnection are
`formed. Thus, as shown in FIG. 3A, gate 18 of the ?eld
`effect transistor and dummy interconnection 44 are
`formed at the same time by selective etching. Then, in
`silicon substrate 11 are formed diffusion layers 14 and 15
`constituting a source/drain region of the ?eld effect
`transistor, a diffusion layer 17 of peripheral circuitry
`and a conductive diffusion layer 16 by ion implantation.
`As shown in FIG. 3B, an insulation ?lm layer 222 is
`formed by deposition of $102 by employing e.g., a CVD
`(Chemical Vapor Deposition) method. A sidewall insu
`lation ?lm 22 and a dummy interconnection sidewall
`insulation ?lm 26 as shown in FIG. 4A are formed by
`subjecting the entire surface of insulation ?lm layer 222
`to anisotropical etching. Then, as shown in FIG. 4B, a
`storage node layer 229 corresponding to a lower elec
`trode of a capacitor is formed, and a photoresist pattern
`129 for formation of a storage node 29 and a photoresist
`' pattern 130 for formation of a conductive polycrystal
`line silicon layer 30 (see FIG. 5A) are formed. Accord
`ingly, referring to FIG. 5A, storage node 29 and con
`50
`ductive polycrystalline silicon layer 30 are formed by
`selective etching.
`Then, as shown in FIG. SE, a capacitor insulation
`?lm layer 231 and a cell plate layer 232 corresponding
`to an upper electrode’of the capacitor are formed. After
`that, a photoresist pattern 132 is further formed, and a
`capacitor insulation film 31 and a cell plate 32 are
`formed by selective etching as shown in FIG. 6A. Thus,
`conductive polycrystalline silicon layer 30 remains un
`removed.
`'
`Referring then to FIG. 6B, an interlayer insulation
`layer 233 is formed, and a photoresist pattern 134 hav
`ing an opening portion where a contact hole is to be
`formed is formed. Then, as shown in FIG. 7A, an inter
`layer insulation ?lm 33 having contact holes 34, 35, 36
`and 37 formed therein is formed by selective etching.
`After that, referring to FIG. 7B, a polycrystalline sili
`con layer 238 and a tungsten silicide layer 239 are
`
`6
`formed to form bit lines over the entire surface. The
`formation of tungsten silicide layer 239 is carried out by
`first forming a tungsten layer on polycrystalline silicon
`layer 238 by sputtering or the like and then subjecting
`the tungsten layer to heat treatment and silicidation.
`A description will now be made on a photoresist
`mask for formation of bit lines by photolithography and
`selective etching, with reference to FIGS. 8A and 8B.
`FIGS. 8A and 8B are plan views showing a lay-out of
`the state where photoresist masks for formation of bit
`lines are patterned in the structure of FIG. 7B. All of
`photoresist masks 340, 343,440 and 443 shown in FIGS.
`8A and 8B are positive photoresist masks in which pho
`toresists in hatched portions are left. At that time, in
`order to retain superimposing margins upon exposure in
`a photolithography processing, it is necessary to obtain
`distances M0, M1 and M2, shown in FIGS. 8A and SE,
`to be not less than approximately 0.15 to 0.2 pm. The
`actual bit line pattern is a combination of pattern 340 of
`FIG. 8A and pattern 443 of FIG. 8B. Respective pat
`terns 343 and 440 shown in respective FIGS. 8A and 8B
`serve to cover the actual bit line pattern upon double
`exposure in photolithography processing. Photoresist is
`applied to the formed structure of FIG. 7B. Then, a
`resultant structure is exposed by using the photoresist
`masks of FIG. 8A and then exposed by using the photo
`resist masks of FIG. 8B. The order of the patterns of
`FIGS. 8A and 8B may be reverse.
`Through the above-described two exposure process
`ing steps, respective depths of focus corresponding to
`respective photoresist mask patterns 340 and 4-43 in the
`respective processing steps can be obtained. By a devel
`opment processing carried out after the end of such
`exposure processing steps, a desired photoresist pattern
`is formed, and by selective etching, bit line 40 formed of
`polycrystalline silicon layer 38 and tungsten silicide
`layer 39 and bit line 43 formed of polycrystalline silicon
`layer 41 and tungsten silicide layer 42 shown in FIGS.
`1A and 1B are formed.
`As has been described heretofore, according to the
`?rst embodiment, bit line 43 serving as a ?rst conduc
`tive interconnection layer and bit line 40 as a second
`conductive interconnection layer are formed, respec
`tively in a lower surface and a higher surface of the
`interlayer insulation film 33 which lower and higher
`surfaces are on opposite sides of the step-like portion of
`the interlayer insulation ?lm, and respective separate
`photoresist patterns undergo photolithography. Ac
`cordingly, even if the step-like portion of interlayer
`insulation ?lm 33 is larger than the depth of focus in
`photolithography, the photolithography for each of bit
`lines 43 and 40 can be made within the depth of focus,
`and hence a highly precise pattern formation in comply
`with the pattern of photoresist masks can be made.
`A second embodiment of the present invention will
`now be described with reference to FIGS. 9A and 9B.
`The second embodiment differs from the ?rst embodi
`ment in that the electrical connection of bit lines 40 and
`43 is made only by a conductive polycrystalline silicon
`layer 30 Without provision of a conductive diffusion
`layer 16 in the second embodiment, whereas it is made
`by conductive polycrystalline silicon layer 30 formed
`from the top surface of dummy interconnection 44 to
`the surface of silicon substrate 11 and by conductive
`diffusion layer 16.
`The second embodiment is effectively applied to a
`case where bit lines 40 and 43 serving as conductive
`interconnection layers are formed over the step-like
`
`55
`
`65
`
`NVIDIA Corp.
`Exhibit 1106
`Page 016
`
`

`

`10
`
`25
`
`30
`
`35
`
`5,441,916
`7
`portion of interlayer insulation ?lm 33 located on an
`isolation region 12. This embodiment has the same ef
`fect as that of the ?rst embodiment.
`A third embodiment of the present invention will
`now be described with reference to FIGS. 10A and
`10B. The third embodiment differs from the ?rst and
`second embodiments in that a conductive polycrystal
`line silicon layer 30 for electrically connecting bit lines
`40 and 43 extends also over the surface of a conductive
`diffusion layer 16 provided in the surface of silicon
`substrate 11 and that bit line 43 and conductive poly
`crystalline silicon layer 30 are connected through a
`contact hole on conductive diffusion layer 16.
`According to the third embodiment, contact resis
`tance can be further suppressed as compared to that in
`the case where conductive diffusion layer 16 and bit line
`43 are directly connected.
`As has been described heretofore, according to the
`foregoing respective embodiments, even if a conductive
`interconnection layer is formed on an interlayer insula
`20
`tion ?lm having a step-like portion larger than depth of
`focus so that it is formed over the step-like portion,
`respective conductive interconnection layers of lower
`and higher surfaces interposing the step-like portion
`therebetween are patterned by separate photolithogra
`phy processing steps, so that the respective conductive
`interconnection layers can be patterned within the
`depth of focus. Accordingly, conductive interconnec
`tion layers of desired patterns are precisely formed
`without being affected by the step-like portion, and
`conductive interconnections can be formed without any
`constriction or the like produced in a multi-layer struc
`ture with higher productivity.
`Although the present invention has been described
`and illustrated in detail, it is clearly understood that the
`same is by way of illustration and example only and is
`not to be taken by way of limitation, the spirit and scope
`of the present invention being limited only by the terms
`of the appended claims.
`What is claimed is:
`1. A method of manufacturing a semiconductor de
`vice, comprising the steps of:
`forming an interlayer insulation film having a step
`like portion on a substrate, wherein said step-like
`portion is de?ned by adjacent lower and higher
`surfaces of said interlayer insulation ?lm;
`depositing a conductive ?lm on said interlayer insula
`tion ?lm; and
`patterning said conductive ?lm and forming a ?rst
`conductive interconnection layer in said lower
`surface of said interlayer insulation ?lm and a sec
`ond conductive interconnection layer in said
`higher surface of said interlayer insulation ?lm,
`said ?rst and second conductive interconnection
`layer forming step comprising the steps of:
`forming a ?rst photoresist mask having a pattern
`covering all regions where said second conduc
`tive interconnection layer is to be formed, in
`addition to the same pattern as the pattern of said
`?rst conductive interconnection layer, and using
`said ?rst photoresist mask as an etching mask,
`and
`
`8
`forming a second photoresist mask having a pattern
`covering all regions where said ?rst conductive
`interconnection layer is to be formed, in addition
`to the same pattern as the pattern of said second
`conductive interconnection layer, and using said
`second photoresist mask as an etching mask.
`2. The method of claim 1, wherein said conductive
`?lm forming step comprises the steps of:
`forming a polycrystalline silicon layer,
`forming a tungsten layer on said polycrystalline sili
`con layer, and
`silicidizing said tungsten layer.
`3. The method of claim 1, wherein:
`said photoresist mask having the pattern covering all
`regions where said second conductive interconnec
`tion layer is to be formed in patterning of said ?rst
`conductive interconnection layer covers up to an
`outer region of at least 0.15 pm from the pattern of
`second conductive interconnection layer, and said
`photoresist mask 343 having the pattern covering
`all regions where said ?rst conductive interconnec
`tion layer is to be formed in patterning of the sec
`ond conductive interconnection layer covers up to
`an outer region of at least 0.15 um from the pattern
`of said ?rst conductive interconnection layer.
`4. A method of manufacturing a semiconductor de
`vice, comprising the steps of:
`forming a conductive layer in a region on a substrate;
`forming on said substrate an interlayer insulation ?lm
`having a step-like portion on said region of said
`conductive layer, wherein said step-like portion is
`de?ned by adjacent lower and higher surfaces of
`said interlayer insulation ?lm;
`forming a pair of contact holes in which a surface of
`said conductive layer becomes a bottom surface on
`the contact holes, on both a lower region and a
`higher region interposing said step-like portion
`therebetween in a region in the vicinity of said
`step-like portion of said interlayer insulation ?lm;
`and
`forming a ?rst conductive interconnection layer and
`a second conductive interconnection layer, respec
`tively on said lower surface and said higher surface
`of said interlayer insulation ?lm, including an inner
`surface of said contact hole pair.
`5. The method of claim 4, wherein said conductive
`layer forming step comprises the step of forming a con
`ductive polycrystalline silicon layer directly on a
`dummy interconnection having approximately the same
`height as that of said step-like portion formed on said
`substrate to extend over said substrate, wherein a
`contact hole for connecting said second conductive
`interconnection layer and said conductive layer therein
`is formed directly on said dummy interconnection.
`6. The method of claim 4, wherein said conductive
`layer forming step comprises the steps of:
`implanting impurities onto the surface of said sub
`strate and forming a conductive diffusive layer, and
`forming a conductive polycrystalline silicon layer
`connected to the surface of said conductive diffu
`sion layer.
`
`45
`
`60
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`* * * * *
`
`NVIDIA Corp.
`Exhibit 1106
`Page 017
`
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