United States Patent 1191
`Chen
`
`111111111 111111 1111111115 11111111 111 111 11111 lllll 11
`5,550,076
`Aug. 27, 1996
`
`[11] Patent Number:
`[45] Date of Patent:
`
`METHOD OF MANUFACTURE OF COAXIAL
`CAPACITOR FOR DRAM MEMORY CELL
`AND CELL MANUFACTURED THEREBY
`
`Primary Examiner-——H. Jey Tsai
`Attorney, Agent, or Firm—George O. Saile; Graham S.
`Jones, 11
`
`[54]
`
`[75]
`
`[73]
`
`[21]
`[22]
`[51]
`
`[58]
`
`Inventor: Chung-Zen Chen, Hsinchu, Taiwan
`_
`_
`_
`Asslgnec: Vanguard Internatmnal .
`Semlconducmr Corp" Hsmchu’ Talwan
`
`APPI- NO-I 526,363
`.
`_
`Sep' 11’ 1995
`Flled'
`Int. Cl.6 ........................... .. H01L 21/70; H01L 27/00
`US. Cl. .............. ..
`437/52; 437/60; 437/919
`Field of Search ................................ .. 437/4748, 52,
`437/60’ 919; 257/203’ 206_210
`
`References Cited
`
`US- PATENT DOCUMENTS
`5 049 957 9/1991 Inoue et al. ............................. .. 437/52
`5:053:351 10/1991 Fazan a a1_
`437/52
`5,084,405
`1/1992 Fazan et al. . . . . .
`. . . .. 437/52
`5,278,091
`1/1994 Fazan et a1.
`437/52
`5,346,844
`9/1994 Cho et al. ............................... .. 437/52
`
`ABSTRACT
`[57]
`A DRAM capacitor is formed over a device with FOX
`regions and device areas with S/D regions. Form a planariza
`tion silicon oxide layer over the device and FOX areas
`covered with an etch stop layer and a ?rst portion of a ?rst
`capacitor plate over the planarization layer, a contact open
`ing to the SID areas by etching through the ?rst capacitor
`layer and layers down to a S/D region. Form a second
`portion of a ?rst plate over the device and through the
`Contact Opening into electrical and mechanical Contact with
`one Of the 5/13 areas, the second P°m°I1 has “Posed
`sidewalls and a top surface extending above the surface of
`the device. Form sacri?cial spacers adjacent to the sidewalls
`of the second portion. Deposit a third portion of the ?rst
`plate over the device. Etch back the third portion down to the
`etch stop layer to expose the sacri?cial structure and remove
`the sacri?cial Smmmfc- Form an interconducwr dielemc
`layer and an upper capacitor plate extending between the
`second and third portions.
`
`23 Claims, 8 Drawing Sheets
`
`5O 38
`
`3 7 ’ 3 6 .3 7 ’
`
`.38
`
`34
`
`49~ »
`3 O
`23 -
`2 8 "1"
`26\- /
`2 4 N/
`1 4- ---
`-
`
`FOX
`
`?
`1 O
`
`/ z
`
`\
`
`R
`
`\%
`
`34
`
`\ 3 O
`
`/ /A/A
`N__
`
`7
`
`4 I
`
`S
`
`‘L
`I
`l
`I
`/
`I
`l
`I
`221 16 19 22c 20 24
`24- 24
`
`NVIDIA Corp.
`Exhibit 1105
`Page 001
`
`

`

`US.‘ Patent
`
`Aug. 27, 1996
`
`Sheet 1 of 8
`
`5,550,076
`
`37’ 36 37’
`
`38
`
`38
`
`34 7
`
`34
`
`I
`I
`l
`/
`I
`I
`221 241
`6 2422020
`7
`
`I
`24
`
`FIG.
`
`p [////////~/33
`///
`33w //
`(l\\\\\\\\‘k\\\\\\\\\\\\§M34
`‘all I
`
`‘M35
`
`30
`
`l
`l
`
`l
`l
`
`/
`
`30
`23 "
`28M
`24~_-/
`142.4
`FOX
`K
`1
`1
`1
`221 2416
`FIG. 2A
`
`I
`
`I
`I
`I /
`9228 20 24
`
`NVIDIA Corp.
`Exhibit 1105
`Page 002
`
`

`

`US. Patent
`
`Aug. 27, 1996
`
`Sheet 2 of 8
`
`5,550,076
`
`36 / //////% ///////
`:TL
`\%\\\\\\\\\\f 34
`30
`/
`30
`28x1’ I y \ 28
`2e» /
`/
`{/23
`24-~V
`I m \
`jze
`14 L FOX
`'
`'
`N-
`18
`
`23 -——
`
`N-
`
`s
`
`D
`
`J
`
`"O
`
`I
`I
`/
`/
`I
`I
`221 l162|419 22G 20 24
`
`FIG. 2B
`
`-
`
`3O
`
`26
`
`/
`
`‘
`
`/
`
`7%
`355i
`%\\\\\\\\\\§ 34
`34
`53:; \ %
`24~—-/
`//,//4
`r/
`SI KW
`
`14
`
`FOX
`
`N-— I
`
`\
`
`N-
`
`W
`f
`P
`10
`F
`I
`/
`I! l
`I
`/
`221 241624]9 22G 20 24
`FIG. 2C
`
`23
`
`18
`
`F/12
`
`NVIDIA Corp.
`Exhibit 1105
`Page 003
`
`

`

`US. Patent
`
`Aug. 27, 1996
`
`Sheet 3 of 8
`
`5,550,076
`
`37 36 37
`
`i\\\\\Y-'
`
`5o
`
`28
`25
`
`/
`
`N_
`
`26
`18
`
`12
`
`J
`F”
`
`23——-—
`28A
`26
`
`/
`
`24—~-/
`14 L FOX
`j
`?
`10
`
`__
`
`/////2\
`'
`I
`S
`D
`7
`P
`I
`I
`/
`\
`1
`I
`l
`/
`22124162419 22G 20 24
`F I G . 2D
`37 3s :57
`
`\\\\\\\\\$ 33
`
`‘1
`
`iii/FOX
`P
`h
`I
`I
`l
`/
`1
`I
`221214164439 22@ 20 24
`10
`FIG. 2E
`
`s
`
`[
`
`D
`
`K
`
`N..
`
`/%2
`if”
`
`NVIDIA Corp.
`Exhibit 1105
`Page 004
`
`

`

`US. Patent
`
`Aug. 27, 1996
`
`Sheet 4 of 8
`
`5,550,076
`
`38 3(7
`3x6 3f 38
`7 W
`é\ \\\\\\\\§ 3;;
`E52
`
`F"
`
`N- S
`
`f [
`
`D
`
`N-
`
`K
`
`18 .
`
`if’ 12
`
`3;:
`551/1”
`
`14\]
`
`/r
`
`10
`
`1
`I
`I /II/ /
`22124162419 220 20 24
`FIG. 2F
`37' 36 37’
`
`“Ll
`
`%x\\\\l, s
`
`3O
`23-"
`
`26
`
`/
`
`24/
`
`14‘ FOX
`
`1O
`
`71
`\p_.
`2221 2/41'62L?9/ 22G 20 24
`FIG. 2C
`
`D
`
`N“
`
`8
`
`J 12
`
`NVIDIA Corp.
`Exhibit 1105
`Page 005
`
`

`

`US. Patent
`
`Aug. 27, 1996
`
`Sheet 5 0f 8
`
`5,550,076
`
`37' .36 37’
`
`50
`
`34
`
`\
`§\
`
`-
`
`49
`30
`23—-—
`
`26\-_
`
`, /
`
`34
`
`28
`
`18
`
`F112
`
`NVIDIA Corp.
`Exhibit 1105
`Page 006
`
`

`

`US. Patent
`
`Aug. 27, 1996
`
`Sheet 6 of 8
`
`5,550,076
`
`I
`I
`/'\ ’
`22I241624]9 22G 20 24
`FIG. 4A
`
`37 36 37
`
`34
`
`34
`
`2,21 2/41
`/
`\
`I
`/
`I
`I
`624]9 22G 20 24
`419
`
`FIG.
`
`12
`
`NVIDIA Corp.
`Exhibit 1105
`Page 007
`
`

`

`US. Patent
`
`Aug. 27, 1996
`
`Sheet 7 of 8
`
`5,550,076
`
`38
`
`37 36 37
`\
`
`38 /
`\\l 7,34
`
`2 r \\\\\\\\>
`
`Mj
`
`N- s
`
`>0 a;
`
`/ I
`
`N-—
`
`18
`
`I
`l
`/
`/
`/l l
`221 241624]9 22G 20 24
`FIG. 4C
`
`37 36 37
`
`L
`
`38
`
`3O
`23
`28
`26
`24
`14
`
`W
`
`10
`
`5O
`
`28
`23
`26
`18
`
`12
`
`p_
`
`221 241624]9 22G 20 24
`FIG. 4D
`
`NVIDIA Corp.
`Exhibit 1105
`Page 008
`
`

`

`US. Patent
`
`Aug. 27, 1996
`
`Sheet 8 of 8
`
`5,550,076
`
`37’36 37’
`
`3O
`53
`26
`24
`14
`
`1O
`
`22124162419 22G 20 24
`
`FIG. 4E_
`
`5O
`
`49
`3O
`28
`23
`26
`18
`
`NVIDIA Corp.
`Exhibit 1105
`Page 009
`
`

`

`5,550,076
`
`1
`METHOD OF MANUFACTURE OF COAXIAL
`CAPACITOR FOR DRAM MEMORY CELL
`AND CELL MANUFACTURED THEREBY
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`This invention relates to the process of manufacture of
`integrated circuit (IC) semiconductor devices and more
`particularly to manufacture of coaxial capacitor structures in
`dynamic random access memory (DRAM) devices and the
`like.
`2. Description of Related Art
`U.S. Pat. No. 5,084,405 of Fazan et al for “Process to
`Fabricate a Double Ring Stacked Cell Structure" shows a
`double ring structure, so there are four sidewalls on the top
`of the bottom polysilicon layer. The process of that patent
`provides node contact etching after silicon layer 41 and
`silicon nitride layer 42, as shown in FIG. 5.
`See US. Pat. No. 5,346,844 of Cho et al for “Method for
`Fabricating Semiconductor Memory Device.”
`
`SUMMARY OF THE INVENTION
`
`25
`
`In accordance with this invention, there are only three
`sidewalls on the top of the bottom layer of polysilicon, since
`the inner ring of the prior art has been transformed into a
`solid “bar-like” structure.
`In the process of this invention, node contact etching is
`done after silicon dioxide, silicon nitride, the bottom portion
`of the lower capacitor plate layer and a TEOS glass layer.
`The steps which follow are altered by these initial stages of
`the process.
`In accordance with this invention, a method for fabricat~
`ing a dynamic random access memory has a capacitor
`involves the following steps. Selectively form ?eld oxide
`areas on the surface of a semiconductor substrate while
`leaving device areas for fabrication of ?eld effect devices
`has gate electrode structures and source/drain structures.
`Form a gate dielectric layer on the substrate in the device
`areas. Deposit a ?rst layer of polysilicon on the ?eld oxide
`areas and the device areas. Remove portions of the ?rst
`polysilicon layer while leaving portions thereof for the gate
`structure in the device areas, and portions over the ?eld
`oxide areas. Form the source/drain structures within the
`device areas of the semiconductor substrate associated with
`the gate structures. Form a planarization silicon oxide layer
`over the device and ?eld oxide areas. Form an etch stop layer
`over the planarization layer. Form a ?rst portion of a ?rst
`capacitor plate doped polysilicon layer over the planariza
`tion layer. Form a contact opening to the source/drain
`structures by etching through the ?rst capacitor layer and
`layers therebelow down to a the source/drain region. Form
`a second portion of a ?rst capacitor plate comprising a doped
`polysilicon layer over the device and through the contact
`opening into electrical and mechanical contact with one of
`the source/drain structures, the second portion has exposed
`sidewalls and a top surface extending above the surface of
`the device. Form sacri?cial spacer structures adjacent to the
`sidewalls of the second portion. Deposit a third portion of
`the ?rst capacitor plate polysilicon layer over the device
`including the sacri?cial structures and the ?rst portion and
`the second portion into electrical and mechanical contact
`therewith, and providing doping thereof. Etch back the third
`portion of the ?rst capacitor plate down to the etch stop layer
`and exposing the sacri?cial structure. Etch away the sacrie
`
`45
`
`50
`
`60
`
`65
`
`2
`?cial structure. Form a blanket interconduetor dielectric
`layer over the device on the exposed surfaces of the device
`providing an exposed surface of the interconduetor dielectric
`layer. Deposit an upper capacitor plate over the intercon
`ductor dielectric layer, the upper plate extending between
`the second and third portions.
`Preferably, the thickness of the ?rst portion of the lower
`capacitor plate layer is between about 500 A and about 1,000
`A; the thickness of the second portion of the lower capacitor
`plate layer is between about 1,000 A and about 3,000 A; and
`the thickness ‘of the third portion capacitor plate layer is
`between about 500 A and about 2,000 A.
`Preferably, the etch stop layer is etched away before
`forming the interconduetor dielectric layer.
`Preferably, following etching away the etch stop layer, the
`interconduetor dielectric and the top plate electrode are
`deposited between the ?rst portion and the planarization
`layer.
`Preferably, following formation of the sacri?cial spacer
`structures the portion of the ?rst portion not protected
`thereby is etched away.
`Preferably, the etch stop layer is wet etched away before
`forming the interconduetor dielectric layer.
`Preferably, following wet etching of the etch stop layer,
`the interconduetor dielectric and the top plate electrode are
`deposited between the ?rst portion and the planarization
`layer.
`In accordance with another aspect of this invention a
`method for fabricating a dynamic random access memory
`has a capacitor comprises:
`Selectively form ?eld oxide areas on the surface of a
`semiconductor substrate while leaving device areas for
`fabrication of ?eld effect devices has gate electrode struc
`tures and source/drain structures.
`Form a gate dielectric layer on the substrate in the device
`areas.
`Deposit a ?rst layer of polysilicon on the the ?eld oxide
`areas and the device areas.
`Remove portions of the ?rst polysilicon layer while
`leaving portions thereof for the gate structure in the device
`areas, and portions over the ?eld oxide areas.
`Form the source/drain structures within the device areas
`of the semiconductor substrate associated with the gate
`structures.
`Form a planarization silicon oxide layer over the device
`and ?eld oxide areas.
`Form an etch stop layer over the planarization layer.
`Form a ?rst portion of a lower capacitor plate doped
`polysilicon layer over the planarization layer has a thickness
`between about 500 A and about 1,000 A,
`Form a glass layer formed by a TEOS process on the first
`portion has a thickness between about 5,000 A and about
`10,000 A;
`Form a contact opening to the source/drain structures by
`etching through the glass layer, the ?rst capacitor layer and
`layers therebelow down to a the source/drain region.
`Form a second portion of a ?rst capacitor plate compris
`ing a doped polysilicon layer over the device and through the
`contact opening into electrical and mechanical contact with
`one of the source/drain structures, the second portion has
`exposed sidewalls and a top surface extending above the
`surface of the device.
`Form sacri?cial spacer structures adjacent to the sidewalls
`of the second portion.
`
`NVIDIA Corp.
`Exhibit 1105
`Page 010
`
`

`

`5,550,076
`
`3
`Deposit a third portion of the ?rst capacitor plate doped
`polysilicon layer over the device including the sacri?cial
`structures and the ?rst portion and the second portion into
`electrical and mechanical contact therewith.
`Etch back the third portion of the ?rst capacitor plate
`down to the etch stop layer and exposing the sacri?cial
`structure.
`Etch away the sacri?cial structure.
`Form a blanket interconductor NO dielectric layer over
`the device on the exposed surfaces of the device providing
`an exposed surface of the interconductor dielectric layer.
`Deposit an upper capacitor plate extending between the
`second and third portions, the upper plate comprising a
`doped polysilicon layer over the interconductor NO dielec
`tric layer.
`Preferably, the thickness of the ?rst portion of the lower
`capacitor plate layer is between about 500 A and about 1,000
`A; the thickness of the second portion of the lower capacitor
`plate layer is between about 1,000 A and about 3,000 A; and
`the thickness of the third portion capacitor plate layer is
`between about 500 A and about 2,000 A.
`Preferably, the etch stop layer is etched away before
`forming the interconductor dielectric layer.
`Preferably, following etching away the etch stop layer, the
`interconductor dielectric and the top plate electrode are
`deposited between the ?rst portion and the planarization
`layer.
`Preferably, following formation of the sacri?cial spacer
`structures the portion of the ?rst portion not protected
`thereby is etched
`Preferably, the etch stop layer is wet etched away before
`forming the interconductor dielectric layer.
`Preferably, following wet etching of the etch stop layer,
`the interconductor dielectric and the top plate electrode are
`deposited between the ?rst portion and the planarization
`layer.
`0 Preferably, the etch stop layer has a thickness of about 500
`A; and/or the ?rst portion has a thickness between about 500
`A and about 1,000 A.
`In accordance with still another aspect of this invention,
`a dynamic random access memory device has a capacitor
`formed thereon. There are ?eld oxide areas on the surface of
`a semiconductor substrate with device areas for ?eld effect
`devices has gate structures and source/drain structures, with
`a gate dielectric layer on the substrate in the device areas.
`There is a ?rst layer of polysilicon on the the ?eld oxide
`areas and the device areas patterned into the gate structure
`in the device areas, and portions over the ?eld oxide areas.
`The source/drain structures are formed within the device
`areas of the semiconductor substrate associated with the gate
`structures. A ?rst oxide layer is formed over the device and
`?eld oxide areas. A planarization silicon oxide layer is
`formed over the device and ?eld oxide areas. The capacitor
`is formed with a contact opening to a source/drain structure
`etched through the device. A ?rst portion of a ?rst capacitor
`plate polysilicon layer is formed over the planarization layer.
`A second portion of a ?rst capacitor plate comprises a
`polysilicon layer over the device which extends down
`through the contact opening into electrical and mechanical
`contact with one of the source/drain structures and doping
`the second portion. The second portion has exposed side
`walls and a top surface extending above the surface of the
`device. A third portion of the ?rst capacitor plate polysilicon
`layer is formed over the device the ?rst portion and the
`second portion into electrical and mechanical contact there
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`with, and providing doping thereof spaced away from the
`sidewalls providing a space therebetween from the top of the
`device. A blanket interconductor dielectric layer is formed
`over the exposed surfaces of the lower plate the device
`providing an exposed surface of the interconductor dielectric
`layer. An upper capacitor plate is located over the intercon
`ductor dielectric layer extending between the second and
`third portions. An etch stop layer is sandwiched between the
`planarization layer and the ?rst portion.
`Preferably, the etch stop layer has a thickness of about 500
`
`Preferably, the interconductor dielectric layer and the
`upper plate reach between the ?rst portion and the planariza
`tion layer.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The foregoing and other aspects and advantages of this
`invention are explained and described below with reference
`to the accompanying drawings, in which:
`FIG. 1 shows a device which both incorporates I the
`features of this invention and which has been manufactured
`in accordance with the method of this invention.
`FIGS. 2A-2H illustrate a method of manufacture of the
`device of FIG. 1 in accordance with this invention.
`v
`FIG. 3 shows a modi?cation of the preferred embodiment
`of the invention shown in FIG. 1.
`FIGS. 4A-4E shows a set of process steps which are an
`alternative to the process of FIGS. 2E—2H.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`FIG. 1 shows an embodiment of a device which both
`incorporates the features of this invention and which has
`been manufactured in accordance with the method of this
`invention. The method of manufacture of the device of FIG.
`1 is described below with reference to FIGS. 2A-2H. FIG.
`3 and FIG. 4E show modi?cations of the preferred embodi
`ment of the invention shown in FIG. 1.
`The DRAM device 10 is shown with a ?eld oxide (FOX)
`region 14 and a silicon dioxide gate oxide layer 20 formed
`on the surface of P-type silicon substrate 12. A ?rst poly
`silicon layer has been formed over both the gate oxide layer
`20 and FOX region 14 and patterned into a gate electrode
`22G over layer 20 and interconnector 221 on region 14.
`The semiconductor substrate 12 is preferably composed
`of silicon having a (100) crystallographic orientation. The
`silicon 12 remains as a mesa surrounded by the sunken
`silicon dioxide or ?eld oxide (FOX) pattern 14.
`The gate electrode 226 is provided for a transistor 19 seen
`in FIG. 2A and a conductor (or interconnector) structure 221
`is provided on the surfaces of FOX 14 or elsewhere as seen
`in FIG. 2A to provide interconnections to other circuits.
`A P channel FET integrated circuit device could also be
`formed by simply’ substituting opposite doping types in
`place of those employed in the N channel embodiment
`shown in FIGS. 2A to 2H. Also, a CMOS FET could be
`formed, in a similar way, by making both N channel and P
`channel devices upon the same substrate.
`Then N- dopant ions are ion implanted to form N-lightly
`doped source/drain regions 16 and 18 in the portions of
`substrate 12 beneath the portion of the surface of substrate
`12 which are not covered by control electrode 226 which
`
`NVIDIA Corp.
`Exhibit 1105
`Page 011
`
`

`

`5,550,076
`
`5
`acts as a self-aligned mask and the FOX regions 14 which
`also mask the portions of substrate 12 therebelow.
`A silicon dioxide structure 23 was formed on the ?rst
`polysilicon layer interconnector 221 and gate electrode 22G.
`Dielectric spacers 24 were formed adjacent to gate elec
`trode 22G and interconnector 22I.
`A BPSG layer 28, which has been planarized by a
`conventional heating process, covers the device prior to
`formation of plug 36.
`A thin ?lm silicon nitride Si3N4 layer 30 covers the BPSG
`layer 28.
`A bottom polysilicon (poly 2-1) layer 34 was formed
`having a thickness of about 500 A.
`The next layer is a silicon dioxide layer 35 formed by a
`conventional TEOS process described above, and having a
`thickness between about 5,000 A and 10,000 A thick, and
`preferably about 5,000 A thick.
`A node contact opening has been opened through the
`layers 30, 28, etc. down to the N- region 16.
`
`20
`
`Deposition of Node Contact Layer
`
`25
`
`35
`
`45
`
`50
`
`A blanket polysilicon layer 36 (P2-2) was deposited over
`the device 10 reaching down into the opening etched pre
`viously. Polysilicon layer 36 (P2-2) is preferably between
`about 1,000 A and about 3,000 A thick. The blanket poly
`silicon layer 36 (P2-2) was doped and etched to form a
`polysilicon plug 36 extending above the layers 28 and 29.
`TEOS glass spacer spacers 37 have been formed adjacent
`to the sidewalls of the plug 36.
`A blanket polysilicon layer 38 (P2-3) has been deposited
`over the device 10 in electrical and mechanical contact with
`the plug 36 (P22) and with the exposed surface of bottom
`polysilicon (P2-1) layer 34.
`Polysilicon layer 38 (P23) preferably has a thickness
`between about 500 A and about 2,000 A. The blanket
`polysilicon layer 38 (P2-3) has been doped.
`The polysilicon layer 38 (P2-3) has been etched back with
`the silicon nitride layer 30 serving as an etch stop layer. The
`result is a pair of upright polysilicon elements 38 adjacent to
`the spacers 37 with a similar cross sectional shape to the
`spacers 37.
`The device 10 is shown after sacri?cial spacers have been
`etched away to form openings 37' between the upright
`polysilicon elements 38 and the polysilicon plug 36.
`If at this point the silicon nitride layer has been wet etched
`away, the bottom plate of the crown can be enlarged to
`further increase the capacitor area.
`The key feature here is that the central plug or bar 36 is
`superior when we shrink the cap size rather than employing
`another narrow ring as has been done in the prior art.
`A conventional thin Nitride Oxide (NO) layer 49 of
`interconductor dielectric is formed next to permit formation
`electrical insulation from the upper capacitor plate 50. Layer
`49 has a thickness of about 20-50 A.
`An in-situ polysilicon layer 50 forming the top plate of the
`DRAM capacitor has been deposited on the top of the
`surface of NO layer 49 to serve as a top plate electrode of
`the capacitor. Layer 50 is between about 500 A and about
`1,500 A thick.
`
`Process of Manufacture of Preferred Embodiment
`
`65
`
`FIG. 2A illustrates the results of the initial stages of
`manufacture of a DRAM structure upon which the new
`
`6
`capacitor structure of this invention will be fabricated. A
`DRAM device 10 in an early stages of manufacture is shown
`with a ?eld oxide (FOX) region 14 and a silicon dioxide gate
`oxide layer 20 formed on the surface of P-type silicon
`substrate 12 by a conventional process. A ?rst blanket
`polysilicon layer has been formed over the gate oxide layer
`20 and FOX region 14. (Later in the process, the blanket
`polysilicon layer is patterned to form a gate electrode 22G
`over gate elecnode 20 and an interconnector 221 over FOX
`region 14, as explained below.)
`The semiconductor substrate 12 is preferably composed
`of silicon having a (100) crystallographic orientation. In an
`effort to simplify the description and the drawings the
`dielectric isolation between devices has been only partially
`shown and will not be described in detail, as it is conven
`tional. For example, one method is described by E. Kooi in
`his US. Pat. No. 3,970,486 wherein certain selected surface
`portions of a silicon semiconductor substrate is masked
`against oxidation, and then the exposed unmasked surface is
`oxidized to grow a thermal oxide which in effect sinks into
`the silicon surface at the unmasked areas. The masked
`silicon remains as a mesa surrounded by the sunken silicon
`dioxide or ?eld oxide (FOX) pattern 14.
`'
`Then semiconductor devices can be provided in the
`silicon mesas according to the following processes.
`The surface of the silicon substrate 12 is thermally
`oxidized to form the desired thickness of gate oxide layer 20
`having a preferred thickness between about 80 A to 200 A.
`Next, the ?rst polysilicon layer (later to be formed into gate
`electrode 22G and conductor 221) is blanket deposited by
`LPCVD (Low Pressure Chemical Vapor Deposition)
`method. The preferred thickness of the ?rst polysilicon layer
`is between about 2,000 A and about 4,000 A. The ?rst
`polysilicon layer can be doped by several methods. One
`method includes ion implanting with phosphorous or arsenic
`ions with a dose of between 5 E 15 ions/cm2 and 10 E 15
`ions/cm2 at an energy of between 20 keV and 60 keV.
`Alternatively the polysilicon layer is doped with phosphorus
`oxychloride at a temperature of about 900° C.
`The device 10 is shown after a blanket ?rst polysilicon
`layer has been deposited upon device 10. Then a blanket
`silicon dioxide (SiOZ) layer was formed immediately after
`the blanket ?rst polysilicon layer. Next a mask was formed
`to de?ne a pattern and etch back the blanket silicon dioxide
`and ?rst polysilicon layer forming polysilicon interconnec
`tor 221 over the FOX region 14 and polysilicon gate elec
`trode 22G over the gate oxide 20. Layers 23 are formed over
`the interconnector 221 and the gate electrode 22G.
`Preferred conditions for forming the dielectric structures
`23 are LPCVD deposition of TEOS or silane based CVD
`silicon oxide deposition at about 600° C. to 900° C. The
`preferred thickness of dielectric layer 20 is between about
`500 to 2500 A and a preferred thickness of about 1500 A.
`The etching of. the ?rst polysilicon layer has been accom
`plished in accordance with the well known state of the art.
`The portions of ?rst polysilicon layer unprotected by pho~
`toresist mask segments have been removed by anisotropic
`etching techniques, as is conventional in the art to provide
`a desired pattern. The etching leaves the gate electrode 22G
`for a transistor 19 seen in FIG. 2A and the conductor (or
`interconnector) structure 221 on the FOX 14 surfaces or
`elsewhere as seen in FIG. 2A.
`The source/drain structure of the MOSFET 19 is then
`formed by steps which lead to the formation of an N channel
`FET integrated circuit device. However, it is well under
`stood by those skilled in the art that a P channel FET
`
`NVIDIA Corp.
`Exhibit 1105
`Page 012
`
`

`

`5,550,076
`
`7
`integrated circuit device could also be formed by simply
`substituting opposite doping types in place of those
`employed in the N channel embodiment shown in FIGS. 2A
`to 2H. Also, a CMOS FET could be formed, in a similar way,
`by making both N channel and P channel devices upon the
`same substrate.
`N- dopant ions have been ion implanted to form N -lightly
`doped source/drain regions 16 and 18 in the portions of
`substrate 12 beneath the portion of the surface of substrate
`12 which are not covered by control electrode 22G which
`acts as a self-aligned mask and the FOX regions 14 which
`also mask the portions of substrate 12 therebelow. Litho
`graphic masks (not shown) may be required to protect the
`areas not to be subjected to that particular N- ion implan
`tation. The formation of the lithographic masks is done by
`conventional lithography and etching techniques. The
`N-lightly doped drain implantation is done with, for
`example, 2phosphorous p31 at a dose of between 1 E 13
`atoms/cm and 10 E 13 atoms/cm2 and with an energy of
`between about 30 keV and about 80 keV.
`Next, a blanket silicon dioxide spacer layer has been
`formed on the device 10 in the conventional manner. A low
`temperature silicon oxide deposition is preferred, such as
`through the chemical vapor deposition of tetraethoxysilane
`(TEOS) at a temperature in the range of between about 650°
`C. and about 900° C. Other silicon oxide deposition methods
`include silane based LPCVD. The thickness of the dielectric
`silicon dioxide spacer layer is between about 1,000 A and
`2,000 A, and preferably about 1,500 A.
`Then dielectric spacers are formed from the blanket
`silicon dioxide spacer layer by a process of anisotropic
`etching of the spacer layer producing a set of dielectric
`spacers 24 on the sidewalls of the gate electrode 22G and
`conductor structure 221. The preferred process of anisotropic
`etching employs a conventional reactive ion etching ambient
`as will be well understood by those skilled in the art.
`Then a blanket silicon dioxide layer 26 is formed by
`TEOS (Cl-TEOS.) A low temperature silicon oxide depo
`sition is preferred, such as through the chemical vapor
`deposition of tetraethoxysilane (TEOS) at a temperature in
`the range of between about 650° C. and about 900° C. The
`thickness of the dielectric silicon dioxide spacer layer is
`between about 1,000 A and 2,000 A thick, and preferably
`about 1,500 A thick.
`Next, follow the steps of blanket deposition of a conven
`tional BPSG layer 28, heating the device 10 to cause BPSG
`layer 28 to ?ow in the conventional process. The BPSG layer
`28 is deposited between about 5,000 A and 10,000 A thick,
`and preferably about 5,000 A thick. Then the BPSG layer 28
`is etched back to between about 3,000 A and 5,000 A thick,
`and preferably about 4,000 A thick to reduce topography, i.e.
`planarize the surface of the BPSG layer 28 so that it has a
`high degree of ?atness.
`Subsequently, the device is coated with a thin ?lm silicon
`nitride Si3N4 layer 30 having a thickness of about 200 A.
`The Si3N4 layer 30 is formed by the LPCVD method. The
`purpose of having Si3N4 layer 30 is to provide an interface
`between the BPSG layer 28 and polysilicon layer 34 which
`is required because it is used as an etch stop layer in the
`following SiO2 etch step to protect the underlying oxide.
`Next, the bottom polysilicon (poly 2-1) layer 34 is formed
`having a thickness of between about 500 A and about 1000
`A.
`The next layer is a silicon dioxide layer 35 formed by a
`conventional TEOS process described above, and having a
`thickness between about 2,000 A and 10,000 A thick, and
`preferably about 5,000 A thick.
`
`10
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`55
`
`60
`
`65
`
`8
`Finally a node contact photoresist mask 33 with an
`opening 33‘ centered over the source/drain region 16 of
`transistor 19 is applied over the device 10 to prepare for
`etching a node contact through layers 35, 34, 30, 28, and 26
`down to the surface of source/drain region 16 of transistor
`19.
`FIG. 2A shows the device 10 with the node contact
`opening 33" described above shown in phantom where it is
`to be etched by a process of etching. The process used is
`selected from the group consisting of RIE, CVD, APCVD,
`and LPCVD, using a gas selected from the group consisting
`of CF4 and C12 gases in a low pressure chamber.
`A series of more than one etching process is required to
`go through these layers, with one step for the silicon dioxide,
`one step for the polysilicon, and one for the silicon nitride.
`Then the mask 33 is removed leaving the TEOS glass
`layer 35 with the opening 33" extending therethrough down‘
`to N-region 16.
`Deposition of Node Contact Layer
`
`A blanket polysilicon layer 36 (P2-2) is deposited over the
`device 10 reaching down into the opening 33" etched
`previously. Polysilicon layer 36 (P2-2) is preferably blanket
`deposited by an LPCVD (Low Pressure Chemical Vapor
`Deposition) method. The preferred thickness of the blanket
`polysilicon layer is between about 1,000 A and about 3,000
`A thick.
`The blanket polysilicon layer 36 (P2-2) can be doped by
`several methods. One method includes ion implanting with
`phosphorous or arsenic ions with a dose of between 5 E 15
`ions/cm2 and 10 E 15 ions/cm2 at an energy of between 20
`keV and 60 keV. Alternatively the polysilicon layer is doped
`with phosphorus oxychloride at a temperature of about 900°
`C. The deep portion of polysilicon (p2-2) layer 36 doped at
`the bottom of hole 33" by diifusion of the dopant.
`FIG. 2C shows the device of FIG. 2B after the polysilicon
`layer 36 (P2-2) has been etched back to form a polysilicon
`plug within the layer 35.
`FIG. 2D shows the device of FIG. 2C after the TEOS
`glass layer 35 has been wet etched to remove the layer 35
`completely. The wet etchant is used is conventional buffered
`hydrogen ?uoride (HE)
`After etching is complete, the etchant is ?ushed or
`removed from the surface with deionized water cleaning.
`Then a blanket spacer layer (not shown) of TEOS glass is
`formed one of the processes described above with a thick
`ness between about 500 A and 2,500 A thick, and preferably
`about 1,000 A thick.
`Next, the blanket TEOS glass spacer layer is etched to
`form spacers 37 adjacent to the sidewalls of the plug 36. The
`etching is performed by a conventional process of anisotro
`pic etching of the spacer layer produces the dielectric
`spacers 37. The preferred process of anisotropic etching
`employs a conventional reactive ion etching ambient gas
`selected from the group consisting of methane gas (CF4) and
`oxygen gas (02). as will be well understood by those skilled
`in the art.
`FIG. 2E shows the device of FIG. 2D after the blanket
`polysilicon layer 38 (P2-3) has been deposited over the
`device 10 in electrical and mechanical contact with the plug
`36 (P2-2) and with the exposed surface of bottom polysili
`con (P2-1) layer 34, aside from the spacers 37, which are
`temporarily buried under the layer 38.
`Polysilicon layer 38 (P2-3) is preferably blanket deposited
`by LPCVD (Low Pressure Chem