`
`
`
`
`
`
`
`(51) Int. Cl.5
`H01l 21/336
` 21/027
` 29/784
`
`
`
`
`(19) Japan Patent Office (JP)
`(12) Japanese Unexamined Patent
`Application Publication (A)
`Identification codes
`JPO file number
`
`(11) Japanese Unexamined Patent
`Application Publication Number
`H4-63437
`
`(43) Publication date 28 Feb 1992
`
`
`
`
`
`
`
` 301 Z
`8422-4M H01L 29/78
` 301 Z
`7352-4M 21/30
` 301 P
`7352-4M
`Examination request: None Number of claims: 1 (Total of 12 pages)
`
`(54) Title of the invention
`
`
`(72) Inventor
`
`(71) Applicant
`(74) Agent
`
`SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
`(21) Japanese Patent Application
`H2-177022
`(22) Date of Application
`July 2, 1990
`Michihiro Yamada
`c/o Mitsubishi Electric Co., Ltd. LSI Research Lab
`4-1 Mizuhara, Itami-shi, Hyogo-ken
`2-2-3 Marunouchi, Chiyoda-ku, Tokyo-to
`and 2 others
`
`Mitsubishi Electric Co., Ltd.
`Masuo Oiwa, patent attorney
`
`
`
`
`SPECIFICATION
`
`
`1. Title of the Invention
`
`Semiconductor Integrated Circuit Device
`2. Claims
`A semiconductor integrated circuit device in
`(1)
`which a plurality of field effect transistors having one or a
`plurality of gate electrodes are formed in a mixed manner,
`wherein
`dummy patterns are formed in locations outside
`
`the gate electrodes of
`the field effect
`transistors a
`predetermined distance from the gate electrodes, positioned
`parallel thereto, and made from an identical material.
`3. Detailed Description of the Invention
`[Industrial Field of Use]
`
`The present invention relates to a semiconductor
`integrated circuit device in which a plurality of field effect
`transistors such as MOS-FETs are formed in a mixed
`manner, and more particularly relates to a technology for
`making channel lengths in the mixed-formation field effect
`transistors uniform.
`[Prior Art]
`
`
`
`The best-known conventional example of this
`
`type of semiconductor integrated circuit device is a MOS
`integrated circuit configured by a plurality of fine
`MOS-FETs. As such, in the description of the present
`invention, the semiconductor integrated circuit device is a
`MOS integrated circuit device, and the MOS integrated
`circuit device is configured by a plurality of n-channel
`MOS-FETs.
`
`MOS-FETs come in two types, a single gate
`electrode type as shown in FIG. 6(a) and (b) which is
`provided with one gate electrode and has a short channel
`length, and a multiple gate electrode type as shown in FIG.
`8(a) and (b) which is provided with a plurality of gate
`electrodes and has a long channel length. Normally in a
`general MOS integrated circuit device MOS-FETs of the
`single gate electrode type and multiple gate electrode type
`are formed on one chip in a mixed manner. Accordingly, in
`the following description, a single gate electrode MOS-FET
`is described first and then a multiple gate electrode type is
`described.
`
`
`
`
`
`
`
`– 207 –
`
`NVIDIA Corp.
`Exhibit 1104
`Page 001
`
`

`

`
`
`FIG. 6(a) is a plan view showing a schematic
`
`structure of a single gate electrode n-channel
`type
`MOS-FET in the middle of being fabricated, and FIG. 6(b)
`is a cross-sectional view showing a sectional structure along
`line B-B in FIG. 6(a). Reference numeral 1 in these
`drawings is a p-type silicon substrate, 2 is a device
`separation insulation film, 3 is a gate insulation film
`covering a MOS-FET channel, 4 is a gate electrode thereof,
`and 5 is an interlayer insulation film covering the device
`separation insulation film 2 and the gate electrode 4.
`Reference numerals 6 and 7 are a source and drain region of
`the MOS-FET which are n+-type. Electrical connection of
`the source and drain regions 6 and 7 is made via contact
`holes 8 and 9 formed in the interlayer insulation film 5.
`Reference numeral 10 is a contact hole for making an
`electrical connection of the gate electrode 4, 11 is a field
`pattern showing boundaries of
`the device separation
`insulation film 2, and L1 shows a pattern width of the gate
`electrode 4 which determines the channel length of the
`MOS-FET.
`
`
`The order of fabrication of this MOS-FET is
`
`described based on cross-sectional views of steps shown in
`FIG. 7(a) to (e).
`
`To start, an insulation film 12, which will serve
`as the device separation insulation film 2 and the gate
`insulation film 3, is formed on a surface of the silicon
`substrate 1, and then a polysilicon film 13 is formed
`covering the entire surface thereof (see FIG. 7(a)). Next, a
`positive (or negative type) photoresist is applied, covering
`the entire surface of the polysilicon film 13. Only an
`unexposable region 14a of a photoresist film 14 needed to
`form the gate electrode 4 is masked. Light is shined on an
`exposure region 14b of the photoresist film 14 which is not
`masked, using a reduced projection exposure device or the
`like, to expose that region (see FIG. 7(b)). After exposure is
`finished developing is performed, and if the photoresist film
`14 is positive, only the unexposable region 14a is left on the
`polysilicon film 13 (see FIG. 7(c)). The pattern width L1 (R)
`of the unexposable region 14a is a major factor in
`determining the channel length of the MOS-FET.
`
`Next, anisotropic etching, such as reactive ion
`etching, is performed, using the remaining unexposable
`region 14a as a mask, to remove unneeded portions of the
`polysilicon film 13. The polysilicon film 13 covered by the
`unexposable region 14a is partially left behind, thereby
`forming the gate electrode 4 (see FIG. 7(d)). The pattern
`width L1 of the gate electrode 4 determines the channel
`length of the MOS-FET. Next, an n+-type impurity is
`implanted using the unexposable region 14a as a mask, and
`then unneeded portions of the unexposable region 14a and
`the insulation film 12 are removed. The n+-type impurity is
`thermally diffused to form the n+-type source and drain
`regions 6 and 7 inside the silicon substrate 1 located on
`either side of the gate electrode 4 (see FIG. 7(e)). After
`forming the interlayer insulation film 5, the contact holes 8
`
`– 208 –
`
`JP H4-63437 (2)
`to 10 are formed in the interlayer insulation film 5, thereby
`completing the single gate electrode n-channel MOS-FET
`shows in FIG. 6(a) and (b).
`
`Now turning to FIG. 8(a) and (b), a multiple gate
`electrode n-channel MOS-FET used to obtain large channel
`lengths is described.
`
`FIG. 8(a) is a plan view showing a schematic
`structure of a multiple gate electrode n-channel MOS-FET
`in the midst of being fabricated, and FIG. 8(b) is
`cross-sectional view showing a sectional structure along
`line B-B in FIG. 8(a). As is clear from the drawings, the
`difference between a multiple gate electrode MOS-FET and
`a single gate electrode MOS-FET is that the gate electrode
`4, which is a single electrode in the former, is divided into
`multiple parts (three in the drawings) in the latter. Therefore,
`parts in FIG. 8(a) and (b), which are identical to or
`correspond to parts in FIG. 6(a) and (b), are given the same
`reference numerals and detailed descriptions thereof are
`omitted here.
`
`Specifically, reference numerals 4a to 4c in FIG.
`8(a) and (b) are gate electrodes formed a predetermined
`distance S apart from one another, and L2 is pattern width
`of the gate electrodes 4a and 4c located on either side of the
`MOS-FET. L3 is a pattern width of the gate electrode 4b
`which is located in the middle. Note that the separation
`distance S between the gate electrodes 4a to 4c is set when
`designing the MOS-FET. For example, the separation
`distance S is 1.1 µm if the diameter of the contact holes 8
`and 9 is 0.5 µm and the distance between ends thereof and
`ends of the gate electrodes 4a to 4c is 0.3 µm.
`
`Next, a procedure for fabricating this multiple
`gate electrode n-channel MOS-FET is described. The
`fabricating procedure of this MOS-FET is the same as the
`procedure for fabricating the single gate electrode type
`described with reference to FIG. 7(a) to (e), so only those
`steps which require a description shall be discussed below
`with reference to the cross-sectional view step views shown
`in FIG. 9(a) to (c) which correspond to FIG. 7(b) to (d).
`
`To start, using the same procedure described with
`reference to FIG. 7(a), the photoresist film 14 is formed
`over the polysilicon film 13 which covers the device
`separation insulation film 2 and the insulation film 12.
`Unexposable regions 14c and 14d of the photoresist film 14,
`which are needed to form the gate electrodes 4a and 4c
`which are separated from one another by the predetermined
`distance S, are masked, after which exposure regions 14e
`and 14f of the photoresist film 14 are exposed by being
`irradiated with light using a reduced projection exposure
`device or the like (see FIG. 9(a)).
`
`Once exposure is done developing is performed,
`and if the photoresist film 14 is positive, the unexposable
`regions 14c and 14d remain on the polysilicon film 13 (see
`FIG. 9(b)). The pattern widths L2 (R) and L3 (R) of the
`unexposable regions 14c and 14d are major factors in
`determining the channel length of the MOS-FET.
`
`Thereafter, anisotropic etching is performed, with
`the remaining unexposable regions 14c and 14d masked,
`
`NVIDIA Corp.
`Exhibit 1104
`Page 002
`
`

`

`
`
`thereby removing unneeded portions of the polysilicon film
`13 and forming the gate electrodes 4a to 4c separated from
`one another by the predetermined distance S (see FIG. 9(c)).
`The pattern widths L2 and L3 of the gate electrodes 4a to 4c
`determine the MOS-FET channel length. The same process
`as described in FIG. 7(e) is then performed, and the n+-type
`source and drain regions 6 and 7 are formed in the silicon
`substrate 1, thus completing the multiple gate electrode
`n-channel MOS-FET shown in FIG. 8(a) and (b).
`[Problem to be Solved by the Invention]
`
`With general MOS integrated circuit devices, the
`single electrode and multiple electrode type MOS-FETs
`described above are formed on the same chip in a mixed
`manner. However, if the patterning when fabricating these
`MOS-FETs is very fine, at 0.3 to 0.5 µm, even if the pattern
`widths L1 to L3 of the gate electrodes 4 and 4a to 4c are set
`so as to be uniform and even if the photoresist film 14 is
`exposed using light of one wavelength, the problem
`sometimes occurs
`that
`the channel
`lengths of
`the
`MOS-FETs thus obtained are not uniform and vary.
`
`This problem is thought to occur due to the
`following factors. First, in a single gate electrode MOS-FET,
`as shown in FIG. 7(b) and (c), the exposed region 14b of the
`photoresist film 14 has a satisfactory length relative to the
`wavelength of the light used for exposing the photoresist
`film 14 (e.g., 0.248 µm with excimer light), so the
`photosensitivity is satisfactory. The pattern width L1 (R) of
`the unexposable region 14a obtained by developing tends to
`be narrow as a result. However, in a multiple gate electrode
`MOS-FET, as shown in FIG. 9(a) and (b), the length of the
`exposed region 14f is sufficient relative to the wavelength
`of the light, but nevertheless the length of the exposed
`region 14e between the unexposable regions 14c and 14d is
`only double to 10 times the wavelength of the light (i.e., if
`the separation distance S, or the length of the exposed
`region 14e is set to be 1.1 µm, then 1.1/0.248 = 4.4 times),
`meaning the exposed region 14e is affected by refraction or
`reflection of the light, making the photosensitivity thereof
`insufficient. Accordingly, the pattern width L2 (R) of the
`unexposable region 14d sandwiched by the exposed region
`14e tends to be thicker, and the pattern width L3 (R) of the
`unexposable region 14c sandwiched between the exposed
`region 14e and the exposed region 14f tends to be the
`average thickness thereof due to a balance between
`tendencies to be thinner and thicker.
`
`Therefore, even though in the original design the
`pattern widths L1 to L3 of the gate electrodes 4 and 4a to 4c
`of the MOS-FET formed in a mixed manner are set so as to
`be uniform, once the wafer process is finished the pattern
`widths L1 to L3 of the gate electrodes 4 and 4a to 4c which
`determine the channel lengths of the single gate electrode
`and multiple gate electrode MOS-FETS wind up being
`different, which has been a problem. Moreover, in the
`multiple gate electrode MOS-FET, the pattern widths L2
`and L3 of the gate electrodes 4a and 4c, which are located
`on either side, and the gate electrode 4b located in the
`middle have been different.
`
`
`– 209 –
`
`JP H4-63437 (3)
`The present invention was devised in light of this
`
`problem and has as an object to provide a semiconductor
`integrated circuit device whereby channel lengths of field
`effect transistors formed in a mixed manner can be made
`uniform and variation thereamong can be minimized.
`[Means for Solving the Problem]
`
`To achieve this object, the present invention is a
`semiconductor integrated circuit device in which a plurality
`of field effect transistors having one or a plurality of gate
`electrodes are formed in a mixed manner, wherein dummy
`patterns are formed in locations outside the gate electrodes
`of the field effect transistors a predetermined distance from
`the gate electrodes, positioned parallel thereto, and made
`from an identical material.
`[Operation]
`
`With this configuration, irrespective of whether
`the field effect transistors formed in a mixed manner on a
`semiconductor integrated circuit device are single gate
`electrode types or multiple gate electrode types, the gate
`electrodes are sandwiched by dummy patterns which are
`positioned parallel, separated from one another by a
`predetermined distance. The exposure conditions when
`fabricating these gate electrodes are thus uniform.
`[Embodiments]
`invention are
`the present
`
`Embodiments of
`described below with reference to the drawings. Note that
`in the embodiments the semiconductor integrated circuit
`device is a MOS integrated circuit device comprising a
`plurality of n-channel MOS-FETs.
`the
`in
`
`The MOS
`integrated circuit device
`embodiments is configured by a plurality of single gate
`electrode and multiple gate electrode n-channel MOS-FETs
`which are formed in a mixed manner on one chip. In the
`following description, first a configuration and fabrication
`procedure for the single gate electrode MOS-FETs is
`described with reference to FIG. 1(a) and (b) and FIG. 2(a)
`to (e), after which a configuration and fabrication procedure
`for multiple gate electrode MOS-FETs is described with
`reference to FIG. 4(a) and (b) and FIG. 5(a) to (c). Note that
`all MOS-FETs related to the present embodiment are
`fundamentally the same as the prior art examples in FIG.
`6(a) and (b) and FIG. 8(a) and (b) aside from the dummy
`patterns described below being provided, so portions and
`parts which are identical or corresponding are given the
`same reference numerals.
`
`FIG. 1(a) is a plan view showing a schematic
`structure of a single gate electrode n-channel MOS-FET in
`the midst of being fabricated. FIG. 1(b) is a cross-sectional
`view showing a section structure along line B-B in FIG. 1(a).
`Reference numeral 1 in these drawings is a p-type silicon
`substrate, 2 is a device separation insulation film, 3 is a gate
`insulation film covering a MOS-FET channel, and 4 is a
`gate electrode comprising polysilicon or the like. Dummy
`patterns 15 are formed on the device separation insulation
`film 2 outside the gate electrode 4, separated therefrom by a
`predetermined distance S, positioned parallel thereto, and
`made from an identical material as the gate electrode 4.
`
`NVIDIA Corp.
`Exhibit 1104
`Page 003
`
`

`

`
`
`Note that the dummy patterns 15 are formed electrically
`separated from the gate electrode 4, and the separation
`distance S from the gate electrode 4 is identical to or
`substantially equal to the separation distance S between
`gate electrodes 4a to 4c in a multiple gate electrode
`MOS-FET of the prior art.
`
`Reference numeral 5 in the drawings is an
`interlayer insulation film 2 covering the gate electrode 4
`and the dummy patterns 15, and 6 and 7 are n+-type source
`and drain regions of the MOS_FET. Electrical connection
`of the source and drain regions 6 and 7 is made via contact
`holes 8 and 9 formed in the interlayer insulation film 5.
`Reference numeral 10 is a contact hole for electrical
`connection with the gate electrode 4, and 11 is a field
`pattern showing boundaries
`in
`the device separation
`insulation film 2. L is a pattern width of the gate electrode 4
`which determines a channel length of the MOS-FET.
`
`A fabrication procedure for this MOS-FET is
`described with reference to cross-sectional step views
`shown in FIG. 2(a) to (e).
`
`To start, an insulation film 12 that will serve as
`the device separation insulation film 2 and the gate
`insulation film 3 is formed on a surface of the silicon
`substrate 1, and then a polysilicon film 13 is formed over
`the entire surface thereof (see FIG. 2(a)). Next, a positive
`(or negative) photoresist is applied to cover the entire
`polysilicon film 13, and only unexposable regions 14a and
`14g of a photoresist film 14which are needed to form the
`gate electrode 4 and the dummy patterns 15 which are
`separated from one another by the predetermined distance S
`are masked. Exposed regions 14h and 14i, which have not
`been masked, of the photoresist film 14 are exposed by
`being irradiated with light with a reduced projection
`exposure device or the like (see FIG. 2(b)). After exposure
`is finished, developing is done, and if the photoresist film
`14 is positive, the unexposable region 14a and the
`unexposable region 14g having the pattern width L (R) are
`left on the polysilicon film 13 (see FIG. 2(c)). Note that
`exposure of the photoresist 14 is done by light here, but
`exposure can also be done using x-rays, electron beams, or
`the like.
`Next, anisotropic etching, e.g., reactive ion
`
`etching, with the remaining unexposable regions 14a and
`14g masked, is performed, thereby removing unneeded
`portions of the polysilicon film 13, thereby causing only
`those parts of the polysilicon film 13 covered by the
`unexposable regions 14a and 14g to remain and forming the
`gate electrode 4 and the dummy patterns 15 with the pattern
`width L (see FIG. 2(d)). Next, an n+-type impurity is
`implanted, using the unexposable regions 14a and 14g as a
`mask, unneeded parts of the unexposable regions 14a and
`14g and the insulation film 12 are removed, and the n+-type
`impurity is thermally diffused, thereby forming the n+-type
`source and drain regions 6 and 7 inside the silicon substrate
`1 located on either side of the gate electrode 4 (see FIG.
`2(e)). After forming the interlayer insulation film 5, contact
`holes 8 to 10 are formed in the interlayer insulation film 5,
`
`– 210 –
`
`JP H4-63437 (4)
`thereby completing the single gate electrode n-channel
`MOS-FET shows in FIG. 1(a) and (b). The dummy patterns
`15 which are formed outside the gate electrode 4 of the
`MOS-FET, are positioned parallel
`thereto and
`the
`predetermined distance S therefrom.
`
`Note that in FIG. 1(a) and (b) the dummy patterns
`15 are electrically separated from the gate electrode 4 and
`are formed on the device separation insulation film 2, but
`this is not a limitation. For example, as shown in FIG. 3(a),
`the dummy patterns 15 can be connected and unified with
`the gate electrode 4, or another wiring pattern 16
`configuring a MOS integrated circuit device can be used as
`the dummy patterns 15 as shown in FIG. 3(b). Moreover, as
`shown in FIG. 3(c), the dummy patterns 15 can also be
`configured as dummy gate electrodes having the exact same
`configuration as the gate electrode 4.
`
`Now turning to FIG. 4(a) and (b), a multiple gate
`electrode n-channel MOS-FET is described.
`
`FIG. 4(a) is a plan view showing a schematic
`structure of a multiple gate electrode n-channel MOS-FET
`in
`the midst of being fabricated. FIG. 4(b)
`is a
`cross-sectional view showing a sectional structure along
`line B-B in FIG. 4(a). Note that basic configurations of the
`multiple gate electrode MOS-FET and the single gate
`electrode MOS-FET are the same, so parts in FIG. 4(a) and
`(b) which are identical or corresponding to parts in FIG.
`1(a) and (b) are given the same reference numeral, and a
`detailed description thereof is omitted.
`
`Specifically,
`in
`this multiple gate electrode
`MOS-FET, gate electrodes 4a to 4c comprising polysilicon
`are formed a predetermined distance S apart from one
`another, as shown in FIG. 4(a) and (b). Dummy patterns 15
`are formed on the device separation insulation film 2
`outside the gate electrodes 4a to 4c, separated by the
`predetermined distance S from the gate electrodes 4a and 4c
`which are located at either side, positioned parallel thereto,
`and made from the same material, namely polysilicon or the
`like. Note that the separation distance S between the gate
`electrode 4 and the dummy patterns 15 is set so as to be
`identical to or substantially equal to the separation distance
`S between the gate electrodes 4a to 4c.
`
`A procedure for fabricating this multiple gate
`electrode n-channel MOS-FET is described next. Note that
`the procedure for fabricating this MOS-FET is basically the
`same as that for the single gate electrode type shown in FIG.
`2(a) to (e), so only those steps which are different are
`described below, with reference to the cross-sectional step
`view shown in FIG. 5(a) to (c), which corresponds to FIG.
`2(b) to (d).
`
`To start, the photoresist film 14 is formed on the
`polysilicon film 13 that covers the device separation
`insulation film 2 and the insulation film 12 using the same
`procedure as was described with reference to FIG. 2(a).
`Unexposable regions 14j and 14k in the photoresist film 14,
`which are needed to form the gate electrodes 4a to 4c and
`the dummy patterns 15, which are separated from one
`another by the predetermined distance S, are masked, and
`
`NVIDIA Corp.
`Exhibit 1104
`Page 004
`
`

`

`JP H4-63437 (5)
`showing a schematic structure of a multiple gate electrode
`n-channel MOS-FET in the midst of being fabricated. FIG.
`4(b) is a cross-sectional view showing a sectional structure
`along line B-B in FIG. 4(a). FIG. 5(a) to (c) is a
`cross-sectional step view showing a fabrication procedure
`thereof.
`FIGs. 6 to 9 relate to a conventional example.
`
`FIG. 6(a) is a plan view showing a schematic structure of a
`single gate electrode n-channel MOS-FET in the midst of
`being fabricated. FIG. 6(b) is a cross-sectional view
`showing a section structure along line B-B in FIG. 6(a). FIG.
`7(a) to (e) is a cross-sectional step view showing a
`fabrication procedure thereof. FIG. 8(a) is a plan view
`showing a schematic structure of a multiple gate electrode
`n-channel MOS-FET in the midst of being fabricated. FIG.
`8(b) is a cross-sectional view showing a section structure
`along line B-B in FIG. 8(a). FIG. 9(a) to (c) is a
`cross-sectional step view showing a fabrication procedure
`thereof.
`Reference numerals 4 to 4a to 4c in the drawings
`
`are gate electrodes, 15 is dummy patterns, L is gate
`electrode pattern widths, and S is a separation distance
`(predetermined distance).
`
`Note that the same reference numerals in the
`drawings indicate identical or corresponding parts.
`
`Agent: Masuo Oiwa
`
`4: gate electrode
`15: dummy patterns
`L: gate electrode pattern width
`S: separation distance (predetermined distance)
`
`
`
`exposed regions 14m and 14n in the photoresist film 14.
`which are not masked, are exposed by being irradiated with
`light by a reduced projection exposure device or the like
`(see FIG. 5(a)).
`
`After exposure is finished, developing is done,
`and if the photoresist film 14 is positive, the unexposable
`regions 14j and 14k are left on the polysilicon film 13 (see
`FIG. 5(b)). The pattern width L (R) of the unexposable
`region 14j is a major factor in determining the channel
`length of the MOS-FET.
`
`When unneeded portions of the polysilicon film
`13 are removed by anisotropic etching with the remaining
`unexposable regions 14j and 14k masked,
`the gate
`electrodes 4a to 4c, separated from one another by the
`predetermined distance S, and the dummy patterns 15 are
`formed (see FIG. 5(c)). The MOS-FET channel length is
`determined by the pattern width L of the gate electrodes 4a
`to 4c. The same process is performed as was described with
`reference to FIG. 2(e) to form the n+-type source and drain
`regions 6 and 7 in the silicon substrate 1, thereby
`completing the multiple gate electrode n-channel MOS-FET
`shown in FIG. 4(a) and (b). The dummy patterns 15 are
`formed outside the gate electrodes 4a to 4c of the
`MOS-FET, separated therefrom by the predetermined
`distance S and positioned parallel thereto.
`
`The single gate electrode and multiple gate
`electrode MOS-FETs thus described are formed on one chip
`in a mixed manner, and the dummy patterns 15 are formed
`parallel outside the gate electrodes 4 and 4a to 4c, separated
`therefrom by the predetermined distance S, meaning the
`gate electrodes 4 and 4a to 4c are sandwiched between the
`dummy patterns 15.
`[Effects of the Invention]
`
`As described above, with the semiconductor
`integrated circuit device according to the present invention,
`irrespective of whether the field effect transistors formed in
`a mixed manner thereon are single gate electrode types or
`multiple gate electrode types, the gate electrodes are
`sandwiched by dummy patterns which are positioned
`parallel thereto and separated from one another by a
`predetermined distance. The exposure conditions when
`fabricating these gate electrodes are thus uniform, and the
`pattern width between the gate electrodes thus obtained are
`substrate uniform. As a result, the outstanding effect can be
`provided of
`the channel
`lengths of
`the field-effect
`transistors formed in a mixed manner being able to be made
`uniform, and variation thereamong being able to be
`minimized.
`4. Brief Description of the Drawings
`
`FIGs. 1 to 5 relate to embodiments of the present
`invention. FIG. 1(a) is a plan view showing a schematic
`structure of a single gate electrode n-channel MOS-FET in
`the midst of being fabricated. FIG. 1(b) is a cross-sectional
`view showing a section structure along line B-B in FIG. 1(a).
`FIG. 2(a) to (e) is a cross-sectional step view showing a
`fabrication procedure thereof. FIG. 3(a) to (c) is a plan view
`showing a variation thereof. FIG. 4(a) is a plan view
`
`– 211 –
`
`NVIDIA Corp.
`Exhibit 1104
`Page 005
`
`

`

`
`
`JP H4-63437 (6)
`
`FIG. 2
`
`FIG. 2
`
`FIG. 2
`
`FIG. 2
`
`FIG. 2
`
`– 212 –
`
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`NVIDIA Corp.
`Exhibit 1104
`Page 006
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`

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`JP H4-63437 (7)
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`FIG. 3
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`FIG. 3
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`FIG. 3
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`FIG. 4
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`
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`S: separation distance (predetermined distance)
`L: gate electrode pattern width
`15: dummy patterns
`4a to 4c: gate electrodes
`FIG. 4(a)
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`– 213 –
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`FIG. 4
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`NVIDIA Corp.
`Exhibit 1104
`Page 007
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`

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`JP H4-63437 (8)
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`FIG. 5
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`FIG. 5
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`FIG. 5
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`FIG. 6
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`FIG. 7
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`FIG. 6
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`FIG. 7
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`– 214 –
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`NVIDIA Corp.
`Exhibit 1104
`Page 008
`
`

`

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`JP H4-63437 (9)
`
`FIG. 7
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`FIG. 7
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`FIG. 7
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`FIG. 8
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`FIG. 8
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`– 215 –
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`NVIDIA Corp.
`Exhibit 1104
`Page 009
`
`

`

`Attn: Commissioner of Patents
`1. Indication of case: Heisei 2 Patent Application No.
`177022
`2. Title of the invention: Semiconductor Integrated Circuit
`Device
`3. Parties to the amendment
` Relationship to case: Applicant
` Address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo-to
`Postal Code 100
` Name: (601) Mitsubishi Electric Co., Ltd.
` Moriya Shigi, representative
`4. Agent
` Address: c/o Mitsubishi Electric Co., Ltd.
` 2-2-3 Marunouchi, Chiyoda-ku, Tokyo-to
`Postal Code 100
` Name: (7375) Masuo Oiwa, patent attorney
`
`[seal: illegible]
` (Contact: Patent Dept., 03 (213) 3421)
`5. Date of amendment order: voluntary amendment
`6. Increased number of claims due to amendment: none
`7. Amended sections: “Detailed Description of
`Invention” in the Specification
`8. Content of amendment: see separate
`
`[seal: Patent Office/21 Dec 90/]
`
`
`the
`
`
`
`
`
`Content of the Amendment
`(1) The “Detailed Description of the Invention” in the
`Specification is amended as follows.
`(i) “short channel length” in Specification, page 2, line 11 is
`amended to “small channel width”.
`(ii) “large channel length” in Specification, page 2, line 13
`to line 14 is amended to “large channel width”.
`(iii) “large channel length” in Specification, page 6, line 2
`to line 3 is amended to “large channel width.”
`
`END
`
`
`
`JP H4-63437 (10)
`
`
`
`
`
`Written Amendment (Voluntary)
`[stamp: APPROVED]
`December 19, 1990
`
`FIG. 9
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`FIG. 9
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`FIG. 9
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`– 216 –
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`NVIDIA Corp.
`Exhibit 1104
`Page 010
`
`

`

`Ed
`
`TRANSPERFECT
`
`City ot‘New York, State ofNew York, County ot‘New York
`
`1. Julianne Marzulla, hereby certify that the following, document is, to the best 01‘
`
`my knowledge and belief, a true and accurate translation from Japanese to
`
`English.
`
`“Japanese Unexamined Patent App. Pub. 112-177022”
`
`
`
`Julianne Marzulla
`
`Sworn to before me this
`
`Wednesday, May 06, 2015
`
`
`
`Signature; Notary mute _
`
` SAMA
`A DEWAA- ALEFYT _
`
`Notary“?Putic- State bfeaw York
`
`1DE6320& 3
`Qualified in NEW YORK Cmmty
`Commission Expires Mar 02, 9.019
`
`
`.
`
`Stamp, Notary Public
`
`NVIDIA Corp.
`Exhibit 1104
`Page 011
`
`

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`NVIDIA Corp.
`EbeH1104
`Page012
`
`NVIDIA Corp.
`Exhibit 1104
`Page 012
`
`

`

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