(12) United States Patent
`Kim
`
`US006287902B1
`US 6,287,902 B1
`Sep. 11, 2001
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`(54) METHODS OF FORMING ETCH
`INHIBITING STRUCTURES ON FIELD
`ISOLATION REGIONS
`
`(75) Inventor: Do-hyung Kim, Seoul (KR)
`
`(73) Assignee: Samsung Electronics Co., Ltd. (KR)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/318,188
`(22) Filed:
`May 25, 1999
`
`Related US. Application Data
`
`(62) Division of application No. 08/748,148, ?led on Nov. 12,
`1996, now abandoned.
`Foreign Application Priority Data
`
`(30)
`
`Jun. 28, 1996
`
`............................................... .. 96-25227
`
`(51) Int. Cl.7 ................................................. .. H01L 21/338
`(52) US. Cl. ........................................... .. 438/183; 438/926
`(58) Field of Search ................................... .. 438/183, 926,
`438/740, 233, 439
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`11/1992 Nagatomo et al. ................ .. 257/395
`5,164,806
`12/1992 Yamamoto et al. ..
`156/643
`5,174,858
`12/1993 Ikeda ............... ..
`438/453
`5,273,936
`3/1994 Nishigoori
`174/250
`5,293,503
`4/1994 Drummond
`257/620
`5,306,945
`5,357,133 * 10/1994 Morita ......... ..
`257/316
`5,365,111
`11/1994 Ramaswami et al.
`257/768
`5,436,188
`7/1995 Chen .................................. .. 438/397
`
`5,441,916 * 8/1995 Motonami .......................... .. 437/195
`5,475,266 * 12/1995 Rodder
`.. 257/750
`5,550,076 * 8/1996 Chen
`438/253
`5,659,202 * 8/1997 Ashida ...... ..
`257/758
`5,698,902 * 12/1997 Uehara 6161.
`257/773
`5,706,164
`1/1998 Jeng .......... ..
`438/239
`5,789,313 * 8/1998 Lee ..... ..
`.. 438/599
`5,932,920 * 8/1999 Kim 6161. .......................... .. 257/395
`
`FOREIGN PATENT DOCUMENTS
`
`12/1977 (DE).
`2724165
`1/1993 (EP) ............................ .. H01L/21/90
`0523856A2
`9/1978 (JP) ............................. .. H01L/21/88
`53-108391
`59-76447 * 5/1984 (JP).
`59-76447
`8/1984 (JP) ............................. .. H01L/21/88
`60-66444
`4/1985 (JP) ..
`.. H01L/21/76
`62-177945
`8/1987 (JP) .................................... .. 257/758
`463437 * 2/1992 (JP).
`8-335701 * 2/1992 (JP).
`9-64195 * 3/1997 (JP).
`
`* cited by examiner
`
`Primary Examiner—Olik Chaudhuri
`Assistant Examiner—Phat X. Cao
`(74) Attorney, Agent, or Firm—Myers Bigel Sibley &
`Sajovec
`(57)
`
`ABSTRACT
`
`A microelectronic structure includes a substrate having
`adjacent active and ?eld regions. A ?eld isolation layer
`covers the ?eld region, and an etch inhibiting layer is
`provided on the ?eld isolation layer adjacent the active
`region of the substrate. An insulating layer covers the
`substrate, the ?eld isolation layer, and the etch inhibiting
`layer, and the insulating layer de?nes a contact hole therein
`exposing a portion of the active region adjacent the etch
`inhibiting layer. Related methods are also discussed.
`
`18 Claims, 2 Drawing Sheets
`
`N41:
`
`440 “p48
`
`€-40
`
`NVIDIA Corp.
`Exhibit 1101
`Page 001
`
`

`

`U.S. Patent
`
`Sep. 11,2001
`
`Sheet 1 012
`
`US 6,287,902 B1
`
`
`
`FIG‘ 1 (PRIOR ART)
`
`1A 1
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`FIG. 2
`(PRIOR ART)
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`M
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`jjzj
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`M24
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`FIG. 3
`(PRIOR ART)
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`‘:12?
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`FIG. 4
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`5
`44a
`44
`1
`1
`f
`46“ %
`-—4-6c1
`“r42
`
`“k145i
`
`NVIDIA Corp.
`Exhibit 1101
`Page 002
`
`

`

`U.S. Patent
`
`Sep. 11,2001
`
`Sheet 2 0f 2
`
`US 6,287,902 B1
`
`FIG. 5
`
`2?“
`
`FIG. 6
`
`4160
`4&4-
`46 W , W 46642
`if
`
`FIG. '2
`
`FIG. 8’
`
`"48
`--46c1
`
`F42
`
`NVIDIA Corp.
`Exhibit 1101
`Page 003
`
`

`

`US 6,287,902 B1
`
`1
`METHODS OF FORMING ETCH
`INHIBITING STRUCTURES ON FIELD
`ISOLATION REGIONS
`
`This application is a divisional application of US. patent
`application Ser. No. 08/748,148 ?led Nov. 12, 1996,
`abandoned, and entitled ETCH INHIBITING STRUC
`TURES ON FIELD ISOLATION REGIONS AND
`RELATED METHODS.
`
`FIELD OF THE INVENTION
`
`The present invention relates to microelectronic structures
`and methods and more particularly to microelectronic struc
`tures and methods including isolation regions.
`
`BACKGROUND OF THE INVENTION
`
`As integrated circuit devices become more highly
`integrated, the space available for individual devices formed
`thereon is reduced. Accordingly, the siZes of patterns such as
`gates, bit lines, and metal lines formed on integrated circuits
`are generally reduced. Furthermore, space betWeen these
`patterns is also generally reduced.
`In particular, integrated circuit memory devices include a
`plurality of memory cells, and each memory cell is con
`nected to other cells by conductive (metal) lines. The cells
`and conductive (metal) lines are connected to the substrate
`or other conductive layers by contact holes or via holes. The
`contact holes expose active regions of the substrate and the
`via holes expose the surface of other conductive layers.
`Patterned layers such as the gate electrodes should be
`isolated from the holes, and these patterned layers are
`generally arranged around the holes. Accordingly, the holes
`must be accurately placed in order to maintain electrical
`isolation With respect to the patterned layers such as the gate
`electrodes.
`As the space betWeen these patterned layers is reduced,
`hoWever, the space available for forming the holes may also
`be reduced. Furthermore, there may be physical limits to the
`reductions Which can be made to the siZe of the holes.
`Accordingly, the increased integration reduces the margin
`available in the placement of the holes. The margin available
`for the placement of the holes is also in?uenced by the
`process limitations of the steps for forming other adjacent
`patterns. For example, When a LOCOS ?eld oxide layer is
`formed, the bird’s beak phenomenon may reduce the active
`region. When a trench ?eld oxide layer is formed, the inner
`Wall of the trench may encroach into the active region also
`reducing the area available to the hole and further decreasing
`the margin for the formation of the hole.
`FIG. 1 is a cross-sectional vieW of an integrated circuit
`device having a contact hole 16. The ?eld oxide layer 12 is
`formed on the semiconductor substrate 10, and the gate
`electrode 14 is formed on an active region de?ned by the
`?eld oxide layer 12. Spacers 15 are formed along the
`sideWalls of the gate electrode 14. An insulating layer 20 is
`then formed on the surface of the substrate including the gate
`electrode 14 and the ?eld oxide layer 12, and the contact
`hole 16 is formed therein to expose a portion of the active
`region of the substrate. The conductive layer 18 is formed on
`the insulating layer 20 thus ?lling the contact hole 16. The
`contact hole 16 is preferably formed over the active region
`betWeen the gate electrode 14 and the ?eld oxide ?lm 12 so
`that neither the gate electrode 14 nor the ?eld oxide ?lm 12
`is exposed.
`While the contact hole 16 is shoWn centered betWeen the
`gate electrode 14 and the ?eld oxide layer 12 in FIG. 1, it
`
`10
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`15
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`25
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`35
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`45
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`55
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`65
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`2
`may become more difficult to form the contact hole betWeen
`these structures as the device integration increases. As the
`spaces become smaller, formation of the contact hole 16 may
`be limited by the physical characteristics of light and the
`ability to properly align the mask. Accordingly, the margin
`for error during the formation of the contact hole is reduced.
`As shoWn in FIGS. 2 and 3, misalignment of the contact hole
`photomask may cause the contact hole to expose either the
`gate electrode 14 or the ?eld oxide layer 12.
`As shoWn in FIG. 2, the misaligned contact hole 24
`exposes a portion of the active region as Well as a portion of
`the ?eld region. This misalignment may also result in the
`formation of a Well through the ?eld oxide layer 12 thus
`exposing a portion of a ?eld region of the substrate When
`etching the insulating ?lm 20. In other Words, a contact hole
`24 may partially expose an active region of the substrate and
`a Well in the ?eld region of the substrate. Accordingly, When
`the contact hole 24 is ?lled With the conductive layer 18, the
`conductive layer 18 is brought into contact With the Well.
`Leakage current may thus ?oW through the conductive layer
`18 into the Well area. The integrated circuit device may thus
`overload leading to a delay in the operation of the device or
`even a malfunction. If a capacitor is formed, the life of the
`capacitor may also be reduced.
`In FIG. 3, a misaligned contact hole exposes a portion of
`the gate electrode 14. Accordingly, the conductive layer 18
`?lling the contact hole 25 may contact the gate electrode 14
`thus short circuiting the device. The reliability of the inte
`grated circuit device may thus be reduced.
`As discussed above, margins for forming contact holes are
`reduced as device integration increases. For example, the
`extension of a gate or a ?eld region may reduce the area
`available for a contact hole, thus reducing the process
`margins. The reduction of process margins in turn causes a
`reduction in the alignment margin for the photomask used to
`form the contact hole. Accordingly, alignment of the pho
`tomask may become more difficult. The contact holes for
`integrated circuit devices may thus be more dif?cult to form
`and the alignment thereof may also be more dif?cult.
`Accordingly, there continues to exist a need in the art for
`improved contact hole structures and related methods.
`
`SUMMARY OF THE INVENTION
`It is therefore an object of the present invention to provide
`improved contact hole structures and methods.
`It is still another object of the present invention to provide
`increased alignment tolerances for the formation of contact
`holes.
`These and other objects are provided according to the
`present invention by structures and methods Wherein an etch
`inhibiting layer is provided on a ?eld isolation layer adjacent
`the active region of the substrate. This etch inhibiting layer
`alloWs the misalignment of the contact hole Without dam
`aging the ?eld isolation, layer. Accordingly, the yield and
`reliability of integrated circuit devices formed according to
`the present invention can be increased at a given level of
`integration.
`In particular, a microelectronic structure includes a sub
`strate having active and ?eld regions and a ?eld isolation
`layer Which covers the ?eld region, and ?rst and second
`patterned conductive layers. The ?rst patterned conductive
`layer is on the active region of the substrate spaced apart
`from the ?eld region, and the second patterned conductive
`layer is on the ?eld isolation layer adjacent the active region
`of the substrate. The second patterned conductive layer thus
`acts as the etch inhibiting layer protecting the ?eld isolation
`layer.
`
`NVIDIA Corp.
`Exhibit 1101
`Page 004
`
`

`

`US 6,287,902 B1
`
`3
`The structure can also include an insulating layer covering
`the substrate, the ?eld isolation layer, and the ?rst and
`second patterned conductive layers, and the insulating layer
`includes a contact hole therein exposing a portion of the
`active region betWeen the ?rst and second patterned con
`ductive layers. The contact hole can thus extend over the
`?eld region Without damaging the ?eld isolation layer
`because the ?rst patterned conductive layer protects the ?eld
`isolation layer.
`In addition, the ?rst and second patterned conductive
`layers may include insulating spacers along sideWalls
`thereof, and the insulating layer can preferably be selectively
`etched With respect to the insulating spacers. In particular,
`the insulating layer can be formed from nitride.
`The second patterned conductive layer is preferably elec
`trically isolated so that it serves no electrical function in the
`completed device. This layer can thus act only as an etch
`inhibiting layer to protect the ?eld isolation layer.
`Furthermore, the ?eld isolation layer can be formed from
`oxide, and the ?eld region can be a trench in the substrate
`With the ?eld isolation layer ?lling the trench.
`According to another aspect of the invention, a method
`includes the steps of de?ning adjacent active and ?eld
`regions on a substrate, and forming a ?eld isolation layer on
`the ?eld region. An etch inhibiting layer is formed on the
`?eld isolation layer adjacent the active region of the sub
`strate. An insulating layer is then formed on the substrate,
`the ?eld isolation layer, and the etch inhibiting layer, and a
`contact hole is formed in the insulating layer. This contact
`hole exposes a portion of the active region of the substrate
`adjacent the etch inhibiting layer and the ?eld isolation layer.
`The etch inhibiting layer thus protects the ?eld isolation
`layer during the step of forming the contact hole.
`The insulating layer can be nitride, and the step of
`forming the insulating layer can be preceded by the step of
`forming a patterned conductive layer on the active region of
`the substrate. More particularly, the etch inhibiting layer and
`the patterned conductive layer can each include a conductive
`portion and insulating spacers along sideWalls thereof.
`Preferably, the steps of forming the etch inhibiting layer and
`forming the patterned conductive layer are performed simul
`taneously. In addition, the etch inhibiting layer is preferably
`electrically isolated, and the ?eld isolation layer can be
`oxide.
`The methods and structures of the present invention thus
`provide protection for the ?eld isolation layer during the
`formation of a contact hole. Accordingly, a greater degree of
`misalignment during the step of forming the contact hole can
`be tolerated.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a cross sectional vieW illustrating a contact hole
`formed according to the prior art.
`FIG. 2 is a cross sectional vieW illustrating a ?rst mis
`aligned contact hole formed according to the prior art.
`FIG. 3 is a cross sectional vieW illustrating a second
`misaligned contact hole formed according to the prior art.
`FIG. 4 is a cross sectional vieW illustrating a contact hole
`formed according to the present invention.
`FIGS. 5—7 are cross sectional vieWs illustrating steps of a
`method for forming a contact hole according to the present
`invention.
`FIG. 8 is a cross sectional vieW illustrating a misaligned
`contact hole formed according to the present invention.
`
`10
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`15
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`DETAILED DESCRIPTION
`The present invention Will noW be described more fully
`hereinafter With reference to the accompanying draWings, in
`
`65
`
`4
`Which preferred embodiments of the invention are shoWn.
`This invention may, hoWever, be embodied in many different
`forms and should not be construed as limited to the embodi
`ments set forth herein; rather, these embodiments are pro
`vided so that this disclosure Will be thorough and complete,
`and Will fully convey the scope of the invention to those
`skilled in the art. In the draWings, the thicknesses of layers
`and regions are exaggerated for clarity. Like numbers refer
`to like elements throughout.
`A contact hole formed according to the present invention
`is illustrated in FIG. 4. As shoWn, a ?eld isolation layer 42
`is formed on a ?eld region of the substrate 40, and the ?eld
`isolation layer 42 can be an oxide layer. Portions of the
`substrate 40 not covered by the ?eld isolation layer 42 de?ne
`the active region Where microelectronic devices Will be
`formed. As also shoWn, the ?eld isolation layer 42 may be
`formed in a trench. Alternately, the ?eld oxide layer may be
`formed by a LOCOS-type method.
`First and second patterned conductive layers 44 and 44a
`are formed respectively on the active region of the substrate
`and on a ?eld isolation layer 42. Insulating spacers 46 and
`46a are formed along the sideWalls of the ?rst and second
`patterned conductive layers 44 and 44a. In particular, the
`?rst patterned conductive layer 44 can be a gate electrode of
`a transistor. The second patterned conductive layer 44a
`preferably has the same structure as the ?rst patterned
`conductive layer 44 With the exception that the second
`patterned conductive layer is electrically isolated. In other
`Words, the second patterned conductive layer 44a serves as
`a dummy pattern.
`An insulating layer 48 is then formed over the surface of
`the semiconductor substrate including the ?rst and second
`patterned conductive layers 44 and 44a. Acontact hole 50 is
`then formed in the insulating layer 48 thereby exposing a
`portion of the active region of the substrate. More
`particularly, the contact hole 50 may expose a doped layer
`43 in the active region of the substrate. The insulating layer
`48 is preferably formed from a material such as nitride
`Which is more susceptible to etching than the material used
`to form the insulating spacers 46 and 46a.
`Using the structure discussed above, some misalignment
`of the contact hole 50 can be tolerated. In particular, if the
`contact hole extends beyond the active region of the sub
`strate encroaching into the ?eld region, a second patterned
`conductive layer 44a reduces the likelihood that a Well Will
`be formed in the ?eld isolation layer 42. In particular, the
`second patterned conductive layer 44a can act as an etch
`stop if needed When etching the insulating layer 48. In other
`Words, contact hole 50 can noW extend over the ?eld region
`Without damaging the ?eld isolation layer 42.
`When comparing the prior art structure of FIG. 1 With that
`of FIG. 4, the area over Which the contact hole 50 can be
`formed using the structure of the present invention is larger
`than the area available using the structure of the prior art. In
`particular, the contact hole of FIG. 1 must be formed
`betWeen the gate electrode 14 and the ?eld oxide layer 12.
`When using the structure of the present invention, hoWever,
`the area over Which the contact hole 50 can be formed
`extends over a portion of the ?eld region covered by the
`second patterned conductive layer 44a.
`A method for forming an integrated circuit device accord
`ing to the present invention Will be discussed With reference
`to FIGS. 5—7. Active and isolation regions of the substrate 40
`are de?ned as shoWn in FIG. 5. In particular, ?eld isolation
`layer 42 is formed on the isolation region of the substrate,
`and the active region of the substrate is left exposed. This
`
`NVIDIA Corp.
`Exhibit 1101
`Page 005
`
`

`

`US 6,287,902 B1
`
`10
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`25
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`5
`?eld isolation layer can be formed from a layer of oxide.
`Electronic devices are typically not formed in the isolation
`region of the substrate. As shoWn, a trench can be formed on
`the isolation region of the substrate and this trench can be
`?lled With the ?eld isolation layer. Alternately, a ?eld
`isolation layer can be formed by other methods such as the
`LOCOS method. Electronic devices can be formed in the
`active region of the substrate Which is left exposed.
`First and second patterned conductive layers 44 and 44a
`can then be formed as shoWn in FIG. 6. As shoWn, a ?rst
`patterned conductive layer 44 is formed on an active region
`of the substrate 40, and a second patterned conductive layer
`44a is formed on the ?eld isolation layer 42. In particular, an
`oxide layer and a conductive layer can be sequentially
`formed on the surface of the substrate 40 including the ?eld
`isolation layer 42. A photoresist pattern can then be formed
`on the conductive layer to de?ne the patterned conductive
`layers. The exposed portions of the conductive layer and the
`oxide layer can then be isotropically etched to expose
`portions of the surface of the substrate 40 and the ?eld
`isolation layer 42. Accordingly, the ?rst and second pat
`terned conductive layers 44 and 44a are respectively formed
`on the active and ?eld regions of the substrate. The patterned
`conductive layers can be de?ned to include an oxide layer
`adjacent the substrate.
`Anitride layer can then be formed over the surface of the
`patterned conductive layers, the substrate 40, and the ?eld
`isolation layer 42. This nitride ?lm can be isotropically
`etched to form the nitride spacers 46 and 46a along the
`sideWalls of the ?rst and second patterned conductive layers
`44 and 44a. As Will be discussed beloW, a contact hole 50
`can thus be self-aligned using the spacers 46 and 46a.
`Unlike methods of the prior art, the structure formed
`according to the present invention includes the second
`patterned conductive layer 44a on the ?eld isolation layer
`42. The ?rst patterned conductive layer 44 may be used as
`a gate electrode, While the second patterned conductive layer
`44a can be a dummy pattern serving no electrical function.
`Instead, the second patterned conductive layer 44a is used to
`increase a process margin for the formation of a contact hole
`by alloWing the formation of a self-aligned contact hole as
`discussed beloW. Accordingly, the second patterned conduc
`tive layer 44a is preferably electrically isolated over the ?eld
`region.
`The second patterned conductive layer 44a is formed on
`a portion of the ?eld isolation layer 42 Where a misaligned
`contact hole Would most likely encroach. Accordingly, the
`second patterned conductive layer 44a can be used to reduce
`design rule constraints related to the formation of the contact
`hole. The siZe of the second patterned conductive layer 44a
`is determined in part by the siZe of the contact hole to be
`formed and the likely position of the contact hole in the
`event of misalignment.
`A contact hole 50 is formed as shoWn in FIG. 7. A
`55
`conductive layer 43 can be formed in the active region of the
`substrate by implanting a dopant into the substrate 40. This
`implant can be masked in part by the patterned conductive
`layer 44, and the implanting step may be an ion implanting
`step. The insulating layer 48 can then be formed With a
`thickness suf?cient to cover the ?rst and second patterned
`conductive layers 44 and 44a. The contact hole 50 is then
`formed in the insulating layer 48 to expose a portion of the
`active region betWeen the ?rst and second patterned con
`ductive layers 44 and 44a. The contact hole 50 preferably
`exposes the doped layer 43 Without exposing either of the
`patterned conductive layers.
`
`45
`
`65
`
`6
`The contact hole 50, hoWever, may extend into the ?eld
`region or into the ?rst patterned conductive layer 44 accord
`ing to the alignment of the mask used to form the contact
`hole. As shoWn in FIG. 8, a self-aligned contact hole 50 may
`extend over the ?eld region. Because the second patterned
`conductive layer 44a serves as an etch inhibiting ?lm, the
`contact hole 50 is self-aligned alloWing it to extend over the
`?eld region. Stated in other Words, the second patterned
`conductive layer 44a and associated spacers 46a protect the
`?eld isolation layer 42 from the etch used to form the contact
`hole 50. Accordingly, even With a misalignment of the
`contact hole mask over the ?eld region and over etching to
`insure exposure of the active region, the ?eld isolation layer
`42 is not damaged. The masking and etching margins can
`thus be increased With respect to the prior art. In the event
`the contact hole mask is aligned to the ?rst patterned
`conductive layer 44, a self-aligned contact hole can be
`formed using the spacers 46.
`In the integrated circuit devices of the present invention,
`patterned conductive layers are simultaneously formed on
`both the active and ?eld regions. The patterned conductive
`layer on the ?eld region, hoWever, can be electrically
`isolated thus serving no electrical function in the completed
`integrated circuit device. A self-aligned contact hole can
`thus be formed over the active region of the substrate using
`the patterned conductive layer formed in the ?eld region to
`protect the ?eld isolation layer during the etch used to form
`the contact hole. Because the patterned conductive layer
`over the ?eld region protects the ?eld isolation layer, the
`area over Which the contact hole can be formed is increased
`With respect to the prior art. Accordingly, a greater contact
`margin is alloWed When forming the contact hole.
`Furthermore, the etching margins can be increased Without
`increasing the risk of damaging the ?eld isolation layer.
`Reliability of the integrated circuit device can thus be
`increased because leakage current generated by damage to
`the ?eld isolation layer can be reduced. Furthermore, no
`extra processing steps are required because the second
`patterned conductive layer and the ?rst patterned conductive
`layer (Which can be a transistor gate) can be formed simul
`taneously.
`In the draWings and speci?cation, there have been dis
`closed typical preferred embodiments of the invention and,
`although speci?c terms are employed, they are used in a
`generic and descriptive sense only and not for purposes of
`limitation, the scope of the invention being set forth in the
`folloWing claims.
`That Which is claimed is:
`1. A method for forming a contact hole for a microelec
`tronic structure, said method comprising the steps of:
`de?ning adjacent active and ?eld regions on a substrate,
`and circuits thereon;
`forming a ?eld isolation layer on said ?eld region;
`forming a ?rst patterned conductive layer on said active
`region of said substrate spaced apart from said ?eld
`region;
`forming an etch inhibiting layer on said ?eld isolation
`layer adjacent said active region of said substrate, the
`active region including the ?rst patterned conductive
`layer Wherein said etch inhibiting layer comprises a
`second patterned conductive layer and an insulating
`spacer along a sideWall of the second patterned con
`ductive layer, Wherein the second patterned conductive
`layer does not extend over the active region of the
`substrate, and Wherein the second patterned conductive
`layer is a dummy pattern electrically isolated from the
`substrate and circuits thereon;
`
`NVIDIA Corp.
`Exhibit 1101
`Page 006
`
`

`

`US 6,287,902 B1
`
`7
`forming an insulating layer on said substrate, said ?eld
`isolation layer, said ?rst patterned conductive layer, and
`said etch inhibiting layer; and
`forming a contact hole in said insulating layer exposing a
`portion of said active region betWeen said etch inhib
`iting layer and said ?rst patterned conductive layer.
`2. A method according to claim 1 Wherein said insulating
`layer comprises nitride.
`3. A method according to claim 1 Wherein said ?rst
`patterned conductive layer comprises a conductive portion
`and insulating spacers along sideWalls thereof.
`4. A method according to claim 3 Wherein said steps of
`forming said etch inhibiting layer and forming said patterned
`conductive layer are performed simultaneously.
`5. A method according to claim 1 Wherein said ?eld
`isolation layer comprises oxide.
`6. A method according to claim 1 Wherein said step of
`de?ning said ?eld and active regions comprises the step of
`forming a trench in said substrate, and Wherein said ?eld
`isolation layer ?lls said trench.
`7. A method according to claim 1 Wherein the insulating
`spacer of the etch inhibiting layer extends to the active
`region of the substrate.
`8. A method according to claim 1 Wherein the insulating
`spacer and the insulating layer comprise different materials
`so that the insulating layer can be etched selectively With
`respect to the insulating spacer.
`9. A method according to claim 1 Wherein contact hole is
`formed over the ?eld isolation layer and exposes a portion
`of the etch inhibiting layer Without exposing the ?eld
`isolation layer to thereby increase the area over Which the
`contact hole can be formed Without damaging the ?eld
`isolation layer.
`10. A method according to claim 1 Wherein at least a
`portion of the contact hole is self-aligned With respect to the
`?rst patterned conductive layer and the etch inhibiting layer.
`11. Amethod for forming a microelectronic structure, said
`method comprising the steps of:
`de?ning adjacent active and ?eld regions on a substrate,
`and circuits thereon;
`forming a ?eld isolation layer Which covers said ?eld
`region;
`forming a ?rst patterned layer on said active region of said
`substrate spaced apart from said ?eld region;
`forming a second patterned layer on said ?eld isolation
`layer adjacent said active region of said substrate, the
`active region including the ?rst patterned layer Wherein
`said second patterned layer comprises a patterned con
`ductive layer and an insulating spacer along a sideWall
`of the patterned conductive layer, Wherein the patterned
`conductive layer does not extend over the active region
`of the substrate, and Wherein the patterned conductive
`layer is a dummy pattern electrically isolated from the
`substrate and circuits thereon;
`forming an insulating layer covering said substrate, said
`?eld isolation layer, and said ?rst and second patterned
`layers; and
`forming a contact hole in said insulating layer Wherein
`said contact hole exposes a portion of said active region
`betWeen said ?rst and second patterned layers;
`Wherein said steps of forming said ?rst patterned layer
`and forming said second patterned layer are performed
`simultaneously.
`
`15
`
`35
`
`45
`
`55
`
`65
`
`8
`12. Amethod for forming a microelectronic structure, said
`method comprising the steps of:
`de?ning adjacent active and ?eld regions on a substrate,
`and circuits thereon;
`forming a ?eld isolation layer Which covers said ?eld
`region;
`forming a ?rst patterned layer on said active region of said
`substrate spaced apart from said ?eld region;
`forming a second patterned layer on said ?eld isolation
`layer adjacent said active region of said substrate, the
`active region including the ?rst patterned layer Wherein
`said second patterned layer comprises a patterned con
`ductive layer and an insulating spacer along a sideWall
`of the patterned conductive layer, Wherein the patterned
`conductive layer does not extend over the active region
`of the substrate, and Wherein the patterned conductive
`layer is a dummy pattern electrically isolated from the
`substrate and circuits thereon;
`forming an insulating layer covering said substrate, said
`?eld isolation layer, and said ?rst and second patterned
`layers; and
`forming a contact hole in said insulating layer Wherein
`said contact hole exposes a portion of said active region
`betWeen said ?rst and second patterned layers.
`13. A method according to claim 12 Wherein said ?eld
`region comprises a trench in said substrate, and Wherein said
`?eld isolation layer ?lls said trench.
`14. Amethod according to claim 12 Wherein the insulating
`layer and the insulating spacer comprise different materials
`so that the insulating layer can be etched selectively With
`respect to the insulating spacer.
`15. Amethod for forming a microelectronic structure, said
`method comprising the steps of:
`de?ning adjacent active and ?eld regions on a substrate,
`and circuits thereon;
`forming a ?eld isolation layer Which covers said ?eld
`region;
`forming a ?rst patterned layer on said active region of said
`substrate spaced apart from said ?eld region;
`forming a second patterned layer on said ?eld isolation
`layer adjacent said active region of said substrate, the
`active region including the ?rst patterned layer Wherein
`said second patterned layer comprises a patterned con
`ductive layer and an insulating spacer along a sideWall
`of the patterned conductive layer, Wherein the patterned
`conductive layer does not extend over the active region
`of the substrate, and Wherein the patterned conductive
`layer is a dummy pattern electrically isolated from the
`substrate and circuits thereon;
`forming an insulating layer covering said substrate, said
`?eld isolation layer, and said ?rst and second patterned
`layers; and
`forming a contact hole in said insulating layer Wherein
`said contact hole exposes a portion of said active region
`betWeen said ?rst and second patterned layers;
`Wherein each of said ?rst and second patterned layers
`comprises insulating spacers along sideWalls thereof.
`16. A method according to claim 15 Wherein said insu
`lating layer can be selectively etched With respect to said
`insulating spacers.
`17. A method according to claim 16 Wherein said insu
`lating layer comprises nitride.
`18. Amethod for forming a microelectronic structure, said
`method comprising the steps of:
`
`NVIDIA Corp.
`Exhibit 1101
`Page 007
`
`

`

`US 6,287,902 B1
`
`9
`de?ning adjacent active and ?eld regions on a substrate,
`and circuits thereon;
`forming a ?eld isolation layer Which covers said ?eld
`region;
`forming a ?rst patterned layer on said active region of said
`substrate spaced apart from said ?eld region;
`forming a second patterned layer on said ?eld isolation
`layer adjacent said active region of sa