Paper No.
`Filed: March 10, 2016
`
`
`Filed on behalf of: Samsung Electronics Company, Ltd.
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`By: Naveen Modi (nVidia-Samsung-IPR@paulhastings.com)
`
`Joseph E. Palys (nVidia-Samsung-IPR@paulhastings.com)
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`Paul Hastings LLP
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`NVIDIA CORPORATION
`Petitioner
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`v.
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`SAMSUNG ELECTRONICS COMPANY, LTD.
`Patent Owner
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`Case IPR2015-01327
`Patent No. 6,287,902
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`DECLARATION OF DR. RICHARD B. FAIR
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`Page 1 of 68
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`SAMSUNG EXHIBIT 2006
`NVIDIA v. SAMSUNG
`Trial IPR2015-01327
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`

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`TABLE OF CONTENTS
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`
`I.
`II.
`III.
`IV.
`V.
`VI.
`
`B.
`C.
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`2.
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`3.
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`4.
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`B.
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`Page
`INTRODUCTION ............................................................................................................. 1
`RESOURCES CONSULTED ............................................................................................ 1
`BACKGROUND AND QUALIFICATIONS ................................................................... 2
`LEVEL OF ORDINARY SKILL ...................................................................................... 7
`SCOPE OF PROJECT ....................................................................................................... 8
`CLAIM CONSTRUCTION ............................................................................................... 9
`A.
`“an insulating spacer along a sidewall of the [second] patterned conductive
`layer” (Claims 1, 11, 12, 15, and 18) ..................................................................... 9
`“an insulating layer” (Claims 1, 2, 8, 11, 12, 14-18) ........................................... 10
`“forming a trench in said substrate, and wherein said field isolation layer
`fills said trench” (Claim 6) ................................................................................... 10
`VII. OVERVIEW OF THE ’902 PATENT AND CITED REFERENCES ............................ 11
`A.
`Overview of the ’902 Patent ................................................................................ 11
`Overview of Lee ................................................................................................... 13
`B.
`Overview of Yasushige ........................................................................................ 15
`C.
`VIII. RESPONSE TO PETITIONER’S MAPPING OF THE CLAIMED FEATURES
`TO THE CITED REFERENCES..................................................................................... 19
`A.
`Independent Claim 1 ............................................................................................ 19
`1.
`Lee Does Not Disclose or Suggest a “Second Patterned Conductive
`Layer [that] Is a Dummy Pattern” ............................................................ 19
`Lee Does Not Disclose or Suggest that the “Dummy Pattern” is
`“Electrically Isolated from the Substrate and Circuits Thereon” ............. 22
`Lee Does Not Disclose an “Insulating Spacer Along a Sidewall of
`the Second Patterned Conductive Layer. . . [That] Is a Dummy
`Pattern” .................................................................................................... 28
`One of Ordinary Skill in the Art Would Not Have Combined Lee
`with Yasushige as Proposed by Petitioner ............................................... 30
`Claims 3-5, 7-12, 14-16, and 18 .......................................................................... 32
`1.
`Claim 7 ..................................................................................................... 33
`2.
`Claim 10 ................................................................................................... 34
`Claims 2 and 17 ................................................................................................... 35
`C.
`Claims 6 and 13 ................................................................................................... 35
`D.
`CONCLUSION ................................................................................................................ 37
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`IX.
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`
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`i
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`Declaration of Dr. Richard B. Fair
`IPR2015-01327
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`I.
`
`INTRODUCTION
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`1.
`
`I have been retained by Samsung Electronics Company, Ltd. (“Patent
`
`Owner” or “Samsung”) for this inter partes review proceeding. I understand that
`
`this proceeding involves U.S. Patent No. 6,287,902 (“the ’902 patent”). I
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`understand the ’902 patent is assigned to Samsung and issued from U.S. Patent
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`Application No. 09/318,188, which is a division of U.S. Patent Application No.
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`08/748,148, filed on November 12, 1996 (now abandoned).
`
`II. RESOURCES CONSULTED
`I have reviewed the ’902 patent, including claims 1-18. I have also
`2.
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`reviewed the Petition for Inter Partes Review (Paper No. 2) filed with the U.S.
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`Patent and Trademark Office (“Office”) by nVidia Corporation (“Petitioner” or
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`“nVidia”) on June 2, 2015 (Paper No. 2, the “Petition”). I have also reviewed the
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`Patent Trial and Appeal Board’s (“Board”) decision to institute inter partes review
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`(Paper No. 9, the “Decision”) of December 9, 2015, and any other materials
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`identified in this declaration.
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`3.
`
`I understand that in this proceeding the Board instituted review of
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`the ’902 patent on three grounds: (1) obviousness of claims 1, 3-5, 7-12, 14-16,
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`and 18 over KR App. No. 1994/021255 to Lee (“Lee”, Ex. 1107) in view of JP Pub.
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`No. H7-86158 to Yasushige (“Yasushige”, Ex. 1109); (2) obviousness of claims 2
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`and 17 over Lee, Yasushige, and U.S. Patent No. 4,916,514 to Nowak (“Nowak”,
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`Declaration of Dr. Richard B. Fair
`IPR2015-01327
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`Ex. 1110); and (3) obviousness of claims 6 and 13 over Lee, Yasushige, and U.S.
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`Patent No. 4,952,524 to Lee et al. (“Lee II”, Ex. 1111). (Decision at 19.) I have
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`reviewed the exhibits and other documentation supporting the Petition that are
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`relevant to the Decision and the instituted grounds, and any other material that I
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`reference in this declaration.
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`III. BACKGROUND AND QUALIFICATIONS
`I have summarized in this section my educational background, career
`4.
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`history, publications, and other relevant qualifications. A more detailed account of
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`my work experience, qualifications, and publications is included in my curriculum
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`vitae, which is appended to this declaration.
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`5.
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`By way of summary, I have been a professor in the Department of
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`Electrical and Computer Engineering at Duke University since 1981. My current
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`tenured position is the Lord-Chandran Professor of Engineering in the Pratt School
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`of Engineering.
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`6.
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`I received my Bachelor of Science degree in Electrical Engineering
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`from Duke University in 1964. In 1966, I received a Master of Science degree in
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`Electrical Engineering from Penn State University. In 1969, I received a Ph.D. in
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`Electrical Engineering from Duke University.
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`7.
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`Since 1969, I have been involved in the research, teaching,
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`development, design, and manufacturing of semiconductor devices and processes.
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`Declaration of Dr. Richard B. Fair
`IPR2015-01327
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`For example, I have experience with thin film processes such as physical and
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`chemical vapor deposition methods, modeling semiconductor technology,
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`designing integrated circuits and semiconductor chips, designing high-density
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`memory and analog circuit layouts, and fabricating integrated circuits. In addition,
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`I have experience in the design, layout, and simulation of analog and digital
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`integrated circuits.
`
`8.
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`From 1969 to 1981, I worked at Bell Laboratories and I had direct
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`experience with the manufacturing, design, and testing of numerous semiconductor
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`devices and integrated circuits, including metal-oxide-semiconductor (MOS)
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`dynamic memory chips. I researched and developed numerous semiconductor
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`devices, including silicon and gallium arsenide transistors, analog and digital
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`integrated circuits, photovoltaic devices, and thin film transistors (“TFTs”)
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`fabricated in laser recrystallized polycrystalline silicon.
`
`9.
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`During my time at Bell Laboratories, I worked on advanced silicon
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`process development in the areas of photolithography, thin film deposition,
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`metallization, etching, cleaning, plasma-assisted processing, LPCVD, ion
`
`implantation doping, and annealing/oxidation.
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`10.
`
`In 1981, I became Professor of Electrical Engineering at Duke
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`University. At the same time, I also served in a joint role as Vice President of the
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`Microelectronics Center of North Carolina (“MCNC”) in Research Triangle Park,
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`Declaration of Dr. Richard B. Fair
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`North Carolina. During 1990-1993, I led the Center for Microelectronic Systems.
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`The MCNC and the Center for Microelectronic Systems were devoted to the
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`development of advanced technologies for fabricating integrated circuits and for
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`improvements in semiconductor manufacturing processes in general. My areas of
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`responsibility as Vice President included analog and digital integrated circuit
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`design, system design, semiconductor fabrication technology, advanced multichip
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`module packaging, and studies in electronic materials, including amorphous
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`semiconductors and multi-layered aluminum and copper interconnects. In my
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`division at MCNC, we designed, fabricated, and tested the world’s first one-
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`million-transistor processor chip in 1987. I also was responsible for the MCNC
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`analytical lab, which included electron microscopy, atomic composition analysis,
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`and sample preparation for reverse engineering studies. I have used such analytical
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`tools to perform reverse engineering of semiconductor devices.
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`11. While at MCNC, I helped setup a state-of-the-art CMOS processing
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`facility and directed research on semiconductor processing including
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`photolithography, wafer cleaning, annealing, ion implantation, plasma-enhanced
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`CVD of thin films, metallization, and anisotropic etching processes. I was also
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`involved in the development of an advanced patterning program that included
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`advanced photoresist development, DUV lithography, and the design and
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`development of a magnetron reactive etching tool. We conducted research on
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`Declaration of Dr. Richard B. Fair
`IPR2015-01327
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`multi-level metal interconnects, barrier metallurgy, organic and inorganic inter-
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`metal dielectrics, anti-reflective coatings, via and trench etching processes, and
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`selective tungsten deposition for via filling. We also had an active research
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`program in characterizing point defects in ion implanted amorphous and single
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`crystal silicon, with the goal of understanding implantation defect annealing effects
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`on dopant impurity diffusion.
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`12.
`
`In 1994, I returned to Duke University full-time. Since then I have
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`continued to teach courses on (1) the design and analysis of analog and digital
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`integrated circuits, (2) semiconductor devices, (3) the chemistry and physics of
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`transistor and integrated circuit fabrication, and (4) thin-film microfluidic devices,
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`fluid dynamics, and applications. In addition, I have an active funded research
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`program that involves undergraduate and graduate students.
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`13.
`
`I have published over 170 papers in refereed and peer-reviewed
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`journals and conference proceedings, contributed chapters to 12 books, edited nine
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`books or conference proceedings, given over 130 invited talks in the field of
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`electrical engineering, and I am a named inventor on 30 granted U.S. patents and
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`24 pending U.S. patent applications.
`
`14.
`
`I am also a Life Fellow of the Institute of Electrical and Electronic
`
`Engineers (“IEEE”), a Fellow of the Electrochemical Society, past Editor-in-Chief
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`of the Proceedings of the IEEE, and past Associate Editor of the IEEE
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`Declaration of Dr. Richard B. Fair
`IPR2015-01327
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`Transactions on Electron Devices. I have been listed in Who’s Who in America,
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`Who’s Who in Engineering, Who’s Who in the Semiconductor Industry, Who’s
`
`Who in Frontiers of Science and Technology, Who’s Who in Technology Today,
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`and American Men and Women in Science. I am a recipient of the IEEE Third
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`Millennium Medal, and I was awarded the Solid State Science and Technology
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`Medal of the Electrochemical Society in April 2003.
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`15. Based on my over 45 years of experience in thin film and bulk
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`semiconductor device design, processing technology research and development,
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`integrated circuit fabrication, research in point defects in amorphous and single
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`crystal silicon, and the acceptance of my publications and professional recognition
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`by societies in my field, I believe that I am considered to be an expert in the art of
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`semiconductor processing, semiconductor device design and fabrication, and
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`integrated circuit design and fabrication. I have extensive experience both in
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`research and development, and in the implementation of semiconductor
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`manufacturing processes. I have been qualified numerous times as an expert, and I
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`have given expert opinion testimony relating to semiconductor processing,
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`including MOSFET transistor gate formation, shallow-trench isolation, the use of
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`dummy layer features in patterning, and chemical mechanical planarization.
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`Additionally, I have extensive publications in the field of semiconductor
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`technology, and my accomplishments have been recognized by both academic and
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`Declaration of Dr. Richard B. Fair
`IPR2015-01327
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`professional societies.
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`16.
`
`I am an independent consultant retained by Patent Owner to work on
`
`this case. I am compensated for my services in this case at the rate of $600 per
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`hour. My compensation is not dependent upon my opinions or testimony or the
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`outcome of this case.
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`IV. LEVEL OF ORDINARY SKILL
`I am familiar with the level of ordinary skill in the art with respect to
`17.
`
`the inventions of the ’902 patent as of what I understand is the patent’s November
`
`12, 1996 effective filing date. Specifically, based on my review of the technology,
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`the educational level and experience of active workers in the field, the types of
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`problems faced by workers in the field, the solutions found to those problems, the
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`sophistication of the technology in the field, and drawing on my own experience, I
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`believe a person of ordinary skill in art at that time would have had (i) a bachelor’s
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`degree in electrical engineering, chemical engineering, materials science or physics
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`and 2-3 years of experience in the development of semiconductor fabrication
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`technology, or (ii) a master’s degree in the same areas with 1-2 years of the same
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`work experience. All of my opinions in this declaration are from the perspective of
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`one of ordinary skill in the art as I have defined it here.
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`Declaration of Dr. Richard B. Fair
`IPR2015-01327
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`18. Petitioner’s expert, Dr. Jack C. Lee, has defined the person of
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`ordinary skill in the art as a person with an undergraduate degree in electrical
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`engineering (or an equivalent subject) together with three to four years of post-
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`graduate experience designing semiconductor devices and fabrication processes, or
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`a master’s degree in electrical engineering (or an equivalent subject) together with
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`one to two years of post-graduate experience in designing semiconductor devices
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`and fabrication processes. (Ex. 1116 at ¶ 19.) In my opinion, my definition is
`
`similar to the definition of Dr. Lee offers. While my analysis is based on my
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`definition of the person of ordinary skill in the art, I believe my analysis and
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`opinion would apply equally even under the definition of a person of ordinary skill
`
`in the art Dr. Lee proposes.
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`V.
`
`SCOPE OF PROJECT
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`19.
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`I have been asked to respond to certain of Petitioner’s positions and
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`opinions offered by Dr. Lee, including consider how one of ordinary skill in the art
`
`would have understood the references mentioned above in relation to the claims of
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`the ’902 patent.1 I understand that the Board relied on Petitioner’s positions and
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`Dr. Lee’s opinions in its Decision. As such, when I respond to Petitioner’s
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`1 If I do not address a particular statement made by Petitioner, the Board, or Dr.
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`Lee that does not mean that I necessarily agree with that statement.
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`Declaration of Dr. Richard B. Fair
`IPR2015-01327
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`positions and Dr. Lee’s opinions in this declaration, I am necessarily responding to
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`the Board’s Decision as well. My findings are set forth below.
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`VI. CLAIM CONSTRUCTION
`I understand that Petitioner identified certain terms for construction in
`20.
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`the Petition. (Pet. at 25-27; see also Ex. 1116 at ¶¶ 70-79.) Below is a what I
`
`understand to be a summary of the constructions proposed by Petitioner and Patent
`
`Owner, along with the construction (if any) adopted by the Board in its institution
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`decision.
`
`A.
`
`“an insulating spacer along a sidewall of the [second] patterned
`conductive layer” (Claims 1, 11, 12, 15, and 18)2
`Patent Owner’s Proposed
`Petitioner’s Proposed
`Board’s Construction
`Construction
`Construction
`Plain and ordinary meaning an insulating spacer, along
`a sidewall of the [second]
`patterned conductive layer,
`that prevents etch damage
`to the field isolation layer if
`the contact hole is
`misaligned
`
`No construction
`proposed
`
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`2 I identify only the challenged claims that expressly recite the terms at issue.
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`Declaration of Dr. Richard B. Fair
`IPR2015-01327
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`B.
`Patent Owner’s Proposed
`Construction
`a structure comprising one
`or more electrically
`insulating sublayers
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`“an insulating layer” (Claims 1, 2, 8, 11, 12, 14-18)
`
`Petitioner’s Proposed
`Construction
`Plain and ordinary meaning No construction
`proposed
`
`Board’s Construction
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`C.
`
`“forming a trench in said substrate, and wherein said field
`isolation layer fills said trench” (Claim 6)
`
`Petitioner’s Proposed
`Patent Owner’s Proposed
`Construction
`Construction
`Plain and ordinary meaning Plain and ordinary meaning No construction
`proposed
`
`Board’s Construction
`
`21.
`
`I also understand that the Board construed “dummy pattern,” which is
`
`a term recited in claims 1, 11, 12, 15, and 18, as “a patterned conductive layer that
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`serves no electrical purpose and is electrically isolated from the substrate and
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`circuits thereon.” (Decision at 7.)
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`22.
`
`I have considered the constructions proposed by the Petitioner, the
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`Patent Owner, and the Board. My analysis and conclusions as set forth below in
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`Section VIII remain the same under any of these constructions. For the remaining
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`claim terms of the ’902 patent that were not identified for construction by any
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`party (including the Board), I have given those terms their plain and ordinary
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`meaning, as would be understood by a person of ordinary skill in the art, at the
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`Declaration of Dr. Richard B. Fair
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`time of the invention, having taken into consideration the language of the claims,
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`the specification, and the prosecution history of record.
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`VII. OVERVIEW OF THE ’902 PATENT AND CITED REFERENCES
`A. Overview of the ’902 Patent
`23. The ’902 patent is directed to a method of providing improved
`
`alignment tolerances for contact holes made to scaled microelectronic structures.
`
`(Ex. 1001 at 2:44-48.) A problem that the ’902 patent addresses is how to reliably
`
`make contact holes for MOSFETs in smaller and smaller spaces on a wafer when
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`device integration density increases. (Id. at 2:10-41.) For instance, the ’902 patent
`
`notes that a misaligned contact hole 24 may expose a portion of the active region
`
`of a MOSFET and an adjacent field region that may lead to the flow of leakage
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`currents into the well area of the MOSFET. (Id. at 2:10-20, Fig. 2.)
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`24. To remedy the above problem resulting from contact hole
`
`misalignment, the ’902 patent discloses an exemplary method of forming etch
`
`inhibiting layers on the field isolation region adjacent to the active region (where
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`transistors are formed). The etch inhibiting layer improves alignment tolerance for
`
`a contact hole between a first patterned conductive layer on an active region of the
`
`substrate and an adjacent field region (which isolates an active region). (Id. at
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`4:41-50.) The exemplary solution disclosed in the ’902 patent may be better
`
`understood by referring to the description associated with figures 4-8.
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`25. Figure 4 of the ’902 patent discloses an exemplary embodiment in
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`which a contact hole 50 is placed between first and second patterned conductive
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`layers 44, 44a to make contact to the doped area 43 (source or drain of a transistor)
`
`in the active region. (Id. at 4:10-37.)
`
`
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`26. An insulating layer 48 covering the first and second patterned
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`conductive layers 44, 44a, active region 43, and field isolation layer 42 is etched to
`
`form contact hole 50. (Id. at 5:62-65, 6:8-11, Fig. 7.)
`
`27. Conductive layer 44a (annotated in pink below), which is formed on
`
`the field isolation layer 42, in combination with sidewall spacers 46a (annotated in
`
`blue below) acts as an etch inhibiting layer protecting the field isolation layer from
`
`any undesired etching in case of a contact hole misalignment. (Id. at 6:1-18, Fig. 8
`
`(annotated below).) Conductive layer 44a, which is electrically isolated, is a
`
`dummy pattern that protects against contact hole misalignment. (Id. at 4:25-30,
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`5:33-44, 6:20-23.) According to the ’902 patent, forming an electrically isolated
`
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`conductive layer 44a that serves no electrical function was “unlike methods of the
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`Declaration of Dr. Richard B. Fair
`IPR2015-01327
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`prior art.” (Id. at 5:33-44.)
`
`
`
`(Id. at Fig. 8 (annotated).)
`
`28. Claims 1-18 of the ’902 patent recite some of the novel features
`
`discussed above that protect the field region from contact-hole misalignment,
`
`resulting in improved margins for forming contact holes. For instance, claim 1 of
`
`the ’902 patent recites, inter alia, “forming an etch inhibiting layer on said field
`
`isolation layer adjacent said active region of said substrate, . . . wherein said etch
`
`inhibiting layer comprises a second patterned conductive layer and an insulating
`
`spacer along a sidewall of the second patterned conductive layer, . . . wherein the
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`second patterned conductive layer is a dummy pattern electrically isolated from the
`
`substrate and circuits thereon.” (Ex. 1001, claim 1.)
`
`B. Overview of Lee
`29. Lee discloses a prior art structure in Fig. 1(a), in which the active
`
`region is isolated by a field oxide layer 12 on a semiconductor substrate 11. (Ex.
`
`13
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`1107 at 3.) A MOS gate 14 is also shown that is “formed by depositing gate oxide
`
`layer, poly and gate caps in . . . sequence and then etching them.” (Id.) Lee
`
`recognizes that in prior art devices, a contact hole misalignment may cause damage
`
`to the gate sidewall of the MOS gate or may damage the field oxide layer resulting
`
`in junction leakage. (Id.) Lee illustrates these issues in figure 1(b). (Id.)
`
`30. Lee’s first embodiment is described with reference to figure 3b, which
`
`is shown below:
`
`
`
`(Id. at Fig. 3(b).)
`
`31. Lee describes the first embodiment as follows: “At this time, the etch
`
`stop layer is formed … in the form of a sidewall through a deposition and etch-
`
`back process using the step area formed on the lower layer without any additional
`
`mask.” (Id. at 6.). In Fig. 3b above, it can be seen that the step area referred to by
`
`Lee is the field oxide layer on which the etch stop layer 34-2 is formed “on the
`
`lower layer.” (Id.)
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`14
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`32.
`
`In a second embodiment, Lee discloses “forming an etch stop layer
`
`(44-2) using an internal connection line (44-3) passing adjacently or the step of a
`
`dummy pattern when the step at the lower layer used to form the etch stop layer in
`
`the first embodiment is not sufficient.” (Id. at 7.) Lee is completely silent on the
`
`structure or the constituent layers of the “dummy pattern.” For instance, Lee does
`
`not explain whether the “dummy pattern”3 takes the shape of a gate (such as MOS
`
`gate 34 in Fig. 3(a)) or any other structure. Nor does Lee disclose whether the
`
`“dummy pattern” includes a conductive portion. Neither does Lee disclose that the
`
`“dummy pattern” is electrically isolated. All Lee discloses is that the etch stop
`
`layer 44-2 may be formed using a “dummy pattern” as a step when the step area of
`
`the field oxide layer is insufficient.
`
`C. Overview of Yasushige
`33. Yasushige relates to a method of forming a BiCMOS semiconductor
`
`device with a lightly doped drain (LDD) structure. (Ex. 1109 at abstract.) In
`
`certain embodiments of Yasushige, dummy patterns are formed around the base
`
`region of a bipolar transistor simultaneously with the gate electrode of a MOS
`
`
`3 The discussion here is specific to Lee’s disclosure of “dummy pattern” and is not
`
`to be confused with the term “dummy pattern” recited in the claims of the ’902
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`patent.
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`transistor. For instance, figure 1 of Yasushige illustrates dummy patterns (7d)
`
`formed on an insulation film (5).
`
`
`
`(Id. at Fig. 1.)
`
`34. One of ordinary skill in the art would have understood that the
`
`problem Yasushige was trying to solve was how to form lightly doped drain (LDD)
`
`sidewalls on MOS transistors without deterioration in the base regions of bipolar
`
`transistors formed in the BiCMOS device. (Id. at ¶¶ [0027] – [0028].) As shown
`
`in figures 4 and 5, dummy patterns 7d are formed around the base region 14b of a
`
`bipolar transistor Tr3, and the dummy patterns 7d and are “electrically isolated
`
`from the base region by an isolation region 5.” (Id. at ¶ [0041].) When film 12 of
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`the base region is removed by wet etching, the dummy patterns 7d act as an etch
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`stopper. (Id. at Figs. 4, 5, ¶¶ [0045]-[0046].) At this time, the MOSFET portion of
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`the device is covered by a resist pattern 33. (Id. at Fig. 4.) But during this wet etch
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`of the base region isolation film, the sidewall spacers that would have formed on
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`the side of the dummy patterns 7d are removed from one side of the dummy
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`patterns 7d. (See id. at Fig. 7, illustrating that the dummy patterns only have
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`spacers 37 on one side.) By doing so, the area of isolation region 5 adjacent to the
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`active area in the bipolar junction portion is left unprotected during any subsequent
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`etching, such as contact hole formation.
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`35. One of ordinary skill in the art would have also understood that
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`Yasushige is not concerned about avoiding damage to the isolation region 5. This
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`is evident from the fact that there is no dummy pattern 7d or any other mask
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`present over the field oxide regions during the anisotropic etching of the SiO2 film
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`12. (See id. at Fig. 6 (below with annotations added).) Rather, the dummy patterns
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`7d are added to provide larger tolerance during the formation of resist pattern 36.
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`(Id. at ¶ [0049].) It is the resist pattern 36 that carries out Yasushige’s purpose of
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`protecting the active region of the transistor (35) during the anisotropic etching
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`process. (Id. at ¶ [0049].)
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`IPR2015-01327
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`36. Moreover, one of ordinary skill in the art would have understood that
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`Yasushige is not concerned about avoiding damage to the field oxide region during
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`the contact hole formation. For instance, the only discussion of the contact hole, as
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`shown in figure 8 of Yasushige, relates to an embodiment where dummy patterns
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`are not used. In the embodiment relating to figure 8, the contact holes are made
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`through the thick interlayer dielectric film (19), without any protection from a
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`dummy gate and the sidewall spacers of the dummy pattern for any field oxide
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`region. (See id. at Fig. 8 (annotated).)
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`37. As is shown in Figure 8, the field isolation regions (5) are covered
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`only by the dielectric film (19) and are not protected by a dummy pattern.
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`VIII. RESPONSE TO PETITIONER’S MAPPING OF THE CLAIMED
`FEATURES TO THE CITED REFERENCES
`A.
`38.
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`I understand that independent claim 1 recites a “second patterned
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`Independent Claim 1
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`conductive layer [that] is a dummy pattern electrically isolated from the substrate
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`and circuits thereon.” I also understand that independent claim 1 further recites
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`“an insulating spacer along a sidewall of the second patterned conductive layer.” It
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`is also my understanding that Petitioner and Dr. Lee contend that Lee and
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`Yasushige disclose these features. (Pet. at 31-41; Ex. 1116 at ¶¶ 95-108; see also
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`Decision at 12-15.) In my opinion, this is not correct for at least the following
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`reasons.
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`1.
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`Lee Does Not Disclose or Suggest a “Second Patterned
`Conductive Layer [that] Is a Dummy Pattern”
`39. Lee discloses a “second embodiment” with respect to figure 4. Lee
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`does not provide a detailed discussion of figure 4 and simply states that figure 4
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`discloses “a method of forming an etch stop layer (44-2) using an internal
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`connection line (44-3) passing adjacently or the step of a dummy pattern when the
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`step at the lower layer used to form the etch stop layer in the first embodiment is
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`not sufficient.” (Ex. 1107 at 7, emphasis added.) It is my understanding that
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`Petitioner assumes that element “44-3” in Lee refers to the “dummy pattern” and it
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`is my understanding that Dr. Lee confirmed this assumption during his deposition.
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`(Pet. at 36, “dummy pattern 44-3”; see also Ex. 2005 at 152:25-153:5, 153:18-19.)
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`This is incorrect because Lee never annotates the “dummy pattern” by element 44-
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`3. (See Ex. 1107 generally.) Lee only refers to an internal connection line 44-3
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`and not a dummy pattern 44-3.
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`40. Having assumed that Lee discloses a “dummy pattern 44-3,” which it
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`does not, Petitioner and Dr. Lee try to analogize “dummy pattern 44-3” with MOS
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`gate 34 and from that analogy, they conclude that the “dummy pattern” in Lee is a
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`“patterned conductive layer” like the polysilicon layer in MOS gate 34. (Pet. at
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`36-37; see also Ex. 1116 at ¶ 102.) One of ordinary skill in the art would not have
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`understood that the “dummy pattern” in Lee is a “patterned conductive layer”
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`because there is no disclosure in Lee whether the internal connection line 44-3, let
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`alone the “dummy pattern,” has the same structure and composition as MOS gate
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`34. Nor is there any disclosure in Lee that the layers of internal connection line 44-
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`3, let alone the “dummy pattern,” would have been patterned in the same sequence
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`as MOS gate 34. In fact, Petitioner and Dr. Lee acknowledge that “other
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`mechanical structures are possible” for forming the “dummy pattern” in Lee. (Pet.
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`at 37; Ex. 1116 at ¶ 104.) Therefore, it is my opinion that one of ordinary skill in
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`the art would not have concluded from Lee’s silence regarding the “dummy pattern”
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`that the “dummy pattern”4 has the same structure as MOS gate 34, and that by
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`implication the “dummy pattern” is a “patterned conductive layer” because MOS
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`gate 34 has a patterned poly layer.
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`41.
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`It is my understanding that Dr. Lee contends that the “dummy pattern”
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`in Lee is most likely to be a gate structure like MOS gate 34 because “forming a
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`gate pattern is most efficient given the already existing patterning process for gates
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`throughout the chip.” (Pet. at 37, citing Ex. 1116 at ¶ 104.) Dr. Lee also contends
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`that a mechanical structure such as a “dummy pattern” should be “electrically
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`isolated . . . to prevent accidental electrical connections or shorting damage.” (Ex.
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`1116 at ¶ 104.) However, one of ordinary skill in the art would have known that a
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`simple way to prevent accidental electrical connection or shorting is to make the
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`“dummy pattern” from a non-conductive material