MOSIS Scalable CMOS Design Rules
`
`(revision 7)
`
`J671,-] P1?
`
`the M0515' Service
`Information Sciences Institute
`
`University of Southern California
`4676 Admiralty Way
`Marina. del Rey, CA 90292
`pl@lSl.€(lLl
`August 1, 1995
`
`1
`
`Introduction
`
`1.1
`
`SCMOS Design Rules
`
`This document defines the official layout design rules for MOSIS scalable CMOS (SCl\lOS)
`design technology. lt supercedes all previous revisions. {xii
`In SCMOS technology, circuit geometries are drawn according to Mead and ConWay”s
`,\—based methodology
`The unit of measurement, x\, can easily be scaled to different
`fabrication processes as semiconductor technology advances.
`A user design submitted to MOSIS in SCMOS teclmology should be in either Calma
`GDSH format
`[1] or Caltech Intermediate Form (CIF version 2.0)
`Each design has
`a technology (lesigna2‘i01z t.hat goes with it for the purpose of MOSlS’s data prep. At the
`moment, three designations are used to specify CMOS processes. Each designation may have
`one or more options associated for the purpose of either (1) special features for the target
`process or
`the presence of novel device in the design. At the time of writing, MOSIS is
`offering six CMOS processes from three different foundries with drawn feature sizes ranging
`from 2.0 am down to 0.6 pm.
`A list of the things that have either been revised or added since our last release can be
`found in Appendix A. Please refer to the specific sections for detailed descriptions.
`
`2 Standard SCMOS
`
`The standard CMOS technology accessed by MOSIS is a single polysilicon. double metal.
`bulk CMOS process with enhancement—mode 'n~MOSFET and p—MOSFET devices
`
`SAMSUNG EXHIBIT2003
`
`NVIDIA V. SAMSUNG
`
`TRIAL IPR2015—01327
`
`Page 1 of 28
`
`
`
`(revision 7)
`
`J671,-] P1?
`
`the M0515' Service
`Information Sciences Institute
`
`University of Southern California
`4676 Admiralty Way
`Marina. del Rey, CA 90292
`pl@lSl.€(lLl
`August 1, 1995
`
`1
`
`Introduction
`
`1.1
`
`SCMOS Design Rules
`
`This document defines the official layout design rules for MOSIS scalable CMOS (SCl\lOS)
`design technology. lt supercedes all previous revisions. {xii
`In SCMOS technology, circuit geometries are drawn according to Mead and ConWay”s
`,\—based methodology
`The unit of measurement, x\, can easily be scaled to different
`fabrication processes as semiconductor technology advances.
`A user design submitted to MOSIS in SCMOS teclmology should be in either Calma
`GDSH format
`[1] or Caltech Intermediate Form (CIF version 2.0)
`Each design has
`a technology (lesigna2‘i01z t.hat goes with it for the purpose of MOSlS’s data prep. At the
`moment, three designations are used to specify CMOS processes. Each designation may have
`one or more options associated for the purpose of either (1) special features for the target
`process or
`the presence of novel device in the design. At the time of writing, MOSIS is
`offering six CMOS processes from three different foundries with drawn feature sizes ranging
`from 2.0 am down to 0.6 pm.
`A list of the things that have either been revised or added since our last release can be
`found in Appendix A. Please refer to the specific sections for detailed descriptions.
`
`2 Standard SCMOS
`
`The standard CMOS technology accessed by MOSIS is a single polysilicon. double metal.
`bulk CMOS process with enhancement—mode 'n~MOSFET and p—MOSFET devices
`
`SAMSUNG EXHIBIT2003
`
`NVIDIA V. SAMSUNG
`
`TRIAL IPR2015—01327
`
`Page 1 of 28
`
`
`
`2.1 Well Flavor
`
`Three types of de:.3z'gn.ati0n are used to indicate the flavor of the well (substrate) used for
`fabrication as shown i11 Table l.
`
`Designation Description
`CN
`Scalable CMOS N—well
`SCP
`Scalable C/MOS l-'—well
`SCE
`Scalable CMOS Eithcr—well
`
`Table 1: SCMOS well llavor designations
`
`The SCN and SCP designations with a submitted project are designed for fabrication
`of the specified Well only. For convenience, in both cases, a project may include the ’other’
`Well, but it will always be ignored. SC/E projects are used for fabrication in any CMOS
`process. N—well or l"«well (either). A project with SCH designation must include both wells
`(and correspondingly, Well/substrate contacts for proper bias)
`For any given fabrication
`process, the ’other’ well will be ignored during the mask generation.
`If twin—tub processes
`are offered in the future. both wells will be used.
`
`2.2
`
`SCMOS Options
`
`SCMOS options are used to designate projects Whicli use additional layers beyond the stan-
`dard CMOS technology. Each option is named by a designator that is tacked onto the basic
`designator for its Well flavor. Reader should note that not all possible combinations (with
`Well flavor) are actually available. The currently available SCMOS options are listed in Table
`‘Z.
`
`two undeclared options also exist. One with
`ln addition to the options in Table 2,
`respect to the existence of high voltage MOSFET devices; the other, a tight metal rule for
`high—density metal interconnections. For options available to specific process, please refer to
`Table 3 for the current MOSIS offerings.
`
`2.3
`
`SCMOS Oiferings
`
`MOSIS is currently offering the fabrication processes as shown in Table 3. For each process,
`the list of appropriate SCMOS technology designations is listed. Note that whenever SCNXX
`appears in the table, SCEXX is also appropriate. Likewise, Whenever SC/PXX appears, SCEXX
`is also appropriate.
`
`2CC-D layer not included.
`ZCCD layer not included.
`
`Page 2 of 28
`
`
`
`Designation Long form
`
`Description
`
`E
`
`A
`
`1-‘
`
`A
`
`3M
`
`T— LC
`
`_MEMS
`
`Electrode
`
`Adds a second polysilicon layer (electrode)
`that. can serve as either one of electrode of a poly
`capacitor or as a gate for transistors. A Contact
`layer (electr0de_contact) to metal also exists.
`Adds electrode layer (as in E option) plus a fl
`
`Triple Metal
`
`pbase layer for the construction of Vertical NPN
`transistor. A b11ried_ccd layer is also present.
`for buried-cl1a.nnel CCD applications
`Adds second via (via2) and third metal (metal3)
`layers.
`Linear Capacitor Adds a cap_Well layer for the iniplernentation of
`linear capacitors.
`Micromeclianical Adds two new layers, mems_open and
`Systems
`mems_etcl1_stop for the purpose of micro
`mechanical device construction.
`
`Table 2: SCMOS technology options
`
`Foundry Process
`Orbit
`2.0 pm N—well
`Orbit
`2.0 pm P—well
`AMI
`1.5 ,u,n1 N—well
`Orbit
`1.2 pm N—well
`HP
`AMOSI/CMOS34
`HP
`CMOS26B/G
`
`Lambda
`1.0 pm SCNA, SCNE, SON, SCNA_MEMS
`1.0 pm L I
`, SCP, SCPE_MEMS
`0.8 pm SCNA1, SCNE, SCN, High Voltage
`0.6 ‘urn
`SCNA2
`0.6 /M11
`SCNLC, SON, Tight Metal
`0.5 pm SClV3lVI, SCN, Tight Metal
`
`Table 3: MOSIS SCMOS technology offerings
`
`Page 3 of 28
`
`
`
`3 CIF and GDS Layer Specification
`
`Design geometries (or mask features) can be represented either in GDS—II or Caltech Inter-
`mediate Form (CIF Version
`V\7hile the former is coded in binary format, the latter is a
`plain text file and can be easily interpreted. For detailed syntax and semantic specifications
`of Calma/GDS—H or CIF, plea.se refer to [1] and [3] respectively.
`In GDS 11 format, a mask la.yer is specified by a. layer number between 0 and 63. MOSIS
`now reserves layers nuinberd from 21 to 62 for mask specification and future extension.
`Layers defined out of this range can be used by customers for their own purpose. MOSIS
`will ignore all geometry information on these layers (0 to 20 and 63) and map it to the CIF
`comment layer (CX) if necessary. In this revision, 6 new layers are added starting from layer
`number 21.
`
`is used to indicate high—voltage p—type area. More comprehensive
`o CVP (layer 21)
`information can be found in
`
`CVN (layer 22) is used to indicate high—voltage p—type area.
`
`COP (layer 23) is used to indicate substrate pit opening area for ME.\/IS devices.
`
`CPS (layer 24) is used to indicate substrate p+ etching—stop area for MEMS devices.
`
`0 CC/C (layer
`
`is used for generic contact.
`
`0 XP (layer 26) is used to indicated pad location.
`
`Users should be aware that there exist only one type of physical Contact (i.e. between
`first metal and poly or active), though several have been defined for historical reason and
`are retained for backward compatibility. A complete list of SCWOS layers can be ‘found in
`Table 4 on next page.
`
`4 Sub-micron Rules
`
`The SCMOS design rules have been historically designed for 1.0 — 3.0 micron CMOS tech
`nology. To take full advantage of advanced submicron process technology, a. set of rules have
`been selected to be modified to fit our foundry’s rules.
`Table 5 lists those rules in MOSlS’s HP CMOS26G process that are difierent between
`SCN3M and SCN3M_26G technology specification with ,\ equals to 0.5 and 0.4 pm respec~
`tively.
`
`Page 4 of 28
`
`
`
`GDS 11 number GDS H type
`21
`
`2 2
`
`4
`26
`41
`42
`43
`44
`45
`46
`
`25,47,4s,55
`49
`
`SCMOS la,ye1‘
`P _HIGH_VOLTAGE
`N_HIGH_VOLTAGE
`MEMS_OPEN
`MEMS_ETCH_STOP
`PADS
`P_VVELL
`V_WELL
`ACTIVE
`P_PLUS_SELECT
`N_PLUS_SELECT
`POLY
`CONTACT
`METAL1
`VIA
`METAL?
`GLASS
`ELECTR.ODE
`BURIED_CCD
`PBASE
`CAPNVELL
`VIA2
`METAL3
`COMMENT
`
`CIF name
`CVP
`CVIV
`COP
`CPS
`XP
`CWP
`CWN
`CAA
`CSP
`C-SN
`CPG
`
`CCC, CCP, CCA, C‘/CE
`CMF
`CVA
`C-MS
`COG
`CEL
`CCD
`CBA
`CWC
`CVS
`GMT
`CX
`
`Table 4: SCMOS technology CIF and GDS layers
`
`Page 5 of 28
`
`
`
`SCMOS
`
`SCMOS
`
` '
`
`Description
`
`WELL_W
`WELL_S_D1FF
`WELL_O_ACT)(TOR
`WELL_S_ACT_XTOR
`P O LY _S
`C O N _S
`M 1 _W
`M1 .8
`M2_VV
`M2_S
`M3_VV
`M3_S
`
`Rule
`
`1.1
`1.2
`2.3
`2.3
`3.2
`
`5B.3,6B.3
`7.1
`7 ‘J
`9.1
`9.2
`15.1
`15.2
`
`,\ = 0.5;Ln1
`10
`
`>+'AO\.>-F‘—C/~JUJC»JRDl\')Q‘lC)‘ILO
`
`(Tight. Metal)
`A 2 0.314111
`
`|I
`
`>»
`
`4:7;B
`
`u-P-O?C».'>W[\Di‘.0NJl0OiO('~OE
`
`ooc;«c.4oc.o<;oo:v.\:o.'»:x>m<*.}3§E3
`
`Table 5: SCMOS options for C/MOS26G
`
`Page 6 of 28
`
`
`
`5
`
`SCMOS Design Rules
`
`Well (CWN, CWP)
`
`1.1
`
`Mi11i111u111 Width
`
`Mi11i111u1'11 Sp‘c1L’111g between wells at differe11t potelltial
`1.2
`1.3 Millimum spacing betwee11 wells at same p0te11tia1
`1.4
`3/Ii11i1'1111111 spacing bet.Wee11 Wells of differe11’r. type
`(if both are drawn)
`
`10
`
`9
`U 01' 6
`
`Page 7 of 28
`
`
`
`Active (CAA)
`
`2.1 Minimum width
`
`2.2 Miniuium spacing
`2.3
`Source / drain active to well edge
`2.4
`Substrate/Well coxitact active to well edge
`2.5 Minimum spacing between active of diflerent implant
`
`1
`
`Page 8 of 28
`
`
`
`Poly (CPG)
`
`3.1
`
`3.2
`
`3.3
`
`3.4
`
`3.5
`
`.VIiI1imum Width
`
`Minimum spaciilg
`
`Minimum gate extension of active
`
`.\’Iinimu1I1 active ext.e11si0I1 of ploy
`
`Minimum field poly to active
`
`3.5__>%
`
`CPGI
`I CAA
`
`CPG
`
`%
`
`3.3
`
`Page 9 of 28
`
`
`
`Select (CSN, CSP)
`
`4.1
`
`4.2
`
`4.3
`
`4.4
`
`Minimum select spacing to Cham1el of transistor to
`ensure adequate source/drain Width
`Minimum select overlap of active
`
`Nlinimum select overlap of Contact
`
`Minimum select width and spacing
`(Note: P—se1eCt and N—select may be coincident, but
`must not overlap)
`
`Page 10 of 28
`
`
`
`Simple Contact to Poly (CCP)
`
`-5.1.a Exact c011taCt size
`
`-5.2.21 Mi11i1‘nu111 poly overlap
`
`:3.3.a Mi11i11111n1 Contact spacing
`
`Page 11 of 28
`
`
`
`Simple Contact to Active (CCA)
`
`6.1.21 Exact co11t.act size
`
`6.2.a Mi11imum active overlap
`
`6.3.8. Minimum Contact spacing
`
`6.4.8. Minimum spacing to gate of transistor
`
`Page 12 of 28
`
`
`
`Alternative?’ Contact to Poly (CCP)
`
`5.1.b Exact Contact size
`
`5.2.b Minimum poly overlap
`5.-3.b
`1\~‘Iinimum Contact spacing
`5.4.b Minimum spacing to other poly
`-5.-5.b Minimunl spacing to active (one Contact)
`5.6.b Minimum spacing to active (many Contacts)
`
`5.1.b
`
`5.2.b
`
`¢
`
`* .
`
`CPG
`
`4 b5..
`
`5.6.b ¢
`
`3If you have difficulties with half lambda rule.
`
`Page 13 of 28
`
`
`
`Alternative4 Contact to Active (CCA)
`
`6.1.b Exact Contact size
`
`62.13 Minimum active overlap
`
`6.3.b Minimum Contact spacing
`
`6.4.b Minimum spacing to diffusion active
`6.-5.b Minimum spacing to gate of transistor
`6.6.b Minimum sapcing to field poly (one contact)
`6.7.1) Minimum spacing to field poly (many Contacts)
`6.8.1) Minimum spacing to poly Contact
`
`6.6.b
`
`411" you have difficulties with half lambda rule.
`
`Page 14 of 28
`
`
`
`Metall (CMF)
`
`7.
`
`7.
`
`7.7"!
`r.
`
`7.
`
`Mi11i111uII1 Width
`
`.21 Mi11i111uI11 spacing
`' .b5 l\rIinimum tight metal spacing
`l\/IinimuI11 overlap of poly co11taCt
`
`l\«'Iini111um overlap of active Contact
`
`5Only allowed between minimum width wires, otherwise use regular spacing rule.
`
`Page 15 of 28
`
`
`
`Vial (CVA)
`
`8.1
`
`Exact size
`
`8.2 Minimum vial spacing
`
`8.3 Minimum overlap by lnet/all
`
`8.4 Minimum spacing to Contact
`
`8.-5 Minimum spacing to poly or active edge
`
`Page 16 of 28
`
`
`
`Metal2 (CMS)
`
`9.1
`
`.\vIi11i1'n111'n Width
`
`9 . 2 . a Mi11i1nu1I1 spacing
`9.2.136 Mi11i111u1I1 tight. metal spacing
`9.3 Millimum overlap of Vial
`
`6O11ly allowed between minimum width wires, otherwise use regular spacing rule.
`
`17
`
`Page 17 of 28
`
`
`
`Overg1ass7 (COG)
`
`10.1 Minimum bonding pad Width
`
`10.2
`
`l\'llIllIIl111’I1 probe pad width
`
`Pad overlap of glass opening
`10.3
`10.4 Minimum pad spacing to unrelated metal28
`10.5 Minimum pad spacing to unrelated metall, poly,
`electrode or active
`
`,u.m
`100 x 100
`
`75 X 75
`
`6
`
`30
`
`15
`
`10.1 10.2
` ——-9
`
`7Rules in this section are in unit of pm.
`8And metal3 if triple metal used.
`
`Page 18 of 28
`
`
`
`Electrode for Capacitor (CEL — Analog Option)
`
`11.1
`
`.\li11i111u1n width
`
`11.2 Mi11imun1 spacing
`
`11.3
`
`3/li11i111u111 poly overlap
`
`11.4 Mi11in1um spacing to active or well edge
`
`11.5 Mi11i1n111n spacing to poly Contact
`
`Page 19 of 28
`
`
`
`Electrode for Transistor (CEL - Analog Option)
`
`12.1
`
`1\/Iinimum width
`
`12.2 Minimurii spacing
`
`12.3 Minimum electrode gate overlap of active
`
`12.4 Minimum spacing to active
`
`12.-5 Minimum spacing or overlap of poly
`
`12.6 Minimum spacing to poly or active Contact
`
`Page 20 of 28
`
`
`
`Electrode Contact (CCE - Analog Option)
`
`13.1
`
`Exact Contact size
`
`13.2
`
`Mi11i111u111 Contact spacing
`
`13.3 Mi11i111um electtrode overlap (011 capacitor)
`13.4 Mi11imu111 electrode overlap (not 011 capacitor)
`13.5 Mi11i111u1n spacti11g to poly or active
`
`Page 21 of 28
`
`
`
`Via2 (CVS - Triple Metal Option)
`
`14.1
`
`Exact size
`
`14.2 Minimum spacing
`
`14.3 Minimum overlap by meta12
`
`14.4 Minimum spacing to Vial
`
`Page 22 of 28
`
`
`
`Metal3 (CMT — Triple Metal Option)
`
`15.1
`
`.\'Ii11i1'm1m width
`
`15.2
`
`.\/Ii11i111u1n spa.ci11g to meta13
`
`15.3 Mi11imum overlap of Via2
`
`Page 23 of 28
`
`
`
`NPN Bipolar Transistor (CBA - Analog Option)
`
`16.1 All active Contact
`
`16.2 Minimum select overlap of emitter coiitact
`
`16.3 Winimum pbase overlap of einitter select
`
`3
`
`2
`
`16.4
`
`16.5
`
`\1i11imum spacing between emitter select and base select 4
`
`\/Iinimum pbase overlap of base select
`
`2
`
`16.6 Minimum select overlap of base Contact
`
`16.7
`
`16.8
`
`16.9
`
`NIiI1imu1'I1 nwell 0ve1'1ap of pbase
`
`NIi11i1'num spaciilg between pbase and Collector active
`
`.\"Ii11imum active overlap of collector Contact
`
`16.10 -/Iinimum nwell overlap of collector active
`
`16.11 Minimum select OV€1‘1€Lp
`
`of Collector a.ctiVe
`
`Page 24 of 28
`
`
`
`Capacitor Well (CWC - Linear Capacitor Option)
`
`Minimum width
`
`Mi1'1i11111111 spacillg
`
`Mini111un1 spacing to exte1'11a1 active
`
`1\vIi11i1'11u1n 0Ve1'1a.p of active
`
`Page 25 of 28
`
`
`
`Linear Capacitor (Linear Capacitor Option)
`
`18.1 Minimum width
`
`18.2 Minimum poly extension of active
`
`18.3 Minimum active overlap of poly
`
`18.4 Minimum poly contact. to active
`
`18.-5 Minimum active Contact to poly
`
`linear
`
`capacitor
`
`Page 26 of 28
`
`
`
`Buried Channel CCD (CCD - Analog Optiong)
`
`19.1
`
`.\»li11iInun1 CCD cllannel active width
`
`19.2 Miniinum CCD cllannel active spacing
`
`19.3 Miniinum CCD implant overlap of channel active
`
`19.4 Mi11i1nun1 outside contact to CCD ilnplant
`
`.\«'Ii11iInu1'n select overlap of electrode (or polv)
`19.5
`.\linin1un1 poly/ electrode overlap within channel active
`19.6
`19.7 Mininiuin contact to channel electrode (or poly)
`
`9Not. for all processes
`
`Page 27 of 28
`
`
`
`References
`
`[1] Cadence Design Systems, Inc./Calma. GDSH Stream. F01*nz.at.Manual, Feb. 1987. Release
`6.0, Documentation No; B97E060.
`
`J.—I. Pi, C. Piflé, and
`[2] J. Ma.1‘shaH, M. Gaitan, M. Zaghloul, D. Novotny, V. Tyree,
`VV. Hansford. Realizing suspended structures on chips fabricated by CMOS foundry
`processes through the M0818 service. Technical Report NISTIR—5402, National Institute
`O7‘
`of Standards and Technology. U.S. Department. of Commerce, Gaithersburd MD. 1994.
`
`C. Mead and L. Conway. Introducttion to VLS'1.S'y.steIns. Addison~VVesley, 1980.
`
`[4]
`
`H. E. Weste and K. Eshraghian. P7‘z'I2.c1.'ple.3 of C'.MOS' VL-5'1 1)e.sign.: A .S'y.3tcxn1. Per-
`spective. Adc1iso11—VVes1ey, 2nd. edition, 1993.
`
`Page 28 of 28
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