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`SAMSUNG EXHIBIT 2002
`NVIDIA v. SAMSUNG
`Trial IPR2015-01320
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`E.“Forming a trench in said substrate, and wherein said field
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`isolation layer fills said trench” is construed to according
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`to its plain and ordinary meaning.
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`F.“Insulating spacer along a sidewall" is construed according
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`to its plain and ordinary meaning.
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`G. “Reference voltage” is construed toxnean a voltage level whose
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`steady value serves as a basis for comparison or operation.
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`H.“Controlling propagation delay time” is construed to mean
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`controlling the time from input
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`to output of a signal of a
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`semiconductor memory.
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`I. “A gate insulating layer” is construed to mean
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`a gate
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`comprising one or more insulating layers.
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`J. “Depositing a third.metal gate electrode layer onto the second
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`metal gate electrode layer” is construed to mean depositing
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`a third metal gate electrode layer comprised of one or more
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`metal sublayers onto the second metal gate electrode layer.
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`K.“Depositing a second metal gate electrode layer onto inner
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`sidewalls of the spacers and onto an upper surface of the
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`patterned first metal gate electrode layer” is construed to
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`according to its plain and ordinary meaning.
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`L.“Sending parallel digital video data” is construed to mean
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`transmitting all bits of a given character of the video data.
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`M. “Means for generating a cable sensing signal to be sent to said
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`first external video port over the digital cable,
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`thereby
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`informing the video controller of the digital cable connection
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`state of said first external port” has a function which is
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`construed as generating a cable sensing signal to be sent to
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`first external video port over the digital cable.
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`The means
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`are construed to be the DVCC and resistor R1 depicted in Figure
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`14 of U.S. Patent No. 6,804,724.
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`N.The preamble of claim 19 in the ‘938 Patent is construed as
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`not limiting.
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`It is so ORDERED.
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`Richmond, Virginia
`Date: July ZZ2, 2015
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`/s/
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`L!”
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`Robert E. Payne
`Senior United States District Judge
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`,
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`__, . .
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