Inter Partes Review of USP 6,287,902 – Petition No. 1
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` IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`In re Inter Partes Review of:
`U.S. Patent No. 6,287,902
`Issued: Sept. 11, 2001
`Application No.: 09/318,188
`Filing Date: May 25, 1999
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`For: Methods of Forming Etch Inhibiting Structures on Field Isolation
`Regions
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`FILED VIA PRPS
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`DECLARATION OF DR. JACK LEE IN SUPPORT OF
`PETITION NO. 1 FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,287,902
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`For ease of reference, Dr. Lee refers to this declaration as being in support of “the
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`’902 Petition No. 1” challenging all claims of the ’902 patent.
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`NVIDIA Corp.
`Exhibit 1013
`Page 001
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`I.
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`II.
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`Inter Partes Review of USP 6,287,902 – Petition No. 1
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`TABLE OF CONTENTS
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`Page
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`INTRODUCTION AND QUALIFICATIONS ............................................... 1
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`UNDERSTANDING OF THE GOVERNING LAW ..................................... 4
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`A.
`B.
`C.
`D.
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`Invalidity By Anticipation Or Obviousness .......................................... 4
`Interpreting Claims Before The Patent Office ...................................... 5
`Relevant Time Period For The Obviousness Analysis ......................... 6
`Basis For My Opinion ........................................................................... 6
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`III. LEVEL OF ORDINARY SKILL IN THE ART IN THE RELEVANT
`TIMEFRAME .................................................................................................. 6
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`IV. PERSPECTIVE APPLIED IN THIS DECLARATION ................................. 7
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`V. OVERVIEW OF THE ’902 PATENT ............................................................ 8
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`A.
`B.
`C.
`D.
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`Background ........................................................................................... 8
`Stated Problem ...................................................................................... 9
`Description of ’902 Patent Alleged Invention .................................... 11
`’902 Patent Prosecution History .......................................................... 13
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`VI. OVERVIEW OF THE PRIOR ART ............................................................. 16
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`A. U.S. Patent No. 5,292,677 (“Dennison”) ............................................ 16
`B.
`U.S. Patent No. 5,654,570 (“Agnello”) ............................................... 21
`C.
`U.S. Patent No. 5,472,904 (“Figura”) ................................................. 25
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`VII. MOTIVATIONS TO COMBINE THE PRIOR ART REFERENCES ......... 29
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`A. Motivation To Combine Dennison with Agnello ............................... 29
`B. Motivation To Combine Dennison and Agnello with Figura ............. 35
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`VIII. CLAIM CONSTRUCTIONS ........................................................................ 37
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`A.
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`Legal Standard ..................................................................................... 37
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`Exhibit 1013
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`B.
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`C.
`D.
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`“insulating spacer along a sidewall of the [second] patterned
`conductive layer” ................................................................................. 38
`“an insulating layer” ............................................................................ 39
`“forming a trench in said substrate, and wherein said field
`isolation layer fills said trench” ........................................................... 40
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`IX. SUMMARY OF OPINIONS ......................................................................... 41
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`X.
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`FIRST GROUND OF INVALIDITY – OBVIOUSNESS BY
`DENNISON IN COMBINATION WITH AGNELLO ................................. 41
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`Claim 12 .............................................................................................. 41
`A.
`Claim 1 ................................................................................................ 55
`B.
`Claim 2 ................................................................................................ 61
`C.
`Claim 3 ................................................................................................ 62
`D.
`Claim 4 ................................................................................................ 63
`E.
`Claim 5 ................................................................................................ 65
`F.
`Claim 7 ................................................................................................ 65
`G.
`Claim 8 ................................................................................................ 66
`H.
`Claim 9 ................................................................................................ 68
`I.
`Claim 10 .............................................................................................. 69
`J.
`Claim 11 .............................................................................................. 70
`K.
`Claim 12 .............................................................................................. 71
`L.
`M. Claim 14 .............................................................................................. 71
`N.
`Claim 15 .............................................................................................. 71
`O.
`Claim 16 .............................................................................................. 73
`P.
`Claim 17 .............................................................................................. 73
`Q.
`Claim 18 .............................................................................................. 73
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`XI. SECOND GROUND OF INVALIDITY – OBVIOUSNESS BY
`DENNISON IN COMBINATION WITH AGNELLO AND FIGURA ....... 74
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`A.
`B.
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`Claim 6 ................................................................................................ 74
`Claim 13 .............................................................................................. 77
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`NVIDIA Corp.
`Exhibit 1013
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`Inter Partes Review of USP 6,287,902 – Petition No. 1
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`I, Jack Lee, Professor in the Department of Electrical and Computer
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`Engineering at The University of Texas at Austin, hereby declare as follows:
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`I.
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`INTRODUCTION AND QUALIFICATIONS
`1.
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`I have been retained by NVIDIA Corporation (“NVIDIA”) to provide
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`my opinion concerning the validity of U.S. Patent No. 6,287,902 (Ex. 1001, “the
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`’902 patent”) in support of Petition For Inter Partes Review of U.S. Patent No.
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`6,287,902 (“the ’902 Petition”).
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`2.
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`I am an expert in the field of semiconductor process technology and
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`semiconductor design. I have over 30 years of first-hand experience as a
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`researcher, educator, and consultant in this field.
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`3.
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`I received a B.S. degree in Electrical Engineering, with highest
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`honors, in 1980, and an M.S. degree in Electrical Engineering in 1981, both from
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`University of California, Los Angeles. I received a Ph.D. degree in Electrical
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`Engineering in 1988 from University of California, Berkeley (“UC Berkeley”).
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`TRW Microelectronics Center, in the High‐Speed Bipolar Device Program.
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`4.
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`From 1979 to 1984, I was a Member of Technical Staff at the
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`I worked on bipolar device/circuit design, fabrication, and testing. I was promoted
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`to Engineering Group Leader level in 1983.
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`5.
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`I received several academic honors while at UC Berkeley.
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`For example, I won the Best Paper Award from the Institute of Electrical and
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`NVIDIA Corp.
`Exhibit 1013
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`Inter Partes Review of USP 6,287,902 – Petition No. 1
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`Electronics Engineers (“IEEE”) International Reliability Physics Symposium in
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`1988. I was also awarded a Lectureship with my own teaching assistant from UC
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`Berkeley.
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`6.
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`After receiving my Ph.D. in August 1988, I joined the faculty at The
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`University of Texas at Austin (“UT Austin”). As a faculty member, I have taught
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`numerous courses in semiconductor device fabrication and design, at both the
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`undergraduate and graduate levels. I have supervised 40 students who received a
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`doctoral degree under my guidance. I am currently the Cullen Trust for Higher
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`and Computer Engineering at UT Austin.
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`Education Endowed Professor in Engineering #4 in the Department of Electrical
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`7. My current research interests include: high‐K gate dielectrics and
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`metal gate
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`electrodes
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`in
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`semiconductor devices
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`(CMOS/MOSFETs);
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`semiconductor device fabrication processes, characterization and modeling;
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`dielectric processes, characterization and reliability; and alternative transistor
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`channel materials. My research has been partially supported by grants from the
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`National Science Foundation, the Texas Advanced Research Program, the
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`Semiconductor Research Corporation (SRC), SEMATECH, Texas Emerging
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`Technology Funds, and others. Throughout my career, I have been developing
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`improved processing technologies for insulating layers, including isolation regions
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`and preventing defects such as etching-induced defects.
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`NVIDIA Corp.
`Exhibit 1013
`Page 005
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`Inter Partes Review of USP 6,287,902 – Petition No. 1
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`I have authored over 500 journal publications and conference
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`8.
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`proceeding papers, and have coauthored one book and two book chapters on
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`semiconductor devices. I am a named inventor of several U.S. patents, including:
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`• U.S. Patent No. 6,013,546 (“Semiconductor Device Having a
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`PMOS Device with a Source/Drain Region Formed Using a Heavy
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`Atom p-Type Implant and Method of Manufacture Thereof”)
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`• U.S. Patent No. 6,057,584 (“Semiconductor Device Having a
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`Tri-Layer Gate Insulating Dielectric”)
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`• U.S. Patent No. 6,146,934
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`(“Semiconductor Device with
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`Asymmetric PMOS Source/Drain
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`Implant and Method of
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`Manufacture Thereof”)
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`• U.S. Patent No. 6,306,742 (“Method for Forming a High Dielectric
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`Constant Insulator in the Fabrication of an Integrated Circuit”)
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`• U.S. Patent No. 5,891,798 (“Method for Forming a High Dielectric
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`Constant Insulator in the Fabrication of an Integrated Circuit”)
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`9.
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`I have also earned many research awards including the prestigious
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`SRC Inventor Recognition Award from Semiconductor Research Corporation for
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`my work on dielectric technology and characterization.
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`understanding and development of ultra‐thin dielectrics and their application to
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`10.
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`In 2002, I became an IEEE fellow for my “contributions to the
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`Inter Partes Review of USP 6,287,902 – Petition No. 1
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`silicon devices.” I am also an IEEE Electron Devices Society Distinguished
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`Lecturer.
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`11.
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`I have served in various technology consulting and business advisor
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`roles. For example, I have taught short courses on semiconductor device physics
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`and
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`technologies at various semiconductor companies and consortiums
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`(e.g., SEMATECH). I have also organized several international conferences and
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`have given lectures at numerous conferences and symposia, including the
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`International Symposium on VLSI Technologies, the IEEE Symposia on
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`VLSI Technology, and the IEEE International Electron Devices Meeting. These
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`conferences are some of the most prestigious in the field.
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`12. My Curriculum Vitae is provided as Ex. 1003.
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`13. My work in this matter is being billed at a rate of $475 per hour, with
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`reimbursement for necessary and reasonable expenses. My compensation is not in
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`any way contingent upon the outcome of this Inter Partes Review. I have no
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`interest in the outcome of this proceeding or any related litigation.
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`II. UNDERSTANDING OF THE GOVERNING LAW
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`A.
`14.
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`Invalidity By Anticipation Or Obviousness
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`I understand that a claim is invalid if it is anticipated or obvious. I
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`understand that anticipation of a claim requires that every element of a claim is
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`disclosed expressly or inherently in a single prior art reference, arranged as in the
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`claim.
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`Inter Partes Review of USP 6,287,902 – Petition No. 1
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`15.
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`I further understand that obviousness of a claim requires that the claim
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`be obvious from the perspective of a person of ordinary skill in the relevant art, at
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`the time the invention was made. In analyzing obviousness, I understand that it is
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`important to understand the scope of the claims, the level of skill in the relevant
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`art, the scope and content of the prior art, the differences between the prior art and
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`the claims, and any secondary considerations. I also understand that if a technique
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`has been used to improve one device, and a person of ordinary skill in the art
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`would recognize that it would improve similar devices in the same way, using the
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`technique is obvious unless its actual application is beyond his or her skill. There
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`may also be a specific teaching, suggestion or motivation to combine any first prior
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`art reference with a second prior art reference. Such a teaching, suggestion, or
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`motivation to combine the first prior art reference with the second prior art
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`reference can be explicit or implicit in the first or second prior art references.
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`B.
`16.
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`Interpreting Claims Before The Patent Office
`I understand that “Inter Partes Review” is a proceeding before the
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`United States Patent & Trademark Office (“Patent Office”) for evaluating the
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`validity of an issued patent claim. Claims in an Inter Partes Review are given
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`their broadest reasonable interpretation that is consistent with the patent
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`specification. I understand that a patent’s “specification” includes all the figures,
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`discussion, and claims within the patent document. I understand that the Patent
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`Office will look to the specification to see if there is a definition for a claim term,
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`and if not, will apply the broadest reasonable interpretation from the perspective of
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`a person of ordinary skill in the art.
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`C. Relevant Time Period For The Obviousness Analysis
`17.
`I also understand that the earliest patent application filing leading to
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`the ’902 patent was made in November 12, 1996, with a foreign priority date of
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`June 28, 1996. I have therefore analyzed obviousness as of approximately mid to
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`late 1996 or slightly before, understanding that as time passes, the knowledge of a
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`person of ordinary skill in the art will increase.
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`D. Basis For My Opinion
`18.
`In forming my opinion, I have relied on the ’902 patent claims,
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`disclosure and prosecution history, the prior art exhibits to the Petition for Inter
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`Partes Review of the ’902 patent, and my own experience, expertise and
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`knowledge of a person of ordinary skill in the relevant art in the relevant
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`timeframe.
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`III. LEVEL OF ORDINARY SKILL IN THE ART IN THE RELEVANT
`TIMEFRAME
`19.
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`In 1996, I believe that a relevant person of ordinary skill in the art
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`would have had an undergraduate degree in electrical engineering (or equivalent
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`subject) together with three to four years of post-graduate experience designing
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`semiconductor devices and fabrication processes, or a master’s degree in electrical
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`engineering (or equivalent subject) together with one to two years of post-graduate
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`experience in designing semiconductor devices and fabrication processes. This
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`description is approximate, and a higher level of education or skill might make up
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`for less experience, and vice-versa.
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`20.
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`I believe that I would qualify as a person of at least ordinary skill in
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`the art in 1996, and that I have a sufficient level of knowledge, experience, and
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`education to provide an expert opinion in the field of the ’902 patent. Because of
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`my work experience and the earlier date on which I received my bachelor’s,
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`master’s, and Ph.D. degrees in electrical and computer engineering, and because of
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`my work experience, by 1996 my own level of skill likely exceeded the ordinary
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`level of skill in the art.
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`21. However, in my roles as professor of Electrical and Computer
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`Engineering and as a member of technical staff at the TRW Microelectronics
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`Center, I frequently worked with and taught individuals who were persons of
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`ordinary skill in the art as defined above. Accordingly, I am well acquainted with
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`the actual performance of a POSITA as defined above, and can approach technical
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`issues from the perspective of such a person.
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`IV. PERSPECTIVE APPLIED IN THIS DECLARATION
`22. My testimony in this declaration is given from the perspective of a
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`person of ordinary skill in the art at the time of the filing of the ’902 patent, and for
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`some time before then, unless otherwise specifically indicated. This is true even if
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`the testimony is given in the present tense. Each of the statements below is my
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`opinion based on my review of the prior art, the ’902 patent, and the claims, as
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`well as the prior art cited in this declaration and the prosecution history of the ’902
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`patent.
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`V. OVERVIEW OF THE ’902 PATENT
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`A. Background
`23. The purported invention of the ’902 patent relates to forming contact
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`holes in microelectronic structures. For example, integrated circuit memory
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`devices include a plurality of memory cells, and each memory cell is connected to
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`other cells by conductive (metal) lines. ’902 patent at 1:23-25. The cells and
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`conductive (metal) lines are connected to the substrate by contact holes. Id. at
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`1:25-27. The contact holes expose active regions of the substrate. Id. at 1:28-29.
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`Patterned gate electrode layers are generally arranged around the contact holes and
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`are electrically isolated from the contact holes. Id. at 1:32-33.
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`24. Such structures are formed on a semiconductor substrate, as illustrated
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`in Fig. 1. First, a field oxide layer 12 is formed on the substrate 10. Id. at 1:52-53.
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`The field oxide layer may be formed using a LOCOS field oxide layer or
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`alternatively a trench field oxide layer. Id. at 1:45-50, 4:16-18. The field oxide
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`layer defines the active region on the substrate 10. Id. at 1:52-55. Annotated Fig.
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`1 of the ’902 patent shows a cross-sectional view of an integrated circuit device.
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`Id. at Fig. 1.
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`A gate electrode 14 is formed over the active region (highlighted green), and
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`spacers 15 are formed along the sidewall. Id. at 1:52-56. An insulating layer 20 is
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`formed on the surface of the substrate including the gate electrode 14 and the field
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`oxide layer 12. Id. at 1:56-58. A contact hole 16 is formed by etching the
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`insulating layer 20 between the gate and field oxide layer to expose a portion of the
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`active region. Id. at 1:58-60. A conductive layer 18 is formed on the insulating
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`layer and fills the contact hole, creating a contact with the active region. Id. at
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`1:60-65.
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`B.
`Stated Problem
`25. As integrated circuit devices become more highly integrated, the
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`space available for forming devices is reduced. ’902 patent at 1:18-20. For
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`example, the space between the patterned layers is reduced, and accordingly the
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`space available for forming the contact holes is also reduced. Id. at 1:36-38. Thus
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`increased integration reduces the margin available in the placement of the holes,
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`and leads to an increased risk in misaligned contact holes. Id. at 1:41-50.
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`26. Annotated Fig. 2 of the ’902 patent shows a cross-sectional view of an
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`integrated circuit device with a misaligned contact hole 24 exposing a portion of
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`the active region (green) as well as a portion of the field oxide layer 12 (blue) on
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`the field region (brown) in the substrate 10. ’902 patent at 2:10-12. This
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`misalignment results in the formation of a well (red circle) through the field oxide
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`layer 12 thus exposing a portion of a field region. Id. at 2:12-15.
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`When the contact hole 24 is filled with the conductive layer 18, the conductive
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`layer 18 is brought into contact with the well. Id. at 2:17-19. Leakage current may
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`thus flow through the conductive layer 18 into the well area and cause a delay or
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`malfunction in the device. Id. at 2:20-23.
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`C. Description of ’902 Patent Alleged Invention
`27. The ’902 patent addresses the problem of contact hole misalignment
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`by forming a second patterned conductive layer 44a with insulating sidewall
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`spacers 46a on the field region:
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`’902 patent, Fig. 4. Compared to the first patterned conductive layer 44, the
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`second patterned conductive layer is electrically isolated and thus serves as a
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`dummy pattern. Id. at 4:27-30.
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`28. An insulating layer is then formed over the surface of the substrate
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`and the first and second patterned conductive layers. Id. at 3:31-33. A contact
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`hole 50 is formed in the insulating layer 48 exposing a portion of the active region
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`43. Id. at 3:33-35. Because the insulating layer is preferably formed of a material
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`more susceptible to etching than the material used to form the sidewall spacers
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`46a, some misalignment of the contact hole 50 can be tolerated. Id. at 4:37-42. In
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`particular, if the contact hole extends beyond the active region of the substrate
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`encroaching into the field region, a second patterned conductive layer 44a and its
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`sidewall spacers 46a act as an etch inhibitor when etching the insulating layer 48:
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`’902 patent, Fig. 4; Id. at 4:42-48.
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`29.
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`In the structure of the ’902 patent invention, the area over which the
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`contact hole can be formed is larger than the area available using the structure of
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`the prior art cited in the ’902 patent specification. Id. at 4:52-55. In the prior art
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`Fig. 1, the contact hole must be formed between the gate electrode and the field
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`oxide layer so as not to risk operational problems. Id. at 4:55-57. When using the
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`structure of the ’902 patent, the area over which the contact hole can be formed
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`extends over a portion of the field region covered by the second patterned
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`conductive layer. Id. at 4:58-61. Accordingly, a greater contact margin is allowed
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`when forming the contact hole. Id. at 6:31-32. Etching margins can be increased
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`without increasing the risk of damaging the field isolation layer. Id. at 6:33-34.
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`Reliability of the integrated circuit device can thus be increased because leakage
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`current generated by damage to the field isolation layer can be reduced. Id. at
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`6:35-37.
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`D.
`30.
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`’902 Patent Prosecution History
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`I have reviewed the prosecution history of the ’902 patent. While the
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`Patent Office discussed several references during prosecution, it did not discuss the
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`Dennison, Agnello, or Figura patents discussed below, nor were they cited. The
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`Examiner thus likely did not consider any of these references.
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`31.
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`I also note that in applicant’s last Remarks before receiving the Notice
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`of Allowance, applicant distinguished two combinations of references that the
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`examiner had used to reject the claims under 35 U.S.C. § 103. Ex. 1002, FH, pp.
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`113-116. The examiner cited JP 4-63437 (“Michihiro”), US 5,550,076 (“Chen”),
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`and US 5,441,916 (“Motonami”), with a combination of Michihiro in view of Chen
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`and a combination of Michihiro in view of Motonami. Ex. 1004, Michihiro; Ex.
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`1005, Chen; Ex. 1006, Motonami.
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`Michihiro in view of Chen
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`32.
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`In a non-final rejection, the examiner stated that Michihiro disclosed
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`in Figs. 2(e), 4(b), and abstract, all elements of the independent claim except for
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`“an insulating spacer” formed along a sidewall of the first patterned layer and a
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`sidewall of the second pattern layer.” Ex. 1002, FH, Dec. 5, 2000, p. 4; see also
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`Michihiro at Fig. 2e:
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`See also Id. at Fig. 4(a):
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`33. The examiner noted that Chen teaches the obviousness of forming a
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`second patterned layer on a field oxide isolation layer and a first patterned layer on
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`the active region of a substrate, wherein the first and second patterned layers have
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`insulating spacers formed thereon. Ex. 1002, FH, Dec. 5, 2000, p. 5; see also Id.:
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`Accordingly, it would have been obvious to modify the device
`structure of Michihiro by forming the insulating spacers along a
`sidewall of the first and second patterned layers, because as is well
`known, the insulating sidewall spacers would protect and prevent the
`first patterned conductive layer (gate electrode) and the second
`patterned conductive layer from contacting with the other adjacent
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`elements.”1
`34.
`In response, applicant did not dispute that all the elements were
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`disclosed by Michihiro and Chen. Instead, applicant only argued, “there is no clear
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`and particular evidence of a motivation for modifying Michihiro in view of Chen.”
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`Ex. 1002, FH, Mar. 7, 2001, p. 8. In particular, applicant argued that a POSITA
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`could not combine Michihiro with Chen, because “Chen does not teach or suggest
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`the use of a dummy pattern.” Id. at 9 (emphasis in original). Further, “there is
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`simply no mention in Michihiro that it is desirable to prevent damage to the field
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`oxide layer.” Id. “There is nothing in Michihiro which suggests that there is need
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`to include spacers that would prevent damage to the field oxide layer in the event
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`the contact hole is misaligned.” Id. “Applicant respectfully submits that neither
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`reference appreciates that misalignment of the contact hole during formation
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`thereof can be a problem that can damage the field oxide layer.” Id.
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`Michihiro in view of Motonami
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`35. Similarly, applicant submitted that there is no motivation to combine
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`Michihiro with Motonami because, while they both discuss dummy patterns, 1)
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`Michihiro discusses dummy patterns “to make the channels of mixed field effect
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`transistors the same length and suppress fluctuation thereof”; and 2) Motonami
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`only discusses providing dummy interconnections “in the vicinity of a step-like
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`1 All emphasis added unless otherwise indicated.
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`portion so that ‘the first and second conductive interconnection layers are precisely
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`patterned within depth of focus.’” Id. at 11.
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`Notice of Allowance
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`36.
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`In the Notice of Allowance, the Examiner stated: “the prior art of
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`record fails to disclose all the process limitations recited in the base claims,
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`including a combination of a step of forming a dummy pattern as an etch inhibiting
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`layer on a field isolation layer and a step of forming along the sidewalls of a
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`dummy pattern the spacers that will prevent damage to the field oxide layer in the
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`event the contact hole is misaligned.” As discussed below, prior art discloses this
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`combination of limitations.
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`37. However, as explained below in the Overview of the Prior Art and
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`Motivations to Combine the Prior Art References sections, both primary reference
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`Dennison combined with secondary reference Agnello discloses the use of dummy
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`patterns and using the dummy patterns or their spacers to prevent damage to the
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`field oxide layer.
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`VI. OVERVIEW OF THE PRIOR ART
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`A. U.S. Patent No. 5,292,677 (“Dennison”)
`38. The purported invention of the ’902 patent relates to the forming of a
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`dummy pattern and spacers on a field oxide layer to serve as an etch inhibitor layer
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`when forming contact holes. However, Micron Technology, Inc., a major U.S.
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`memory manufacturer, had already addressed these problems and designed and
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`filed a patent application on the features described in the ’902 patent more than
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`three years prior to the filing date of the earliest parent application of the ’902
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`patent. The patent application, U.S. Patent No. 5,292,677 (“Dennison”) (Ex.
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`1007), is titled “Reduced Mask CMOS Process for Fabricating Stacked Capacitor
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`Multi-Megabit Dynamic Random Access Memories Utilizing Single Etch Stop
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`Layer for Contacts” and lists Charles H. Dennison of Boise, Idaho as an inventor.
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`39. Dennison issued as a U.S. patent on March 8, 1994, more than one
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`year before November 12, 1996, the filing date of the earliest U.S. parent
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`application of the ’902 patent. Dennison is thus prior art to the ’902 patent under
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`35 U.S.C. § 102(b).
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`40. As its title suggests, Dennison discloses an improved method for
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`fabricating CMOS Dynamic Random Access Memories (“DRAMs”). A DRAM
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`circuit comprises an array of memory cells, with each cell storing one bit of binary
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`data. Each cell comprises one or more transistors and a capacitor. Dennison at
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`2:21-23, 4:59-61. Specifically, Dennison is directed to a “stacked capacitor
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`DRAM,” wherein the capacitor is stacked above the transistors. Dennison at 1:12-
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`14, 2:44-55. A CMOS (Complimentary Metal Oxide Semiconductor) DRAM uses
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`both N-channel and P-channel MOSFET transistors, in a complimentary fashion.
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`Id. at 1:40-49.
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`41. An example memory cell is shown on the left portion of Dennison
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`Fig. 14:
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`Capacitor
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`Transistors
`Dennison at Fig. 14 (annotations added).
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`
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`42. Figure 1 of Dennison shows this memory cell at an earlier stage of
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`fabrication:
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`
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`Dennison at Fig. 1. To the left, there are two NMOS transistors, with gates labeled
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`20B and 20C. Id. at 10:42-53. The substrate 12 is lightly doped p-type silicon. Id.
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`at 10:47-48. The substrate is oxidized to form a thin gate insulating oxide layer 14
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`under each gate and a thick field oxide region 16. Id. at 10:48-51. The areas of N+
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`doping 18 are formed using an implantation process. Id. at 10:51-52.
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`43. The gates 20B and 20C each comprise a gate conducting layer 22 on
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`top of the insulating oxide layer 14, and this gate conducting layer 22 may
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`comprise a polysilicon layer 24 and a tungsten silicide layer 26. Id. at 10:52-59.
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`On top of the gate conducting layer 22 is a gate insulating protective layer 28. Id.
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`at 10:59-61. Transistor insulating spacer members 19 are formed on either side of
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`each gate 20B and 20C. Id. at 10:62-64.
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`44. A third gate structure is formed just to the right of the gate 20B and
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`19
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`contains the same layers as gates 20B and 20C. Id. at Fig. 1. However, the layers
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`of this structure that correspond to the gate conducting layer 22 in gates 20B and
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`20C in this gate structure are surrounded by insulating layers (field oxide region 16
`
`below, gate insulating protective layer 28 above, and insulating spacer members 19
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`to the left and right—see discussion of limitation 12[g] below for further details)
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`and thus electrically isolated from the substrate and the rest of the components of
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`the memory cell. Id.
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`45. Covering the gate structures and the exposed substrate is a thin first
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`etch stop layer 30, 2 preferably formed from the insulator aluminum oxide. Id. at
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`10:64-68. A thick insulating layer 32 of boro-phospho-silicate glass (BPSG) or
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`another insulator is formed, further covering the gate structures and exposed
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`substrate. Id. at 11:5-8, 11:23-26.
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`46. Next, a hole 41 (which will contain the capacitor) is opened in the
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`insulating layer 32 and etch stop layer 30, as shown in Dennison Fig. 2:
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`2 While Dennison actually refers to “etch stop layer 32” in the cited section, this
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`appears to be a typo. In the figures and elsewhere in the specification (e.g.,
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`Dennison at 11:24, 11:54) this layer is referred to with the number 30.
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`20
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`Se