United States Patent [19]
`Figura et al.
`
`lllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll
`5,472,904
`* Dec. 5, 1995
`
`US005472904A
`[11] Patent Number:
`[45] Date of Patent:
`
`[54] THERMAL TRENCH ISOLATION
`
`[75] Inventors: Thomas A. Figura; Nanseng Jeng,
`both of Boise, Id.
`
`[73] Assignee: Micron Technology, Inc., Boise, Id.
`
`[*] Notice:
`
`The portion of the term of this patent
`subsequent to Aug. 1, 2012, has been
`disclaimed.
`
`[21] Appl. No.: 287,384
`[22] Filed:
`Aug. 8, 1994
`
`Related US. Application Data
`
`[63] Continuation-impart of Ser. No. 205,663, Mar. 2, 1994.
`
`[51] Int. Cl.6 ................................................... .. H01L 21/76
`[52] US. Cl.
`437/67; 437/69; 437/72;
`148/DIG. 50
`[58] Field of Search ................................ .. 437/67, 69, 72;
`148/DIG. 50
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`9/1985 Havemann .............................. .. 576/29
`4,541,167
`9/1989 Ravaglia ......... ..
`437/38
`4,868,136
`1/1990 Chapman et al.
`.. 437/67
`4,892,614
`'... 4.37/72
`4,980,311 12/1990 Namose .......... ..
`.
`5,087,586 2/1992 Chan etal.
`.. 437/72
`437/67
`5,130,268
`7/1992 Liou et al. .......... ..
`5,342,480
`8/1994 Nishizawa et al.
`437/67
`5,382,541
`1/1995 Bajor etal. ............................. .. 437/67
`
`FOREIGN PATENT DOCUMENTS
`
`Japan ..................................... ..
`Japan ..
`
`Japan ..
`
`1/1984
`59-11645
`22342 2/1984
`0121737 6/1985
`61-81649 4/1986
`0228650 10/1986
`0256649 11/1986
`63-87741
`4/1988
`63-137457
`6/ 1988
`63-155747
`6/1988
`2-26039 10/ 1990
`
`0034556 2/1991 Japan ..................................... . . 437/67
`0218049 9/ 1991 Japan .... ..
`437/67
`513566 1/1993 Japan ..................................... .. 437/72
`
`OTHER PUBLICATIONS
`
`Park et al., “A Novel LOCOS-Type Isolation Technology
`Free of the Field Oxide Thinning Effect”, Extended
`Abstracts of the 1993 International Conference on Solid
`State Devices and Materials, Makuhari, 1993, pp. 528-530.
`IBM Technical Disclosure Bulletin, vol. 29, No. 2, Jul. 1986.
`Ghandhi, “VLSI Fabrication Principles”, 1983, pp. 479-482
`and pp. 495-497.
`Toshiyuki Nishihara et al., “A 0.5 pm Isolation Technology
`Using Advanced Poly Silicon Pad LOCOS (APPL)”, IEEE,
`1988, pp. 100-103.
`H. S. Yang et al., “Poly Void Formation in Poly Buifer
`LOCOS Process", Extended Abstracts of the Spring Elec
`trochemical Society meeting, 1992, p. 442.
`J. M. Sung, “The Impact of Poly-Removal Techniques on
`Thin Thermal Oxide Property in Poly-Bu?er LOCOS Tech
`nology” IEEE Transactions on Electron Devices, Aug. 1991,
`pp. 1970-1973.
`Stanley Wolf, “A Review of IC Isolation Technologies- '
`Part 6”, Solid State Technology, Dec. 1992, pp. 39-41.
`R. L. Guldi, “Characterization of Poly-Bulfered LOCOS in
`Manufacturing Environment”, J. Electrochem. Soc., Dec.
`1989, pp. 3815-3820.
`
`(List continued on next page.)
`
`Primary Examiner-Brian E. Hearn
`Assistant Examiner-Trung Dang
`Attorney, Agent, or Firm-Kevin D. Martin
`
`[57]
`
`ABSTRACT
`
`A process useful for isolating active areas of semiconductor
`devices in which an isolation trench is created in a substrate,
`the isolation trench being lined with an oxidation barrier and
`?lled with a thick ?lm. An oxidation step is performed in
`which the thick ?lm is oxidized. The oxidation is self
`limiting as the oxidation barrier prevents the substrate
`surrounding the trench from being oxidized.
`
`24 Claims, 3 Drawing Sheets
`
`NVIDIA Corp.
`Exhibit 1009
`Page 001
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`

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`5,472,904
`Page 2
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`OTHER PUBLICATIONS
`
`Tin-hwang Lin, “Twin-White-Ribbon Eifect and Pit For
`mation Mechanism in PBLOCOS”, J. Electrochem. Soc,
`Jul. 1991, pp. 2145-2149.
`M. Ghezzo, “LOPOS: Advanced Device Isolation for a 0.8
`
`pm CMOS/BULK Process Technology”, Journal of The
`Electrochemical Society, Jul. 1989, pp. 1992-1996.
`
`N. Shimizu et al., “A Poly-Bulfer Recessed LOCOS Process
`for 256 Mbit DRAM Cells”, IEEE, IEDM 92-279, pp.
`10.6.1—10.6.4.
`
`NVIDIA Corp.
`Exhibit 1009
`Page 002
`
`

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`US. Patent
`
`Dec. s, 1995
`
`Sheet 1 of 3
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`5,472,904
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`i\\
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`FIG. 1
`
`FIG. 2
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`NVIDIA Corp.
`Exhibit 1009
`Page 003
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`

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`US. Patent
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`Dec. 5, 1995
`
`Sheet 2 of 3
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`5,472,904
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`FIG. 4
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`NVIDIA Corp.
`Exhibit 1009
`Page 004
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`

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`US. Patent
`
`Dec. s, 1995
`
`Sheet 3 of 3
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`5,472,904
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`NVIDIA Corp.
`Exhibit 1009
`Page 005
`
`

`
`1
`THERMAL TRENCH ISOLATION
`
`2
`SUMMARY OF THE INVENTION
`
`5,472,904
`
`This invention was made with Government support
`under Contract No. MDA972-93-C-0033 awarded by
`Advanced Research Projects Agency (ARPA). The Govem
`ment has certain rights in this invention. This is a continu
`ation-in-part of application Ser. No. 08/205,663, ?led on
`Mar. 2, 1994.
`
`FIELD OF THE INVENTION
`
`This invention relates to semiconductor manufacturing,
`and more particularly to isolation schemes for integrated
`circuits.
`
`BACKGROUND OF THE INVENTION
`
`The present invention provides a method by which good
`isolation is obtained by using a nitride oxidation stop layer,
`and an amorphous silicon, polysilicon, CVD oxide, or
`silicon-rich deposited oxide for silicon dioxide formation.
`The process of the present invention uses uncomplicated
`and controllable processing steps to obtain advantages from
`the traditional LOCOS and trench isolation. For example,
`there is a severe oxide thinning eifect that limits the standard
`LOCOS process (among other dif?culties) from being scaled
`below 0.5 pm. Trench isolation processes employ CMP
`technology that address the scaling issue, but add process
`complexity and thereby increase cost.
`The process of the present invention utilizes batch type
`processes to generate “trench-like” structures in tight areas
`for superior isolation while maintaining the LOCOS-style
`isolation on the wide open ?eld regions.
`For purposes of this application: tight or narrow isolation
`areas refer to areas having a width less than 0.5 pm; and
`wide or open regions refer to regions which have a width
`greater than 0.5 pm. In actual practice, the wide regions have
`a width which is usually much greater than 0.5 pm.
`The process of the present invention oifers solutions to the
`above-stated problems relating to recessed PBL. One
`embodiment of the present invention provides a method for
`forming an isolation device in which several layers are
`formed on the surface of a semiconductor substrate. The
`layers and the substrate are then patterned and etched to a
`level below the surface of the substrate, thereby forming a
`trench-like structure or recess. A thin oxide layer is then
`grown or deposited, and a nitride layer is disposed thereon.
`A conformal ?lm is then deposited, thereby blanketing the
`structure and ?lling the trench. The conformal ?lm is etched
`back, and a ?eld oxide region is grown on the exposed
`surface of the substrate, and remaining conformal ?lm in the
`narrow ?eld regions. The pad oxide and ?rst nitride layer are
`then removed.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention will be better understood from
`reading the following description of nonlimitative embodi
`ments, with reference to the attached drawings, wherein
`below:
`FIG. 1 is a schematic cross-section of the recessed trench
`formed according to the process of the present invention;
`FIG. 2 is a schematic cross-section of the recessed trench
`of FIG. 1, after the trench re-oxidation, nitride deposition,
`and deposition of a conformal ?lm, according to the process
`of the present invention;
`FIG. 3 is a schematic cross-section of the recessed trench
`of FIG. 2, after an isotropic etch, according to the process of
`the present invention;
`FIG. 4 is a schematic cross-section of the recessed trench
`of FIG. 3, after an anisotropic etch, according to the process
`of the present invention; and
`FIG. 5 is a schematic cross-section of the recessed trench
`of FIG. 4, after ?eld oxidation, according to the process of
`the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The process of the present invention is discussed with
`reference to the LOCOS process. However, one having
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`As device dimensions decrease in size, and device density
`increases, it becomes more and more di?icult to build an
`e?icient and reliable isolation process to separate active
`devices. The limits of the standard LOCOS (LOCal Oxida
`tion of Silicon) process have motivated the search for new
`isolation schemes.
`The conventional, non-recessed, LOCOS-type process
`will not be adequate much below 0.9 pm active area-?eld
`pitch. This is the pitch which is suitable for the 16M DRAM,
`but is not suitable for the 64M DRAM generation.
`Isolation for 256 Mb and greater density DRAMS, and 64
`Mb and greater density SRAMS can not use standard
`LOCOS for isolation. Some of the problems with current
`isolation schemes are physical encroachment size, ?eld
`oxide thinning e?ect, poor electrical isolation, and processes
`which are complicated and expensive.
`One new isolation scheme is Poly Bu?’ered LOCOS
`(PBL), which employs a thin polysilicon layer between the
`oxide and nitride ?lms in the LOCOS stack.
`PBL facilitates design rule shrinking and smaller cell size
`required for subrnicron and sub-half-micron device fabrica
`tion. This isolation scheme utilizes an oxide/poly/nitride
`sandwich to block oxidation of the active regions during
`?eld oxidation growth. The presence of the intermediate
`poly layer allows the oxide to be thinned and the nitride
`thickened without generating undue stress in the active
`regions in order to reduce encroachment during the ?eld
`oxidation step.
`One PBL method is referred to as ONO PBL because an
`oxide/nitride/oxide sandwich is used between the substrate
`and the polysilicon layer. See for example, US. Pat. No.
`5,358,892, issued Oct. 25, 1994, entitled, “An Etch Stop
`Useful in Avoiding Substrate Pitting with Poly Buffered
`LOCOS,” also assigned to Micron.
`Another isolation scheme is known as recessed Poly
`Buffered LOCOS. See for example, Shirnizu, et al. “A
`55
`PolyBuffer Recessed LOCOS Process for 256 Mbit DRAM
`Cells.”
`Generally, recessed PBL processes lead to two main
`problems. The ?rst one is the formation of a sharp comer at
`the active area ?eld edge which leads to a higher leakage
`under positive bias on the gate. The second problem is the
`formation of a groove or indentation in the shape of a ring
`around the active areas. This groove can later lead to the
`generation of a stringer around the active area after etching,
`thereby causing a short. For a solution to this problem see,
`US. Pat. No. 5,393,694, entitled, “Advanced Process for
`Recessed Poly Buffered LOCOS,” also assigned to Micron.
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`NVIDIA Corp.
`Exhibit 1009
`Page 006
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`5,472,904
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`3
`ordinary skill in the art, upon being apprised of the process
`of the present invention, would be able to adapt it to other
`LOCOS-type isolation schemes without undue experimen
`tation.
`At the time in processing when the isolation stack 10 is
`ready to be formed, a layer of pad oxide 2 is preferably
`grown on a substrate 1, as shown in FIG. 1. In the LOCOS
`process, the semiconductor substrate 1, preferably bare
`silicon (Si) is used to produce a pad oxide 2. The pad oxide
`thickness, under normal conditions ranges from 100-500 A.
`The oxide layer 2 can be deposited or thermally grown.
`Stress-relief is one purpose served by the pad oxide layer 2.
`Alternatively, one may choose to employ an oxide layer
`having a thickness less than 100 A, for example in the
`approximate range of 80 A.
`An insulative layer 3, preferably a thin layer of nitride, is
`then deposited, preferably by low pressure chemical vapor
`deposition (LPCVD), at approximately 800° C. to create the
`layer 3 having a preferred thickness in the approximate
`range of 1000 A4000 A.
`Nitride is the preferred material. However, other suitable
`materials, including but not limited to tantalum pentoxide,
`indium tin oxide, and high temperature metals, may also be
`used. Nitride is preferred because nitride is a “barrier” to
`oxidation.
`In an alternative embodiment, the impervious layer 3 is
`disposed directly on the substrate 1, without the oxide layer
`2 therebetween. However, an underlying oxide layer 2 is
`preferred as it aifords some protection to the substrate 1.
`A photomask and dry etch are then used to remove the
`stack 10 on the portions of the substrate 1 where the ?eld
`oxide is to be grown. The isolation stack 10 is patterned with
`photoresist (not shown) using conventional lithography
`techniques or other suitable methods known in the art.
`In the illustrative embodiment, wide ?eld oxide areas 12
`are patterned, as well as narrow ?eld oxide regions 11.
`Narrow isolation regions refer to areas having less than 0.5
`pm in diameter; and wide areas refer to regions which are
`greater than 0.5 pm in diameter. The wide ?eld oxide areas
`12 and narrow ?eld oxide regions 11 are those portions of
`the substrate 1 on which is to be grown a thick ?eld oxide.
`Field oxide is a dielectric and functions to electrically
`isolate the active areas from each other. The narrow ?eld
`oxide regions 11 are commonly seen in memory arrays
`where high density arrangement is required. The wide ?eld
`oxide areas 12 are used in peripheral circuits where die real
`estate constraints are more relaxed.
`In the preferred embodiment, an etch step is then per
`formed in which the unpatterned areas of the stack 10 are
`etched back to the pad oxide layer 2.
`The etch is preferably an anisotropic etch which results in
`side walls which are substantially normal to the substrate
`surface 1. Preferably the etch is performed using a Clz-based
`chemistry in a reactive ion etcher (R.I.E.). However, other
`etch chemistries, such as CHF3, may also be used.
`The etch removes all the unpatterned layers of the stack
`10 down to the substrate 1, as shown in FIG. 1. A portion of
`the substrate 1 is then dry etched using a silicon etch
`chemistry, such as, for example, HBr or NF3, thereby
`creating a recess in the substrate 1. The substrate 1 is
`recessed about 200A to 3000 A.
`An oxidation step is performed whereby another thin
`oxide layer 4 is preferably grown on the bottom and side
`wall portions of the trench or recess. The oxide layer 4 is
`about 20 A-SOOA, as shown in FIG. 2. In an alternative
`
`4
`embodiment, the oxide layer 4 is deposited. The oxide layer
`4 forms on the substrate 1 wherever the substrate 1 is
`exposed. Hence, the oxide layer 4 lines the recessed trench
`portions of the substrate 1 in the wide ?eld oxide areas 12
`and the narrow ?eld oxide regions 11.
`A thin “barrier” layer of, referably, nitride 5 having an
`approximate thickness of 20 l.gPSOOA is then deposited. The
`thin nitride layer 5 is conformal in nature, and blankets the
`isolation stack 10, and also lines the trench portions of the
`wide ?eld oxide areas 12 and the narrow ?eld oxide regions
`11. In the process of the present invention, the “barrier” layer
`serves to inhibit or delay oxidation of the material on which
`it is disposed. Nitride is preferred because nitride is a
`“barrier” to oxidation.
`Next, a sacri?cial ?lm layer 6 of doped or undoped
`amorphous silicon, polysilicon, CVD oxide, or a silicon-rich
`oxide is conforrnally deposited. The ?lm layer 6 is thick
`enough to “bridge” the narrow ?eld oxide regions 11,
`thereby ?lling the trench portion of the narrow ?eld oxide
`region 11. In other words, as the layer 6 conforms to the
`trench, the layer 6 forms a “bridge” as the ?lm 6 impinges
`on itself, see dotted lines in FIG. 2. However, the wide ?eld
`oxide area 12 is only blanketed with ?lm material 6. Hence,
`the narrow ?eld oxide regions 11 are ?lled to a higher level
`than the wide ?eld oxide areas 12.
`Anisotropic etch is then used to recess the sacri?cial ?lm
`layer 6 in the narrow ?eld oxide regions 11. This etch also
`removes from the wide ?eld areas 12 essentially all of the
`sacri?cial ?lm 6, or all of the ?lm if possible. An isotropic
`etch has a vertical component and a horizontal component.
`Since layer 6 is at a higher level in the narrow ?eld oxide
`regions 11 than in the wide ?eld oxide areas 12, the layer 6
`in the wide ?eld oxide areas 12 is removed while the narrow
`?eld oxide regions 11 still contain some sacri?cial ?lm 6.
`This is illustrated in FIG. 3.
`At the end of the isotropic etch, a selective nitride etch is
`used to clear the thin nitride 5 from the wide ?eld oxide areas
`12. Since the sacri?cial ?lm 6 is still in the narrow ?eld
`oxide regions 11, the thin nitride layer 5 remains substan
`tially untouched in the narrow ?eld oxide regions 11. FIG.
`4 depicts the isolation scheme after the thin nitride layer 5
`has been removed from the wide ?eld oxide areas 12, as well
`as from the top of the isolation stacks 10.
`Subsequent to the selective nitride etch, the wafer is ready
`for thermal ?eld oxide 7, 8 growth in areas 12 and regions
`11, respectively. An oxide layer 7, 8 (also known as ?eld
`oxide) is formed over the exposed portions of the substrate
`1, for example, by oxidizing the exposed substrate 1. An
`oxide layer 7,8 having a thickness of about 1000A to 6000A
`is suf?cient, although other thicknesses also function
`adequately. The structure following a ?eld oxidation step,
`which results in an oxide layer 7, 8 having a preferred
`thickness in the approximate range of 4000 A. The oxidation
`is preferably carried out in a steam ambient.
`The amount of ?eld oxide 8 that is grown in the narrow
`?eld oxide region 11 is limited to the amount of the
`sacri?cial ?lm 6 that is left within the trench of the region
`11 after the selective nitride etch. The amount of sacri?cial
`?lm 6 in the trench of the narrow ?eld oxide region 11 is
`limited, and this ?lm 6 is contained by the thin nitride 5,
`which layer 5 acts as an oxidation barrier. Hence, once the
`sacri?cial ?lm 6 is oxidized, the process necessarily stops. It
`is, therefore, a self-limiting process.
`Since the wide ?eld oxide areas 12 provide an exposed
`silicon substrate 1, the ?eld oxidation target thickness and
`the amount of the sacri?cial ?lm 6 left in the narrow ?eld
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`NVIDIA Corp.
`Exhibit 1009
`Page 007
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`

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`5,472,904
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`5
`regions 11 can be optimized to leave little or no topography
`after the ?eld oxidation step. In other words, the oxidation
`process continues in the wide ?eld oxide areas 12, but since
`there is no more silicon being sourced in the narrow ?eld
`oxide areas 11, no more oxide 8 is grown. Hence, it is a
`self-limiting process.
`After the oxidation step, it is necessary to sequentially
`remove any oxide which may have grown on the nitride
`layer, and the nitride layer 3. This strip can be done in a dry
`plasma environment or by use of sequential wet chemical
`etchants.
`The pad oxide 2 can then be removed, in HF for about 45
`seconds, thereby exposing the isolated active area. Alterna
`tively, the pad oxide layer 2 may be left on the substrate 1.
`All of the US. Patents cited herein are hereby incorpo
`rated by reference herein as if set forth in their entirety.
`While the particular process as herein shown and dis
`closed in detail is fully capable of obtaining the objects and
`advantages herein before stated, it is to be understood that it
`is merely illustrative of the presently preferred embodiments
`of the invention and that no limitations are intended to the
`details of construction or design herein shown other than as
`described in the appended claims. For example, one having
`ordinary skill in the art will realize that although the inven
`tion was described with reference to a LOCOS stack, it is
`also applicable to other LOCOS-type isolation schemes.
`Poly-buifered LOCOS stacks and ONO PBL stacks are
`examples of the types of isolation schemes to which the
`present invention is applicable without undue experimenta
`tion.
`What is claimed is:
`1. A method for forming an isolation device comprising
`the following steps:
`providing a semiconductor substrate having a surface;
`patterning said substrate to expose wide areas and narrow
`regions of said substrate surface, said narrow regions
`having a width less than 0.5 pm;
`removing said exposed substrate to a level below said
`surface of said substrate;
`oxidizing said exposed substrate, thereby forming a thin
`oxide layer on said exposed wide areas and narrow
`regions of said substrate;
`forming a conformal ?lm;
`removing essentially all of said conformal ?lm from said
`wide areas and leaving a portion of said conformal ?lm
`in said narrow regions; and
`oxidizing said wide areas of said substrate and said
`portion of said conformal ?lm.
`2. The method according to claim 1, wherein said con
`formal ?lm comprises at least one of polysilicon, amorphous
`silicon, CVD oxide, and silicon-rich oxide.
`3. The method according to claim 2, wherein said removal
`of said conformal ?lm comprises isotropically etching said
`conformal ?lm.
`4. The method according to claim 3, further comprising
`the step of:
`depositing an oxidation barrier subjacent said confonnal
`?lm, said oxidation barrier layer comprising a thin
`nitride ?lm.
`5. The method according to claim 1, further comprising
`forming a pad oxide layer and a nitride layer prior to forming
`said conformal ?lm.
`6. The method according to claim 5, further comprising
`the following step of:
`removing said pad oxide layer and said nitride layer.
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`said
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`*****
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`6
`7. A process for isolating active areas of a semiconductor
`device, comprising the following steps:
`creating wide and narrow isolation trenches in a substrate,
`said isolation trenches being lined with an oxidation
`barrier and ?lled with a conformal ?lm, said conformal
`?lm impinging on itself in said narrow trench, said
`conformal ?lm forming a step in said wide trench;
`isotropically etching said confonnal ?lm, a portion of said
`conformal ?lm remaining in said narrow trench, essen
`tially all of said conformal ?lm being removed from
`said wide trench; and
`oxidizing said portion of said conformal ?lm remaining in
`said narrow trench.
`8. The process according to claim 7, wherein said narrow
`trench has a width less than 0.5 pm.
`9. The process according to claim 8, wherein isolation
`stacks are disposed on said substrate.
`10. The process according to claim 9, wherein said
`oxidation in said narrow trench is self-limiting.
`11. The process according to claim 10, wherein said
`conformal ?lm comprises at least one of polysilicon, amor
`phous silicon, oxide, and silicon-rich oxide.
`12. The process according to claim 11, wherein said
`conformal ?lm is deposited in said trenches, said trenches
`having a depth in the approximate range of 200 A-3000 A.
`13. The process according to claim 12, wherein an oxide
`layer is disposed subjacent said oxidation barrier.
`14. A process for fabricating a recessed ?eld oxide area,
`comprising the following steps:
`providing a substrate having isolation stacks and recesses,
`said recesses being wide and narrow, said recesses
`having openings, said recesses having a depth in the
`approximate range of 200 A-3000 A;
`lining said recesses with nitride;
`blanketing said substrate with a conformal material, said
`conformal material bridging said openings of said
`narrow recesses;
`removing said conformal material and said nitride from
`horizontal surfaces of said isolation stacks and said
`wide recesses; and
`oxidizing said substrate and said conformal material,
`thereby creating ?eld oxide regions at said wide and
`narrow recesses.
`15. The process according to claim 14, wherein said
`conformal material comprises at least one of doped silicon
`and undoped silicon.
`16. The process according to claim 14, wherein
`conformal material comprises oxide.
`17. The process according to claim 14, wherein
`conformal material comprises polysilicon.
`18. The process according to claim 14, wherein
`conformal ?lm is removed by isotropic etching.
`19. The process according to claim 18, wherein
`isolation stack comprises pad oxide and nitride.
`20. The process according to claim 19, wherein
`isolation stack further comprises polysilicon.
`21. The process of claim 1 wherein all of said conformal
`?lm is removed from said wide areas.
`22. The process of claim 7 wherein all of said conformal
`?lm is removed from said wide trench.
`23. The process of claim 14, further comprising creating
`nitride spacers during said nitride removal step.
`24. The process of claim 14 wherein all of said conformal
`material is removed from said wide recesses.
`
`said
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`said
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`said
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`said
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`NVIDIA Corp.
`Exhibit 1009
`Page 008