United States Patent [19]
`Agnello
`
`USOO5654570A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,654,570
`Aug. 5, 1997
`
`[54] CMOS GATE STACK
`
`[75] Inventor: Paul David Agnello, Wappingers Falls,
`NY.
`
`[73] Assignee: International Business Machines
`Corporation, Annonk, NY.
`
`[21] Appl. No.: 425,945
`[22] Filed:
`Apr. 19, 1995
`
`[51] Int. Cl.6 ......................... .. H01L 27/76; H01L 29/94;
`H01L 31/062; H01L 31/113
`[52] U.S. Cl. ........................................... .. 257/338; 257/369
`[58] Field of Search ................................... .. 257/204, 213,
`257/249, 250, 262, 263, 274, 288, 331,
`332, 338, 368, 369, 412
`
`[56]
`
`References Cited
`
`U.S. PATENT‘ DOCUMENTS
`
`4,545,116 10/1985 Lau ......................................... .. 29/591
`4,697,328 10/1987 Custode
`257/412
`5,057,455 l0/l99l F00 et a1.
`437/193
`5,103,272
`4/1992 Nishiyama ...... ..
`357/23.4
`5,168,332 12/1992 Kunishima et a1.
`257/385
`5,177,570
`1/1993 Tanaka .................................. .. 257/345
`
`OTHER PUBLICATIONS
`
`Basavaiah et al., Method to Fabricate Fet Devices, IBM
`Technical Disclosure Bulletin, v01. 35, No. 4A, 1992, pp.
`33-34 no month.
`
`Cronin et al., Low Sheet Resistance Gate Electrode with
`Conventional Borderless Contacts, IBM Technical Disclo
`sure Bulletin, vol. 32, No. 6B, 1989, pp. 122-123 no month.
`Miyake et al., Micro-Tribological Studies on Fluorinated
`Carbon Films, Journal of Tribology, Transactions of the
`ASME, vol. 113, 1991, pp. 386-389 no month.
`Sah et al., Mass spectrometric Study of Gas Evolution from
`Plasma-Deposited Fluorohydrogenated Amorphous Carbon
`Films on Heating, Thin Solid Films, Preparation and Char
`acterization, vol., 167, 1988, pp. 255-260 no month.
`Seth et al., Fluorohydrogenated amorphous carbon (a-CzH,
`F) ?lms prepared by the r.f. plasma decomposition of
`1,3-butadiene and carbon tetra?uon'de, Thin Solid Films,
`vol. 230, 1993, pp. 90-94 no month.
`Grill et al., Temperature and Bias Effects on the Physical and
`Tribological Properties of Diamond-Like Carbon, J. Elec
`trochem. Soc., vol. 138, No. 8, 1991, pp. 2362-2367 no
`month.
`
`Primary Examiner-Carl W. Whitehead
`Attorney, Agent, or Firm-—Pol1ock, Vande Sande & Priddy
`[57]
`ABSTRACT
`
`A gate structure in a CMOS is fabricated wherein the
`encapsulation material is self-aligned with the gate conduc
`tor and the gate channel. The gate conductor is formed
`subsequent to the device doping and heat cycles for formu
`lation of the source and drain junction, and is preferably of
`greater width than the gate.
`
`4 Claims, 6 Drawing Sheets
`
`E
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`I6
`
`NVIDIA Corp.
`Exhibit 1008
`Page 001
`
`

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`US. Patent
`
`Aug. 5, 1997
`
`Sheet 1 of 6
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`5,654,570
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`(
`
`I
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`
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`DIELECTRIC
`
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`I/GATE OXIDE
`SUBSTRATE
`FIG. lPRIOR ART
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`DIFFUSION I
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`NVIDIA Corp.
`Exhibit 1008
`Page 002
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`

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`US. Patent
`
`Aug. 5, 1997
`
`Sheet 2 0f 6
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`5,654,570
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`NVIDIA Corp.
`Exhibit 1008
`Page 003
`
`

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`US. Patent
`
`Aug. 5, 1997
`
`Sheet 3 0f 6
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`5,654,570
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`NVIDIA Corp.
`Exhibit 1008
`Page 004
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`

`

`US. Patent
`
`Aug. 5, 1997
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`Sheet 4 0f 6
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`5,654,570
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`H65
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`ml
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`NVIDIA Corp.
`Exhibit 1008
`Page 005
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`

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`US. Patent
`
`Aug. 5, 1997
`
`Sheet 5 0f 6
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`5,654,570
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`NVIDIA Corp.
`Exhibit 1008
`Page 006
`
`

`

`US. Patent
`
`Aug. 5, 1997
`
`Sheet 6 0f 6
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`5,654,570
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`FIG.8
`
`NVIDIA Corp.
`Exhibit 1008
`Page 007
`
`

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`5,654,570
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`1
`'CM 05 GATE STACK
`
`DESCRIPTION
`
`TECHNICAL FIELD
`
`2
`sidewall, and to repair gate oxide damage. Metals such as
`tungsten and diffusion barriers such as titanium nitride or
`tantalum nitride oxidize very readily. Furthermore, wet
`cleans such as sulphuric acid-peroxide compositions or
`HuangB, acid-peroxide compositions, water-peroxide
`hydrochloric acid or water-peroxide-amonium hydroxide
`compositions, are often used after gate reactive ion etching,
`in order to remove residue from the reactive ion etching.
`However, many of the conductors employed are etched by
`such solutions.
`Another disadvantage is that the patterned gate must
`withstand the thermal cycles that are used to drive and
`activate the dopants for the source/drain junctions. Even for
`Very shallow functions, these thermal cycles can be signi?
`cant (e.g., about 900° C. for about 5 minutes or about 1000°
`C. for about 5 seconds). Materials such as titanium silicide
`or cobalt silicide are not stable on polycrystalline silicon for
`these thermal cycles and therefore, require a diffusion bar
`rier. However, the common diffusion barrier materials such
`as TiW, TiN and TiB are easily oxidized and readily attacked
`by the wet etchants. On the other hand, materials such as
`tungsten are chemically resistant but oxidize much too
`easily. Materials such as WSi2 are more stable, but exhibit
`higher resistivity and therefore are not an option for deep
`submicron lines where sheet resistances of less than 10
`ohm/square are required. Finally, in these situations, the
`polysilicide conductor line width is limited to be less than or
`equal to the gate length. Therefore, as device dimensions are
`scaled down, extremely high aspect ratios cannot be avoided
`if resistance targets remain relatively constant.
`SUMMARY OF INVENTION
`The present invention provides a method that overcomes
`above discussed de?ciencies of the prior art. In particular,
`the method of the present invention provides a self-aligned
`capped conductor suitable for borderless contacts and which
`may be placed on the gate after all front end processing is
`completed. Accordingly, the self-aligned capped conductor
`need only withstand the much lower heat cycles and less
`harsh conditions experienced in the subsequent processing.
`According to the present invention, the conductor is placed
`on the gate in a self-aligned fashion so that no critical
`overlap steps are required. Moreover, the conductor contains
`a dielectric cap that allows the implementation of borderless
`contacting. A further advantage of the present invention is
`[that the gate conductor can be fabricated so that its width is
`greater than the width of the gate polycrystalline silicon.
`This in turn eliminates conventional scaling limitations.
`More particularly, the present invention is concerned with
`a process for fabricating a gate structure in a CMOS device.
`The process comprises forming device insulation regions in
`a semi-conductor substrate. Next, an N-type well region and
`a P-type well region is formed in the semi-conductor sub
`strate. This is achieved by ion implantation or diifusion. A
`gate insulation layer is then formed over active regions of
`the substrate as de?ned by the previously formed device
`isolation regions. A gate forming layer is provided above the
`gate isolation layer, and a sacri?cial gate cap is deposited
`over the gate forming layer. The gate forming layer is doped
`either before the sacri?cial gate cap material is deposited or
`after it is removed later in the process. The sacri?cial gate
`cap layer is etchable at a faster rate than the surrounding
`dielectric material to be subsequently formed. The sacri?cial
`gate cap and gate forming layer are etched to thereby de?ne
`individual gate channel regions. The source and drain
`regions are next formed by ion implantation or diffusion. A
`sacri?cial spacer layer is formed on the vertical sides of the
`
`The present invention is concerned with fabricating a gate
`structure in a CMOS device, and is especially concerned
`with providing a self-aligned insulator on the gate conduc
`tor. More particularly, the present invention is concerned
`with a fabrication process whereby the gate conductor is not
`in place on the gate channel de?ning polysilicon until after
`the device doping and heat cycles required for formation of
`source and drain junctions are completed In addition, the
`present invention is concerned with a CMOS gate stack that
`contain a metallic gate conductor above a polysilicon gate,
`wherein the metallic gate conductor is wider than the
`polysilicon gate.
`
`15
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`BACKGROUND OF INVENTION
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`Metallic silicides have been used as an interconnection
`material in integrated circuits in order to overcome certain
`inherent disadvantages of polycrystalline silicon. The pri
`mary disadvantage of such is its minimum sheet resistivity
`that is about 10 ohms/square. Various metallic silicides have
`been used on the polycrystalline silicon because of the
`reduced sheet resistance, in order to improve the perfor
`mance of large scale integrated circuits. The metallic sili
`cides permit the scaling down of interconnect and gate line
`widths that is required to achieve very large scale integra
`tion. However, the conventional method of forming silicides
`on the surfaces of a polycrystalline silicon gate referred to as
`“Salicide” processing does not result in a self-aligned insu
`lator on the gate conductor. Accordingly, such is not readily
`suitable for borderless contacts that are used in high density
`ULSI. On the other, polycide gate conductors, while incor
`porating the insulating cap for borderless contacts, are
`extremely di?icult to fabricate. In particular, the conductor
`is put in place early in the fabrication sequence and
`therefore, must withstand oxidation, wet chemical cleaning
`and high thermal cycles.
`Reference to FIG. 1 illustrate the typical starting stack in
`the prior art for the polycide gate process. In particular, after
`gate oxidation and poly deposition, a refractory metal or
`metal silicide (such as W, WSI2 or TiSi?) is deposited and
`45
`capped with a dielectric such as silicon nitride (Si3N4). A
`diffusion barrier is sometimes employed between the gate
`conductor and the polysilicon to prevent interaction and
`transport of dopants.
`The gate is then de?ned by photolithography and reactive
`ion etching and a dielectric sidewall is then formed by
`chemical vapor deposition followed by reactive ion etching.
`The resulting structure in the prior art is illustrated in FIG.
`2.
`FIG. 3 illustrates the contact of the substrate material with
`overlap to gate permitted (for increased density) with such
`a gate structure. The capping material and ?eld dielectrics
`are selected such that the contact etch will not etch through
`the gate cap when su?icient etching is done to contact the
`substrate.
`The problems encountered when fabricating such struc
`tures are numerous. First of all, the multiple layer structure
`as illustrated in FIG. 1 is extremely difficult to reactive ion
`etch without undercutting and/or line with bias due to the
`dissimilar materials present. In addition, after the reactive
`ion etching of the gate, a sidewall oxidation step is typically
`required, both to act as a pad oxide for a subsequent nitride
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`Exhibit 1008
`Page 008
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`5,654,570
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`3
`sacri?cial gate cap and gate. Next. the process involves
`blanket depositing interlayer dielectric material to a depth
`that is at least equal to the gate stack height and planarizing
`the interlayer dielectric. This interlayer dielectric is etchable
`at a rate that is slower than that of the sacri?cial gate cap.
`The sacri?cial gate cap is removed and a self-aligned
`metallic gate conductor is then deposited above the poly
`crystalline silicon gate. The gate conductor is selectively
`etched to form a trench and a cap dielectric is blanket
`deposited and thereby self—aligned on the gate conductor.
`The gate dielectric is etchable at a rate that is slower than
`that of the interlayer dielectric.
`The present invention is also concerned with a CMOS
`gate stack that comprises a semi-conductor substrate and
`device isolation regions in said substrate. A gate isolation
`layer is located over active regions of the substrate as
`de?ned by the device isolation regions. A polysilicon gate is
`located above the gate isolation layer and a self-aligned
`metallic gate conductor is located above the polysilicon
`gate. The metallic gate connector is wider than the polysili
`con gate. A self-aligned cap dielectric is provided on the gate
`conductor.
`
`10
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`15
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`4
`about 800° to 900° C. in the presence of dry oxygen. or at
`about 750° to 850° C. in the presence of oxygen mixed with
`steam.
`A layer of polycrystalline silicon 9 is then deposited. This
`polycrystalline silicon layer 9 is typically about 500 to about
`3500 angstroms thick. and may be formed by chemical
`vapor deposition. The polycrystalline silicon layer 9 can be
`doped by ion implantation or some other means. For
`instance. such is typically doped with both N-type and
`P-type dopants in different regions of the wafers through the
`use of photolithographic masking and ion implantation. The
`wafers could then be annealed at this stage of the process. if
`desired This decoupling of the gate anneal from the source/
`drain anneal can result in improved gate activation without
`resulting in deeper source/drain junctions. However. gate
`RIE becomes more dif?cult when the gate dopant is
`activated. thus depending on the gate etching process. one
`may choose to leave the dopants un-annealed at this step.
`Doping via POCl3 or by insitu doping during poly deposi
`tion is also possible. though less attractive because it
`becomes di?icult to obtain both dopant polarities by this
`means.
`A sacri?cial gate cap layer 17 is deposited over the
`polycrystalline silicon layer 9. This gate cap material is
`preferably a dielectric materials but does not need to be so.
`since it will be subsequently removed in the process.
`However. the material must be selected such that it is
`etchable at a rate that is faster than the rate for surrounding
`dielectric material that will be subsequently formed on the
`structure.
`In the case where the interlayer dielectric material 16
`(hereinafter referred to as lLD) is chosen to be SiO2 or SiO2
`doped with F. P or B or a combination of the above. a
`preferred sacri?cial gate cap material is Si3N4. Other suit
`able materials include. but as those skilled in the art will
`realize, are not limited to BN. SiOBN and SiBN. The
`sacri?cial dielectric is chosen for its ease of removal relative
`to the ILD to be deposited later. It is necessary that this
`material be capable of withstanding the subsequent gate
`source/drain thermal cycle. It must be selectively etchable so
`that the gate material and interlayer dielectric is not removed
`during its removal.
`A different sacri?cial dielectric would be chosen for a
`di?erent class of ILD. for example, organic materials. If low
`dielectric constant polyamide or other organic materials,
`such as Te?on are chosen as ILD, then the sacri?cial
`dielectric material could include those listed above and in
`addition could include SiO2 based materials.
`Considering the case of a SiO2 based ILD in more detail.
`the material for the gate cap dielectric is preferably Si3N4
`and is typically about 2000 to 4000 angstroms thick, and
`preferably about 2700 to 3300 angstroms thick.
`The sacri?cial gate cap 17 and polycrystalline silicon gate
`layer 9 are then delineated by employing conventional
`photolithographic patterning techniques followed reactive
`ion etching. as the preferred method of etching (see FIG. 6).
`Ifdesired. the sacri?cial gate cap 17 can be protected against
`any undue line width growth during the reactive ion etching
`by coating on top of it a relatively hard masln'ng layer, such
`as a layer of polycrystalline silicon (not shown).
`The reactive ion etching typically employs a chemically
`reactive gas mixture containing CHF3 and O2 to each the
`dielectric. This process is typically carded out at a power of
`several hundred watts and a pressure of 50 mTorr. An
`emission endpoint. such as disclosed by L. Chen. US Pat.
`No. 4,493 .745, disclosure of which is incorporated herein by
`
`SUMMARY OF DRAWING
`
`FIGS. 1-3 are schematic illustrations of prior art struc
`tures.
`FIG. 4 is a schematic illustration of a CMOS gate struc
`ture pursuant to the present invention.
`FIGS. 5-8 are schematic illustrations of a gate structure
`pursuant to the present invention in various stages of its
`fabrication.
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`BEST AND VARIOUS .MODES FOR CARRYING
`OUT INVENTION
`
`35
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`Reference to FIG. 5 illustrates a semi-conductor substrate
`such as a silicon substrate 30 having any desired crystal
`orientation (e.g., <100>). which can be prepared by slicing
`and polishing a silicon boule, followed by conventional
`crystal gowth techniques.
`Device isolation regions 1 are formed in the semi
`conductor substrate by well known techniques, such as
`thermal oxidation of the semi-conductor substrate in
`selected regions or by a shallow trench isolation technique.
`Typically. the device isolation regions one are about 2000 to
`about 6000 angstroms thick.
`Next. the formation of twin wells are formed by ion
`implantation or diffusion. In particular. an N-type well 2 is
`formed by ion implantation or di?’usion of an N-type dopant,
`which for silicon can be phosphorous, the N-type dopant is
`typically formed by ion implantation or diffusion to a depth
`of about 8000 to about 12000 angstroms in the substrate,
`employing an energy level of about 400 to about 800 KeV
`and a dosage of about l><1012 to about l><lO13 atomslcmz.
`Other N-type dopants include arsenic and antimony. 'Ihe
`P-type dopant for silicon for the P-type well 3 includes
`boron, aluminum. gallium and indium. Such can be provided
`at a depth of about 10000 angstroms employing boron at an
`energy of about 70 to 150 KeV and dosage of about 1x1012
`to about 1><1013 atoms/cm2'
`Next. a gate isolation layer 8 such as silicon dioxide is
`deposited or grown over the active regions of the substrate
`as de?ned by device isolation regions one. This gate
`insulator. which is typically about 30 to about 120 angstroms
`thick. is preferably of silicon dioxide and can be formed by
`thermal oxidation of the silicon substrate, for instance. at
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`Exhibit 1008
`Page 009
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`reference. could be used to detect SiN species in the plasma
`and terminate the etch when the polysilicon is reached and
`the SiN signal is reduced. Other suitable gas chemistries for
`etching the dielectric may include replacing CHF3 with NF3
`or other compounds containing F.
`Following etching of the dielectric cap material, the
`polysilicon is etched. The polysilicon etch can be carried out
`in a chemistry of HCl, He and 02 at a pressure of less than
`20 mTorr and a power in the range of 100 to 200 Watts. In
`this case, the Cl signal is monitored for emission endpoint on
`the gate oxide. Alternatively, if the resist can be stripped
`after the dielectric cap is removed, then a HBr gas chemistry
`at a power of 100 to 200 watts and a pressure of less than 10
`mTorr can be used. In either case, it is preferred that the two
`etching steps be carried out in a clustered tool (multiple
`process chambers attached to a common high vacuum
`central handler) so that the poly surface is not exposed to
`atmosphere before it is etched. This allows for etch chem
`istries that etch SiO2 very slowly (such as disclosed above)
`to be utilized.
`This procedure de?nes the individual CMOS channels as
`illustrated in FIG. 6.
`Convention chemical cleaning to remove reactive ion
`etching residue and oxidation to form a reoxidizing layer 10,
`25
`can be carried out. Chemical cleaning can include dilute HF
`etching and etching in sulphuric/peroxide or other acidic or
`basic peroxide mixtures.
`The N-type FEI‘ and p-type FEI source and drain regions
`4 and 6 are formed by ion implantation and annealing or
`conventional thermal diffusion processing (see FIG. 7). This
`doping can be carried out employing a p-type dopant, such
`as boron, aluminum, gallium and indium at a dosage of
`about l><1015 to about 5><1015 atomslcmz, using an ion
`implantation energy of about ‘10 KeV of boron for the
`p-FEI‘. For the N-type FE'I‘, a dopant such as phosphorous,
`arsenic or antimony at a dosage of about 3X1015 atoms/cm2
`of As employing an ion implantation energy of about 25
`KeV can be used. The annealing to typically carried out at
`temperatures of about 950° to about 1100° C., and more
`typically at about 1000° to about 1050° C.
`Next, gate sidewall spacers 18, can be provided by
`chemical vapor deposition following by reactive ion etching.
`The sidewalls are typically about 500 to about 2000 ang
`stroms thick. The choice of sidewall spacer material is
`subject to the same considerations as that of the gate cap,
`described earlier, if the spacers are to be sacri?cial. One
`embodiment, described later, does not require that the spac
`ers be sacri?cial. However, this is the least preferred
`embodiment, because the resulting gate conductor will be
`narrower than the gate itself. The reactive ion etching
`employed can be by the technique disclosed in U.S. Pat. No.
`4,283,249 to Ephrath, disclosure of which is incorporated
`herein by reference, or by derivatives of this technique
`which employ a gas mixture of CHF3 (or other ?uro
`hydrocarbon) and 02 (or other oxygen containing species
`such as CO) at a power of several hundred watts. Emission
`endpoint based on the SiN line emitted from the plasma
`during etch is usually used to determine when the etch has
`completed etching the Si3N4. Such reactive ion etching
`selectively etches the nitride at a much greater rate than that
`of the substrate. The gate sidewall spacers provide for
`source/drain extensions, halos or lightly doped drains
`(hereinafter LDD). If desired, after LDD halos or source/
`drain extension processing, an additional spacer can be
`formed following similar processing to the ?rst spacer as
`detailed above. This spacer formation is typically carried out
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`only if additional spacer width, over that which may already
`be present due to the gate sidewall spacer, is desired. For
`practical purposes. the widest total spacer width is approxi
`mately 1/2 the height of the gate stack, including the sacri
`?cial gate cap 17. The width of the gate plus the spacers will
`ultimately determine the width of the gate conductor to be
`subsequently provided The wider the spacer, the better.
`However, such is limited to provide su?icient source and
`drain contact areas. FIG. 8 illustrates the widest practical
`gate stack.
`Next, interlayer dielectric 16 is blanketed deposited over
`the entire wafer. The depth of the dielectric layer 16 is at
`least equal to and can be greater than the gate stack height.
`The interlayer dielectric material is selected such that it can
`be planarized to the top of the gate stack by chemical/
`mechanical polishing or any other known technique. Such
`must be etchable at a rate slower than that of the sacri?cial
`gate cap and sacri?cial spacer material. An example of such
`is a TEOS based oxide is an oxide deposited from tetra
`ethylorthosilicate (hereinafter referred to as TEOS) in a
`mixture with O3 (Ozone) at a temperature of approximately -
`400° C. when employing as the sacri?cial dielectric silicon
`nitride. Other suitable materials include TEOS/Ozone based
`oxides doped with phosphorous, boron or ?ourine or a
`combination of the above or ?owable or spin on oxides. The
`second class of ILDs includes polyamides and other ?uro
`hydrocarbon materials which can be deposited by spin on
`techniques or by chemical vapor deposition. This class of
`materials allows the use of SiO2 based materials as the
`sacri?cial dielectric layers as described previously.
`To prevent dishing of the interlayer dielectric 16, dummy
`gate shapes may be placed in the ?eld as is common practice.
`This technique involves patterning additional gate shapes,
`during the gate de?nition stage of the process, that are
`situated over isolation regions 1, of the wafer. As such, they
`have no electrical purpose in the ULSI circuit, but instead
`provide a uniform pattern factor of gate shapes distributed
`over the chip to enable more uniform planarization of the
`ILD. The planarization also may result in some removal of
`the sacri?cial cap material and sacri?cial sidewall isolation.
`Next, the sacri?cial gate cap 17 is removed. Along with its
`removal, the sacri?cial sidewalls can be completely or
`partially removed or can be left intact. The removal of the
`sacri?cial gate cap is carried out selectively, with respect to
`the interlayer dielectric, the gate polycrystalline silicon, and
`in one particular instance, with respect to the source and
`drain material. Removal of the sacri?cial gate cap can be
`achieved by dry etching, such as reactive ion etching or by
`wet etching. A particular preferred removal process is reac
`tive ion etching in any of the nitride etch chemistries
`disclosed earlier for spacer formation. These chemistries
`have moderate selectivity to Si and SiO2. Improved selec
`tivity can be obtained by etching in a Cl2/O2 gas mixture as
`disclosed in U.S. Pat. No. 4,832,787 to J. A. Bondur,
`disclosure of which is incorporated herein by reference. This
`particular etch process has very high etch rate ratios of Si3N4
`with respect to SiO2, but will not stop on Si. If this chemistry
`is to be used, a thin (approximately 100 A) layer of SiO2
`layer should ?rst have been deposited between the gate
`forming layer 9, and the sacri?cial dielectric 17. It will
`provide a good stopping layer for the Si3N4 etch and can be
`removed via a wet etch in dilute HP or by dry etching
`processes.
`In the least preferred embodiment of the present
`invention, the sacri?cial gate cap material only is removed
`and the sidewall spacers are left intact. In this situation, the
`sidewall spacer material must be selected so that such is not
`
`NVIDIA Corp.
`Exhibit 1008
`Page 010
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`8
`The gate conductor 13. such as titanium tantalum. alumi
`num or any other suitable metal. such as tungsten, copper,
`titanium. and aluminium, is deposited and subsequently
`planarized. The deposition can be by any conventional
`method, such as chemical vapor deposition, sputter
`deposition, evaporation or plating. In addition, the deposi
`tion can be blanket deposition or selective deposition. One
`preferred method for depositing W is by CVD by silane and
`hydrogen reduction of WFG at a temperature of around 400°
`C. To prevent reaction of the volatile ?uoride species with
`the underlying Poly Si and Si a sputtered Ti/I‘iN barrier layer
`of several hundred angstroms thickness may be deposited
`?rst. The planarization can be achieved by reactive ion
`etching etchback or by chemical/mechanical polishing or
`any other known technique. CMP typically involves polish
`ing the W surface with an acidic slurry containing nm sized
`abrasive particles such as alumina.
`
`Next, the conductor is selectively recessed so as to form
`a trench into which a gate cap dielectric can be subsequently
`and planarized. Preferably, the recess is to a depth approxi
`mately equal to the desired cap dielectric thickness. For
`instance. when employing W, this can be carried with a high
`degree of selectivity to oxide and nitride using a SP6 oxygen
`gas mixture at a power of 400 Watts and a pressure of about
`100 mTorr.
`'
`
`In the next step. a layer of cap dielectric 14 is blanket
`deposited. Preferably. the thickness of the cap dielectric is
`about 1 to 1 1/2 times the depth of the recess. A suitable cap
`dielectric is silicon nitride. Such is then subjected to a
`chemical/mechanical polishing in order to formed the
`desired cap.
`
`15
`
`20
`
`25
`
`35
`
`7
`sacri?cial. One such material is SiO2. In this arrangement,
`the selective etch of the sacri?cial gate cap material is
`selective to the polycrystalline silicon gate and interlayer
`dielectric and automatically stops on top of the gate poly
`crystalline silicon. This embodiment is the least preferred
`since it provides a gate conductor that is of lesser or equal
`width to the gate polycrystalline.
`In an alternative embodiment, the sacri?cial gate cap layer
`is completely removed. While the sidewall spacers are only
`partially etched. In this embodiment. the sidewall spacers
`are sacri?cial and would be of a material that is similar to the
`sacri?cial gate type material. such as silicon nitride or other
`materials that can be etched selectively to SiO2 and Poly Si
`as discussed previously. To carry out this embodiment. the
`selective etch (selective to the polycrystalline silicon and
`interlayer dielectric) is a timed or emission endpointed etch
`with an over etch to assure that the top of the polycrystalline
`is uncovered, but is limited to assure that the source/drain
`regions are not exposed. This embodiment achieves the
`maximum width gate conductor.
`In a still further embodiment, both the sacri?cial gate cap
`and sidewall spacers are completely removed. In this
`embodiment, the sidewall spacers are sacri?cial and would
`be a material similar to the sacri?cial gate cap material. In
`this situation, the selective etch (selective to the polycrys
`talline silicon, source/drain regions and interlayer dielectric)
`stops on top of the polycrystalline silicon and the source and
`drain regions. When employing this alternative
`embodiment. the gate conductor liner to the subsequently
`deposited. must be deposited at a thickness which is at least
`about one-half the thickness of the space between the gate
`polycrystalline silicon sidewall and the interlayer dielectric,
`in order to protect the exposed source and drain regions from
`the gate conductor to be deposited subsequently. This
`embodiment makes it possible to provide a gate conductor to
`be wider than the gate conductor by twice the liner thick
`ness.
`In the latter two embodiments as discussed above, con
`ductor liner sidewall deposition and reactive ion etching
`formation is carried out subsequent to the removal of the
`sacri?cial gate cap and spacer. Suitable materials for the
`conductor liner sidewall include silicon nitride. Other suit
`able materials are silicon dioxide, boron nitride or other
`dielectric materials that can be deposited conformal and
`etched to form a spacer. If the spacer material is Si3N4, the
`spacer RIE process to be used could be the same as used to
`form the sacri?cial spacer described earlier.
`If desired, the gate polycrystalline silicon can be doped at
`this stage of the process rather than the previous doping
`discussed above. If doped at this stage, then such would also
`be annealed. The annealing is carried at temperatures of
`about 900° to about 1100° C. for about 5 to 60 seconds and
`is controlled so as to minimize dopant penetration through
`the gate oxide. This is bene?cial since it reduces the possi
`bility of dopant motion through the gate oxide into the
`channel region of the device, which in turn could cause
`uncontrolled device behavior.
`
`Next. an additional interlayer dielectric 18 is then
`deposited, which if desired. can be planarized.
`Following the above sequence results in the CMOS gate
`stack of the present invention.
`What is claimed is:
`1. A CMOS gate stack comprising a semiconductor sub
`strate;
`
`device isolation regions on or in said substrate or both on
`and in said substrate;
`gate isolation layer over active regions of said substrate as
`de?ned by said device isolation regions;
`polysilicon gate located above said gate isolation layer;
`self-aligned metallic gate conductor above said polysili
`con gate wherein said metallic gate conductor is wider
`than said polysilicon gate.
`2. The gate stack of claim 1 wherein said substrate is
`silicon.
`3. The gate stack of claim 1 wherein said device isolation
`regions is silicon dioxide.
`4. The gate stack of claim 1 which further comprises a cap
`dielectric.
`
`45
`
`50
`
`55
`
`NVIDIA Corp.
`Exhibit 1008
`Page 011
`
`