United States Patent [191
`Dennison
`
`llllllllllllllllllllllIlllllllllllllllllllllllllllllIllllllllllllllllllllll
`US005292677A
`Patent Number:
`5,292,677
`[11]
`Mar. 8, 1994
`[45] Date of Patent:
`
`[54] REDUCED MASK CMOS PROCESS FOR
`FABRICATING STACKED CAPACITOR
`MULTI-MEGABIT DYNAMIC RANDOM
`ACCESS MEMORIES UTILIZING SINGLE
`ETCI-I STOP LAYER FOR CONTACTS
`[75] Inventor:
`Charles H. Dennison, Boise, Id.
`Assignee:
`Micron Technology, Inc., Boise, Id.
`[73]
`[21]
`Appl. No.: 947,523
`Filed:
`Sep. 18, 1992
`[22]
`[51]
`[52]
`
`Int. Cl.5 . . . . . .
`
`. . . . . . . . . .. H01L 21/70
`
`US. Cl. ...................................... .. 437/52; 437/47;
`437/48; 437/60; 437/919
`Field of Search ..................... .. 437/47, 48, 52, 60,
`437/919, 235, 238; 257/308, 306
`References Cited
`U.S. PATENT DOCUMENTS
`
`[53]
`
`[56]
`
`5,087,591 2/1992 Teng ................................. .. 437/238
`5,118,382 6/1992 Cronin et al. ..................... .. 437/238
`
`OTHER PUBLICATIONS
`Kawamoto et al., “A 1.28pm2 Bit-Line Shielded Mem
`ory Cell Technology for 64Mb DRAMS”, Symposium
`on VLSI Technology, 1990, pp. 13-14.
`Itoh et al., “Two Step Deposited Rugged Surface
`(TDRS) Storagenode and Self Aligned Bitline-Contact
`Penetrating Cellplate (SABPEC) for 64 MbDRAM
`STC Cell” IEEE Symposium on VLSI Technology,
`1991, pp. 9-10.
`Shibata et al., “A Novel Zero-Overlap/Enclosure
`
`(92
`
`90
`
`Metal Interconnection Technology for High Density
`Logic VLSI‘s”, IEEE VMIC Conference, 1990, pp.
`15-21.
`
`Primary Examiner-Tom Thomas
`Attorney, Agent, or Firm—-Dorr, Carson, Sloan &
`Peterson
`
`ABSTRACT
`[57]
`An etch stop layer is deposited on a DRAM wafer after
`formation of the PMOS and NMOS transistors and
`A.A’s. After deposition of oxide 1, a ?rst mask and etch
`process is used to form the capacitor container and
`remove the oxide 1 and etch stop at the future poly 1
`and cell poly contacts. After deposition of the capaci
`tor, a second mask and etch removes the capacitor
`layers at the future poly 1 contact. After deposition of
`oxide 2 and a poly etch stop layer, a third mask and etch
`process forms the bit line contact region through the
`cell poly, and the poly 1 and cell poly contact region.
`The etch is made through the cell poly at the bit line
`contact and a thin oxide is deposited and etched to form
`cell poly spacers that don’t close off the active area. An
`oxide etch goes to the etch stop layer at the bit contact
`region, to the poly 1 at the future poly 1 contact, and to
`the cell poly at the future cell poly contact. After etch
`of the etch stop at the future bit line contact, the
`contacts are formed.
`
`18 Claims, 15 Drawing Sheets
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`U.S. Patent
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`Mar. 8, 1994
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`Exhibit 1007
`Page 016
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`

`
`1
`
`REDUCED MASK CMOS PROCESS FOR
`FABRICATING STACKED CAPACITOR
`MULTI-MEGABIT DYNAMIC RANDOM ACCESS
`MEMORIES UTILIZING SINGLE ETCH STOP
`LAYER FOR CONTACTS
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The invention in general relates to the structure and
`fabrication of integrated circuits and more particularly
`to a process for fabrication of a stacked capacitor
`DRAM.
`2. Statement of the Problem
`As is well-known, integrated circuits, sometimes
`called semiconductor devices, are generally mass pro
`duced by fabricating hundreds of identical circuit pat
`terns on a single semiconducting wafer, which wafer is
`subsequently sawed into hundreds of identical dies or
`chips. While integrated circuits are commonly referred
`to as “semiconductor devices” they are in fact fabri
`cated from various materials which are either electri
`cally conductive, electrically nonconductive, or electri
`cally semiconductive. Silicon, the most commonly used
`semiconductor material, can be used in either the single
`crystal or polycrystalline form. In the integrated circuit
`fabrication art, 0 polycrystalline silicon is usually called
`“polysilicon” or simply “poly”, and shall be referred to
`as such herein. Both forms of silicon may be made con
`ductive by adding impurities to it, which is commonly
`referred to as “doping”. If the doping is with an element
`such as boron which has one less valence electron than
`silicon, electron “holes” become the dominant charge
`carrier and the doped silicon is referred to as P-type
`silicon. If the doping is with an element such as phos
`phorus which has one more valence electron than sili
`con, additional electrons become the dominant charge
`carriers and the doped silicon is referred to as N-type
`silicon.
`CMOS (Complimentary Metal Oxide Semiconduc
`tor) technology is currently the most commonly used
`integrated circuit technology, and thus the present in
`vention will be described in terms of silicon-based
`CMOS technology, although it is evident that it may
`find uses in other integrated circuit technologies. The
`45
`term CMOS is now loosely applied to mean any inte
`grated circuit in which both N-channel and P-channel
`MOSFETs (Metal-Oxide-Semiconductor Field Effect
`Transistors) are used in a complimentary fashion. It
`should be noted here that because the dominant carrier
`in a MOSFET occurs in an inversion layer, the channel
`of an N-channel MOSFET is actually doped P-type and
`the channel of a P-channel MOSFET is actually doped
`N-type. CMOS integrated circuit 0 fabrication may
`begin with a lightly-doped P-type silicon substrate, a
`lightly-doped N-type silicon substrate, or lightly-doped
`epitaxial silicon (deposited crystalline silicon) on a
`heavily doped substrate. For the sake of simplicity, the
`invention will be described using lightly-doped P-type
`silicon as the starting material, although it may be im
`plemented with other materials as the starting point. If
`other materials are used as the starting point, there may
`be differences in materials and structure as is well
`known in the art, e.g. with N-type silicon as the starting
`point dopant types may be reversed, or P-type wells
`may be introduced.
`One well-know integrated fabrication process is the
`photo-mask and etch process which comprises: creating
`
`5,292,677
`2
`a photolithographic mask containing the pattern of the
`parts to be fabricated, coating the integrated circuit
`wafer with a light-sensitive material called photoresist
`or resist, exposing the resist-coated wafer to ultraviolet
`light through the mask to soften or harden parts of the
`resist depending on whether positive or negative resist
`is used, removing the softened parts of the‘ resist, etch
`ing the wafer to remove the part unprotected by the
`resist, and stripping the remaining resist. Etching which
`forms part of the photo-mask and etch process is itself a
`highly developed process which is used in many in
`stances besides in conjunction with the photo-mask. It is
`well-know that etches can be made that etch one mate
`rial relatively rapidly while etching another material
`hardly at all. When an etch does not etch a material it is
`said to be “selective” to that material. That is, it selec
`tively leaves that material while etching away other
`materials.
`Most current-generation DRAM (Dynamic Random
`Access Memory) manufactures utilize CMOS technol
`ogy. DRAM circuits comprise arrays of memory cells,
`each cell comprising two main components: a field
`effect transistor and a capacitor. In the most common
`circuit designs, one side of the transistor is connected to
`one side of the capacitor, the other side of the transistor
`and the transistor gate are connected to external con
`nection lines called the bit line and word line, respec
`tively, and the other side of the capacitor is connected
`to a reference voltage that is typically 5 the internal
`circuit voltage. Thus the fabrication of the Dram cell
`essentially comprises the fabrication of a transistor, a
`capacitor, and three contacts to external circuits.
`The advantages of building integrated circuits with
`smaller individual circuit elements so that more and
`more circuitry may be packed on a single chip are well
`known: electronic equipment becomes less bulky, reli
`ability is improved by reducing the number of solder or
`plug connections, assembly and packaging costs are
`minimized, and improved circuit performance, in par
`ticular higher clock speeds. The requirements of hold
`ing a charge large enough to be sensed for a long
`enough time for practical memory applications result in
`the capacitor being the largest of the circuit parts. Thus,
`the drive to produce smaller DRAM circuits has give
`risen to much capacitor development, which can be
`classi?ed into three basic capacitor types: planar capaci
`tors, trench capacitors and stacked capacitors. For rea
`sons of available capacitance, reliability, and ease of
`fabrication, most manufacturers of DRAMS of 4
`Megabit and larger capacity utilize stacked capacitor
`designs in which the capacitor covers nearly the entire
`area of a cell and in which vertical portions of the ca
`pacitor contribute significantly to the total charge stor
`ing capacity. In such designs the side of the capacitor
`connected to the transistor is generally called the “stor
`age node” or “storage poly” since the material out of
`which it is formed is doped polysilicon, while the
`polysilicon layer defining the side of the capacitor con
`nected to the reference voltage mentioned above is
`called the “cell poly”.
`An area in a integrated circuit to which electrical
`connection is to be made is generally called an active
`area (A.A.). As capacitors have covered ever larger
`areas of individual cells and as the size of the cells has
`shrunk, the size of active areas as well as the corridors
`available for contacts to reach the A.A.’s has also
`shrunk. With these smaller spaces, the chances for leak
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`unacceptably large number of devices with cell-poly-to
`age between the contacts and transistor and capacitor
`bit-line current leakage. The H. Shibata reference
`components and the chances of high resistance or open
`shows a contact plug that penetrates several fabrication
`circuit contacts has increased. Thus a DRAM structure
`layers to contact active areas. The reference discloses
`and fabrication proces that provides more effective
`polysilicon spacers that do not close off the gaps be
`isolation of the contacts from the other parts of the
`DRAM circuit, optimizes the area in which contact
`tween transistor gates on either side of the active areas,
`but would not apply to bit line contacts in DRAM
`may be made, and at the same time permits smaller
`technology as the poly spacers would short the bit line
`contacts is highly desirable.
`to the cell poly. Further, the approach by Shibata does
`The business of fabricating CMOS semiconductor
`devices is a very competitive, high-volume business.
`not self-align the contact with respect to the transistor
`Thus manufacturing efficiency is highly important.
`poly (word lines) and would require the word lines to
`Product quality and reliability are also highly impor
`be spread further apart at the bit contact to allow for
`misalignment.
`tant. It is well-known in the art that reducing the num
`ber of mask steps in the integrated circuit manufactur
`A further approach is disclosed in US. Pat. No.
`ing process not only reduces manufacturing costs and
`5,045,899 issued to Arimoto. This shows a DRAM fab
`time but also generally increases the quality and reliabil
`rication process (see FIG. 12 in Arimoto) in which all
`the oxide is removed prior to deposition of the cell poly.
`ity of the end product, since the opportunities for dis
`This process does not utilize a self-aligned penetrating
`abling defects to occur are reduced. This in turn feeds
`back into further reduced manufacturing costs since
`bit line contact. Thus it will result in a larger cell size for
`a given photolithographic capability. Thus a need exists
`scrapped product is reduced. Thus, a circuit structure
`and process that not only permits more compact de
`for a DRAM structure and fabrication process which
`vices but also reduces the number of fabrication steps,
`utilizes a self-aligned penetrating bit contact and a re
`duced number of photo-mask steps, and which is scal
`particularly the number of mask steps, would be a sig
`able and can utilize metal bit line contacts because it
`ni?cant advance in the art.
`One approach to solving the above problems in a
`does not close off the gap between the word line spacers
`in 64 Mbit DRAMs.
`state-of-the-art DRAM fabrication process is described
`in “A 1.28 umz Bit-line Shielded Memory Cell Technol
`3. Solution to the Problem
`The present invention provides a method of inte
`ogy for 64 Mb DRAMs", by Y. Kawamoto et al, in
`grated circuit fabrication that utilizes a single etch stop
`IEEE 1990 Symposium on VLSI Technology, pp. 13-14.
`layer to form three different self-aligned contacts. In
`This fabrication uses a single photo step to de?ne the
`DRAM, the single etch stop layer is used to form metal
`storage node contacts and storage poly. This results in a
`reduced number of mask steps. However, this method
`to A.A. contacts that are self aligned to the transistor
`poly, to form storage poly contacts that are self aligned
`also results in a buried bit-line which requires that the
`bit line be subjected to the subsequent steps in forming
`to the word line poly, and also to form metal 1 to tran
`the capacitor which generally includes high tempera
`sistor poly contacts without any additional steps.
`In providing the above structure and process, the
`ture. Thus the bit line must be formed out of a tempera
`invention provides an integrated circuit that utilizes
`ture-resistant material, such as a silicide, which has
`contact-throughcell-poly technology while also pro
`higher resistance than a metal such as aluminum or
`viding a method of making metal-to-cell-poly contacts
`tungsten and thus reduces the speed of the DRAM. In
`with no additional photo/etch steps.
`addition, the use of a silicide bit line requires two addi
`The invention further provides an efficient integrated
`tional photo steps. i.e. the A.A. to silicide bit line
`contact photo and the silicide bit line photo.
`circuit structure and process that, when the overall
`Another approach is disclosed in "Two step Depos
`process is considered, requires fewer mask steps; in
`ited Rugged Surface (T DRS) Storagenode and Self
`particular it provides a structure and 0 process for mak
`Aligned Bitline-Contact Penetrating Cellplate (SAB
`ing compact multi-megabit DRAM with minimal mask
`ing steps which exploit self alignment of multiple ele
`PEC) for 64 Mb DRAM STC Cell” by H. Itoh et al. in
`ments and provides large cell capacitance for a given
`IEEE 1991 Symposium on VLSI Technology, pp. 9‘10.
`See also “A Novel Zero-overlap/Enclosure Metal In
`cell area.
`terconnection Technology For High Density Logic
`The present invention is particularly applicable to
`DRAM in that it provides a process for ef?ciently form
`VLSI’s”, by H. Shibata a]. in IEEE Jun. 12-13 1990
`ing multiple contacts in combination with a capacitor of
`VMIC Conference, pp. 15-21. The process and structure
`disclosed in the H. Itoh reference solves some of the
`large area. However, once its use in DRAM is under
`above problems by utilizing a bit line contact that passes
`stood, it is evident that it can be applied in other circuits
`through the cell poly, since this technology allows the
`also.
`.
`bit line is formed after the capacitor. However, to insu
`late the bit line from the cell poly, two layers of insula
`tion must be formed between the word lines, i.e. the
`word line spacers and the cell poly spacers. This greatly
`narrows the well for the bit line, and as a result the
`process is forced to use a poly/silicide bit line since
`metal would not properly ?ll such a narrow well. This
`again requires two additional photo steps. Moreover, in
`64 Mbit DRAM technology the gap between the word
`line spacers is only about 0.2 pm prior to the bit line
`contact de?nition. Thus the well between the spacers
`would be completely closed off with any cell poly oxide
`spacer thickness greater than 0.1 pm. A spacer this thin
`is very dif?cult to form, and would likely result in an
`
`SUMMARY OF THE INVENTION
`The invention provides a method of fabricating a
`integrated circuit dynamic random access memory
`(DRAM), the DRAM comprising a semiconducting
`wafer having a semiconducting substrate, a plurality of
`transistors formed on the substrate, each transistor in
`cluding a gate conducting layer, a capacitor formed on
`the substrate and having a capacitor ?rst conducting
`layer, a capacitor dielectric layer, and a capacitor sec
`ond conducting layer, an active area on the substrate
`adjacent one of the transistors, a bit line contact con
`tacting the active area, and a gate contact contacting
`the gate conducting layer, the method comprising the
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`NVIDIA Corp.
`Exhibit 1007
`Page 018
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`ing a capacitor ?rst conducting layer in the capacitor
`steps of: employing a ?rst etch stop layer to self align
`container and in the transistor gate conducting layer
`the capacitor ?rst conducting layer contact to the gate
`contact region, the capacitor ?rst conducting layer in
`conducting layer; employing the ?rst etch stop layer to
`electrical contact with the ?rst active area; f) forming a
`self align the bit line contact to the gate conducting
`capacitor dielectric layer on the capacitor ?rst conduct
`layer; and utilizing a single photo-mask and etch process
`ing layer; g) forming a capacitor second conducting
`to o de?ne the bit line contact and etch to the active
`layer on the capacitor dielectric layer; h) utilizing a
`area and to de?ne the gate contact and etch to the gate
`conducting layer. Preferably, the step of utilizing fur
`second photo-mask and etch process to remove the
`capacitor second conducting layer, the capacitor dielec
`ther comprises utilizing the single photo-mask and etch
`tric layer, and the capacitor ?rst conducting layer from
`process to de?ne a capacitor second conducting layer
`the gate conducting layer contact region; i) creating an
`contact and etch down to the capacitor second conduct
`ing layer.
`upper insulating layer on the wafer; j) utilizing a third
`photo-mask and etch process to de?ne a bit line contact
`In another aspect the invention provides a method of
`region above the second active area and to de?ne a gate
`fabricating a integrated circuit dynamic random access
`conducting layer contact region above the ?rst transis
`memory (DRAM), the DRAM comprising a semicon
`tor gate member; k) creating a capacitor insulating
`ducting wafer having a semiconducting substrate, a
`spacer between the capacitor layers and the bit line
`plurality of transistors formed on the substrate, each
`contact region; and 1) creating a bit line contact in elec
`including a gate conducting layer, a capacitor formed
`trical contact with the second active area and a gate
`on the substrate and having a capacitor ?rst conducting
`conducting layer contact in electrical contact with the
`layer, a capacitor dielectric layer, and a capacitor sec
`gate conducting layer of the ?rst transistor gate mem
`ond conducting layer, an upper insulating layer cover
`ber. Preferably, the step of utilizing a ?rst photo-mask
`ing the capacitor second conducting layer, an active
`and etch process further comprises utilizing the ?rst
`area on the substrate adjacent one of the transistors, a
`photo-mask and etch process to de?ne a capacitor con
`bit line contact contacting the active area, a gate
`ducting layer contact region in the lower insulating
`contact contacting the gate conducting layer, and a
`layer and the ?rst etch stop layer; the step of utilizing a
`capacitor conducting layer contact, the method com
`third photo-mask and etch process further comprises
`prising the step of: providing a single photo-mask; creat
`utilizing the third photo-mask and etch process to de
`ing a resist layer on the wafer and using the single
`?ne a capacitor conducting layer contact region in the
`photo-mask to pattern the resist layer to de?ne the bit
`upper insulating layer; and the method further com
`line contact and the capacitor conducting layer contact;
`prises creating a capacitor conducting layer contact in
`etching the pattern into the upper insulating layer and
`electrical contact with the capacitor second conducting
`through the capacitor second conducting layer to the
`layer. Preferably, the step of utilizing a third photo
`active area to form a bit line contact region while etch
`mask and etch process further comprises: etching
`ing the pattern into the upper insulating layer to the
`through the upper insulating layer to the capacitor sec
`capacitor second conducting layer to form a capacitor
`conducting layer contact region. Preferably, the
`ond conducting layer above the second active area
`while stopping the etch short of the capacitor second
`DRAM also includes a lower insulator layer between
`conducting layer in the region of the capacitor conduct
`the active area and the o capacitor second conducting
`ing layer region; etching through the capacitor second
`layer in the bit line contact region, which lower insula
`conducting layer above the second active area; and
`tor layer etches similarly to the upper insulating layer,
`etching through the lower insulating layer above the
`and wherein the step of etching comprises: etching
`second active area while completing the etch through
`through the upper insulating layer to the capacitor sec
`the upper insulating layer to the capacitor second con
`ond conducting layer in the bit line contact region while
`ducting layer in the region of the capacitor conducting
`etching through the upper insulating layer stopping
`layer contact region. Preferably, step j) comprises etch
`short of the capacitor second conducting layer in the
`ing through the upper insulating layer, the capacitor
`region of the capacitor conducting layer contact region;
`second conducting layer, the capacitor dielectric layer,
`etching through the capacitor second conducting layer
`the lower insulating layer, and the ?rst etch stop layer
`in the bit line contact region; and etching through the
`to the second active area; and step k) comprises: depos
`lower insulating layer in the bit line contact region
`iting an insulating ?lm on the wafer; and preferably
`while completing the etch through the upper insulating
`etching the insulating ?lm to expose the second active
`layer to the capacitor second conducting layer in the
`region of the capacitor conducting layer contact region.
`area while leaving the capacitor insulating spacer cov
`ering the capacitor second conducting layer. Altema
`In a further aspect the invention provides a method
`tively, a second etch stop layer is formed on the wafer
`for fabricating an integrated circuit comprising the steps
`between steps i) and j); step j) comprises etching
`of: a) providing an integrated circuit wafer having: a
`through the second etch stop layer, the upper insulating
`semiconducting substrate; a plurality of transistor gate
`layer, and the capacitor second conducting layer; and
`members each comprising a gate insulating layer
`step k) comprises: forming a third insulating layer on
`formed on the substrate and a gate conducting layer on
`the wafer; preferably etching through the third insulat
`the gate insulating layer; and ?rst and second active
`ing layer and the lower insulating layer to the ?rst etch
`areas on the semiconducting substrate: b) forming a ?rst
`stop layer in the bit line contact region while stopping
`etch stop layer on the wafer, covering the transistor
`on the second etch stop layer adjacent the bit line
`gate members and the active areas; c) creating a lower
`contact region and leaving the third insulating layer
`insulating layer on the wafer; d) utilizing a ?rst photo
`covering the capacitor second conducting layer along
`mask and etch process to de?ne a capacitor container in
`the sides of the bit line contact region; and etching
`the lower insulating layer and the ?rst etch stop layer
`through the ?rst etch stop layer. Preferably, the ?rst
`above the ?rst active area and a gate conducting layer
`etch stop layer is made of aluminum oxide. Alterna
`contact region in the lower insulating layer and the etch
`tively, each of the transistor gate members further com
`stop layer above a ?rst transistor gate member; e) form
`
`60
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`45
`
`50
`
`55
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`65
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`NVIDIA Corp.
`Exhibit 1007
`Page 019
`
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`25
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`30
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`20
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`5,292,677
`8
`7
`prise an insulating layer on the gate conducting layer,
`tor members, the transistor insulating spacer member,
`the integrated circuit wafer includes a transistor insulat
`and the active area; a capacitor conducting layer cover
`ing spacer member separating each of the active areas
`ing the lower insulating layer above the active area; and
`and the transistor members, and the insulating layer on
`an upper insulating layer covering the capacitor con
`the gate conducting layer, the transistor insulating
`ducting layer; creating an upper insulating layer etch
`spacer member, and the ?rst etch stop layer are made of
`stop layer over the second insulating layer; utilizing a
`silicon nitride.
`photo-mask process to de?ne a contact region penetrat
`The invention also provides a method of fabricating a
`ing the upper insulating layer etch stop layer, the upper
`bit line contact that penetrates the capacitor cell plate in
`insulating layer,‘ and the capacitor conducting layer
`a stacked capacitor DRAM comprising the steps of:
`above the active area; creating a third insulating layer
`providing a semiconductor wafer comprising: a semi
`on the wafer, the third insulating layer made of a mate
`conducting substrate having an active area; a plurality
`rial that etches similarly to the lower insulating layer;
`of transistor gate members, one on either side of the
`and performing an anisotropic etch of the third insulat
`active area, a transistor insulating spacer member be
`ing layer and the lower insulating layer to the active
`tween the transistor gate members and the active area, a
`area while leaving the capacitor insulating spacer cov
`lower insulating layer covering the transistor gate mem
`ering the capacitor conducting layer on the walls of the
`bers, the transistor insulating spacer member, and the
`contact region, the upper insulating area etch stop layer
`active area; a capacitor cell plate layer covering the
`serving as an etch stop on either side of the contact
`lower insulating layer above the active area; and an
`region. Preferably, the semiconductor wafer includes an
`upper insulating layer covering the capacitor cell plate
`active area etch stop layer between the lower insulating
`layer; utilizing a photo-mask process to de?ne a contact
`layer and the transistor gate members, transistor spacer,
`region penetrating the upper insulating layer, the capac
`and active area and the step of performing an isotropic
`itor cell plate layer, and the lower insulating layer
`etch comprises etching the third insulating layer and
`above the active area, the contact region being wider
`lower insulating layer with a ?rst etch and then etching
`than the distance between opposite sides of the transis
`the active area etch stop layer with a second etch. Pref
`tor spacer member across the active area, and creating
`erably, the contact region is suf?ciently wide so the
`a third insulating layer on the wafer, the third insulating
`opening between opposing sides of the capacitor spacer
`layer extending from the sides of the contact region
`member is as great or greater than the width of the
`sufficiently far to overhang the transistors; performing
`active area between opposing sides of the transistor
`an anisotropic etch of the third insulating layer to ex
`spacer member.
`pose the active area while forrning a capacitor insulat
`The invention not only provides a simpli?ed method
`ing spacer member covering the capacitor cell plate
`off making DRAMs with less mask steps and a signi?
`layer on the walls of the contact region, the opening
`cant amount of self alignment, but it also provides an
`between opposing sides of the capacitor spacer member
`integrated circuit structure that is more compact than
`being as great or greater than the width of the active
`prior art DRAMs and can be used in multi-megabit
`area between opposing sides of the transistor spacer
`DRAMS Numerous other features, objects and advan~
`member; and forming a bit line contact in the contact
`tages of the invention will become apparent from the
`region. Preferably, the method of fabricating a bit line
`following description when read in conjunction with
`contact further includes the step of creating an upper
`the accompanying drawings.
`insulating layer etch stop layer over the upper insulat
`ing layer, and the step of utilizing further comprises
`BRIEF DESCRIPTION OF THE DRAWINGS
`utilizing the photo-mask process to de?ne the contact
`FIG. 1 shows a cross-sectional view of a portion of a
`region penetrating the upper insulating layer etch stop
`partially fabricated DRAM integrated circuit according
`layer. Preferably, the step of utilizing a photo-mask
`to the preferred embodiment of the invention compris
`process to de?ne a contact region and creating a third
`ing a silicon substrate tha