Paper No.
`Filed: March 10, 2016
`
`
`Filed on behalf of: Samsung Electronics Company, Ltd.
`
`By: Naveen Modi (nVidia-Samsung-IPR@paulhastings.com)
`
`Joseph E. Palys (nVidia-Samsung-IPR@paulhastings.com)
`
`Paul Hastings LLP
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`
`
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`
`
`
`
`
`NVIDIA CORPORATION
`Petitioner
`
`v.
`
`SAMSUNG ELECTRONICS COMPANY, LTD.
`Patent Owner
`
`
`
`
`
`
`
`
`
`
`
`Case IPR2015-01320
`Patent No. 6,287,902
`
`
`
`
`
`
`
`
`DECLARATION OF DR. RICHARD B. FAIR
`
`
`
`
`
`
`
`
`
`Page 1 of 67
`
`SAMSUNG EXHIBIT 2006
`NVIDIA v. SAMSUNG
`Trial IPR2015-01320
`
`

`
`
`TABLE OF CONTENTS
`
`
`B.
`C.
`
`Page
`INTRODUCTION .......................................................................................... 1
`I.
`RESOURCES CONSULTED ........................................................................ 1
`II.
`III. BACKGROUND AND QUALIFICATIONS ................................................ 2
`IV. LEVEL OF ORDINARY SKILL ................................................................... 7
`V.
`SCOPE OF PROJECT .................................................................................... 8
`VI. CLAIM CONSTRUCTION ........................................................................... 8
`A.
`“an insulating spacer along a sidewall of the [second] patterned
`conductive layer” (Claims 1, 11, 12, 15, and 18) ................................. 9
`“an insulating layer” (Claims 1, 2, 8, 11, 12, 14-18) ......................... 10
`“forming a trench in said substrate, and wherein said field
`isolation layer fills said trench” (Claim 6) ......................................... 10
`VII. OVERVIEW OF THE ’902 PATENT AND CITED REFERENCES ........ 11
`A. Overview of the ’902 Patent ............................................................... 11
`B. Overview of Dennison ....................................................................... 13
`C. Overview of Agnello .......................................................................... 20
`D. Overview of Figura ............................................................................ 21
`VIII. RESPONSE TO PETITIONER’S MAPPING OF THE CLAIMED
`FEATURES TO THE CITED REFERENCES ............................................ 22
`A.
`Independent Claim 12 ........................................................................ 22
`1.
`Dennison Does Not Disclose or Suggest that the
`“Patterned Conductive Layer Is a Dummy Pattern
`Electrically Isolated From the Substrate and Circuits
`Thereon” ................................................................................... 23
`One of Ordinary Skill in the Art Would Not Have
`Combined Dennison With Agnello as Proposed by
`Petitioner .................................................................................. 29
`Claims 1-5, 7-11, 14-18 ...................................................................... 33
`B.
`Claims 6 and 13 .................................................................................. 33
`C.
`IX. CONCLUSION ............................................................................................. 36
`
`2.
`
`
`
`
`
`i
`
`
`
`Page 2 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`
`I.
`
`INTRODUCTION
`
`1.
`
`I have been retained by Samsung Electronics Company, Ltd. (“Patent
`
`Owner” or “Samsung”) for this inter partes review proceeding. I understand that
`
`this proceeding involves U.S. Patent No. 6,287,902 (“the ’902 patent”). I
`
`understand the ’902 patent is assigned to Samsung and issued from U.S. Patent
`
`Application No. 09/318,188, which is a division of U.S. Patent Application No.
`
`08/748,148, filed on November 12, 1996 (now abandoned).
`
`II. RESOURCES CONSULTED
`I have reviewed the ’902 patent, including claims 1-18. I have also
`2.
`
`reviewed the Petition for inter partes review (Paper No. 1) filed with the U.S.
`
`Patent and Trademark Office (“Office”) by nVidia Corporation (“Petitioner” or
`
`“nVidia”) on June 1, 2015 (Paper No. 1, the “Petition”). I have also reviewed the
`
`Patent Trial and Appeal Board’s (“Board”) decision to institute inter partes review
`
`(Paper No. 9, the “Decision”) of December 9, 2015, and any other materials
`
`identified in this declaration.
`
`3.
`
`I understand that in this proceeding the Board instituted review of
`
`the ’902 patent on two grounds: (1) obviousness of claims 1-5, 7-12, and 14-18
`
`over U.S. Patent No. 5,292,677 to Dennison (“Dennison”, Ex. 1007) and U.S.
`
`Patent No. 5,654,570 to Agnello (“Agnello”, Ex. 1008); and (2) obviousness of
`
`claims 6 and 13 over Dennison, Agnello, and U.S. Patent No. 5,472,904 to Figura
`
`
`
`
`
`Page 3 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`(“Figura”, Ex. 1009). (Decision at 18.) I have reviewed the exhibits and other
`
`documentation supporting the Petition that are relevant to the Decision and the
`
`instituted grounds, and any other material that I reference in this declaration.
`
`III. BACKGROUND AND QUALIFICATIONS
`I have summarized in this section my educational background, career
`4.
`
`history, publications, and other relevant qualifications. A more detailed account of
`
`my work experience, qualifications, and publications is included in my curriculum
`
`vitae, which is appended to this declaration.
`
`5.
`
`By way of summary, I have been a professor in the Department of
`
`Electrical and Computer Engineering at Duke University since 1981. My current
`
`tenured position is the Lord-Chandran Professor of Engineering in the Pratt School
`
`of Engineering.
`
`6.
`
`I received my Bachelor of Science degree in Electrical Engineering
`
`from Duke University in 1964. In 1966, I received a Master of Science degree in
`
`Electrical Engineering from Penn State University. In 1969, I received a Ph.D. in
`
`Electrical Engineering from Duke University.
`
`7.
`
`Since 1969, I have been involved in the research, teaching,
`
`development, design, and manufacturing of semiconductor devices and processes.
`
`For example, I have experience with thin film processes such as physical and
`
`chemical vapor deposition methods, modeling semiconductor technology,
`
`2
`
`Page 4 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`designing integrated circuits and semiconductor chips, designing high-density
`
`memory and analog circuit layouts, and fabricating integrated circuits. In addition,
`
`I have experience in the design, layout, and simulation of analog and digital
`
`integrated circuits.
`
`8.
`
`From 1969 to 1981, I worked at Bell Laboratories and I had direct
`
`experience with the manufacturing, design, and testing of numerous semiconductor
`
`devices and integrated circuits, including metal-oxide-semiconductor (MOS)
`
`dynamic memory chips. I researched and developed numerous semiconductor
`
`devices, including silicon and gallium arsenide transistors, analog and digital
`
`integrated circuits, photovoltaic devices, and thin film transistors (“TFTs”)
`
`fabricated in laser recrystallized polycrystalline silicon.
`
`9.
`
`During my time at Bell Laboratories, I worked on advanced silicon
`
`process development in the areas of photolithography, thin film deposition,
`
`metallization, etching, cleaning, plasma-assisted processing, LPCVD, ion
`
`implantation doping, and annealing/oxidation.
`
`10.
`
`In 1981, I became Professor of Electrical Engineering at Duke
`
`University. At the same time, I also served in a joint role as Vice President of the
`
`Microelectronics Center of North Carolina (“MCNC”) in Research Triangle Park,
`
`North Carolina. During 1990-1993, I led the Center for Microelectronic Systems.
`
`The MCNC and the Center for Microelectronic Systems were devoted to the
`
`3
`
`Page 5 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`development of advanced technologies for fabricating integrated circuits and for
`
`improvements in semiconductor manufacturing processes in general. My areas of
`
`responsibility as Vice President included analog and digital integrated circuit
`
`design, system design, semiconductor fabrication technology, advanced multichip
`
`module packaging, and studies in electronic materials, including amorphous
`
`semiconductors and multi-layered aluminum and copper interconnects. In my
`
`division at MCNC, we designed, fabricated, and tested the world’s first one-
`
`million-transistor processor chip in 1987. I also was responsible for the MCNC
`
`analytical lab, which included electron microscopy, atomic composition analysis,
`
`and sample preparation for reverse engineering studies. I have used such analytical
`
`tools to perform reverse engineering of semiconductor devices.
`
`11. While at MCNC, I helped setup a state-of-the-art CMOS processing
`
`facility and directed research on semiconductor processing including
`
`photolithography, wafer cleaning, annealing, ion implantation, plasma-enhanced
`
`CVD of thin films, metallization, and anisotropic etching processes. I was also
`
`involved in the development of an advanced patterning program that included
`
`advanced photoresist development, DUV lithography, and the design and
`
`development of a magnetron reactive etching tool. We conducted research on
`
`multi-level metal interconnects, barrier metallurgy, organic and inorganic inter-
`
`metal dielectrics, anti-reflective coatings, via and trench etching processes, and
`
`4
`
`Page 6 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`selective tungsten deposition for via filling. We also had an active research
`
`program in characterizing point defects in ion implanted amorphous and single
`
`crystal silicon, with the goal of understanding implantation defect annealing effects
`
`on dopant impurity diffusion.
`
`12.
`
`In 1994, I returned to Duke University full-time. Since then I have
`
`continued to teach courses on (1) the design and analysis of analog and digital
`
`integrated circuits, (2) semiconductor devices, (3) the chemistry and physics of
`
`transistor and integrated circuit fabrication, and (4) thin-film microfluidic devices,
`
`fluid dynamics, and applications. In addition, I have an active funded research
`
`program that involves undergraduate and graduate students.
`
`13.
`
`I have published over 170 papers in refereed and peer-reviewed
`
`journals and conference proceedings, contributed chapters to 12 books, edited nine
`
`books or conference proceedings, given over 130 invited talks in the field of
`
`electrical engineering, and I am a named inventor on 30 granted U.S. patents and
`
`24 pending U.S. patent applications.
`
`14.
`
`I am also a Life Fellow of the Institute of Electrical and Electronic
`
`Engineers (“IEEE”), a Fellow of the Electrochemical Society, past Editor-in-Chief
`
`of the Proceedings of the IEEE, and past Associate Editor of the IEEE
`
`Transactions on Electron Devices. I have been listed in Who’s Who in America,
`
`Who’s Who in Engineering, Who’s Who in the Semiconductor Industry, Who’s
`
`5
`
`Page 7 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`Who in Frontiers of Science and Technology, Who’s Who in Technology Today,
`
`and American Men and Women in Science. I am a recipient of the IEEE Third
`
`Millennium Medal, and I was awarded the Solid State Science and Technology
`
`Medal of the Electrochemical Society in April 2003.
`
`15. Based on my over 45 years of experience in thin film and bulk
`
`semiconductor device design, processing technology research and development,
`
`integrated circuit fabrication, research in point defects in amorphous and single
`
`crystal silicon, and the acceptance of my publications and professional recognition
`
`by societies in my field, I believe that I am considered to be an expert in the art of
`
`semiconductor processing, semiconductor device design and fabrication, and
`
`integrated circuit design and fabrication. I have extensive experience both in
`
`research and development, and in the implementation of semiconductor
`
`manufacturing processes. I have been qualified numerous times as an expert, and I
`
`have given expert opinion testimony relating to semiconductor processing,
`
`including MOSFET transistor gate formation, shallow-trench isolation, the use of
`
`dummy layer features in patterning, and chemical mechanical planarization.
`
`Additionally, I have extensive publications in the field of semiconductor
`
`technology, and my accomplishments have been recognized by both academic and
`
`professional societies.
`
`6
`
`Page 8 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`I am an independent consultant retained by Samsung to work on this
`
`16.
`
`case. I am compensated for my services in this case at the rate of $600 per hour.
`
`My compensation is not dependent upon my opinions or testimony or the outcome
`
`of this case.
`
`IV. LEVEL OF ORDINARY SKILL
`I am familiar with the level of ordinary skill in the art with respect to
`17.
`
`the inventions of the ’902 patent as of what I understand is the patent’s November
`
`12, 1996 effective filing date. Specifically, based on my review of the technology,
`
`the educational level and experience of active workers in the field, the types of
`
`problems faced by workers in the field, the solutions found to those problems, the
`
`sophistication of the technology in the field, and drawing on my own experience, I
`
`believe a person of ordinary skill in art at that time would have had i) a bachelor’s
`
`degree in electrical engineering, chemical engineering, materials science or physics
`
`and 2-3 years of experience in the development of semiconductor fabrication
`
`technology, or (ii) a master’s degree in the same areas with 1-2 years of the same
`
`work experience. All of my opinions in this declaration are from the perspective of
`
`one of ordinary skill in the art as I have defined it here.
`
`18. Petitioner’s expert, Dr. Jack C. Lee, has defined the person of
`
`ordinary skill in the art as a person with an undergraduate degree in electrical
`
`engineering (or an equivalent subject) together with three to four years of post-
`
`7
`
`Page 9 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`graduate experience designing semiconductor devices and fabrication processes, or
`
`a master’s degree in electrical engineering (or an equivalent subject) together with
`
`one to two years of post-graduate experience in designing semiconductor devices
`
`and fabrication processes. (Ex. 1013 at ¶ 19.) In my opinion, my definition is
`
`similar to the definition of Dr. Lee offers. While my analysis is based on my
`
`definition of the person of ordinary skill in the art, I believe my analysis and
`
`opinion would apply equally even under the definition of a person of ordinary skill
`
`in the art Dr. Lee proposes.
`
`V.
`
`SCOPE OF PROJECT
`
`19.
`
`I have been asked to respond to certain of Petitioner’s positions and
`
`opinions offered by Dr. Lee, including considering how one of ordinary skill in the
`
`art would have understood the references mentioned above in relation to the claims
`
`of the ’902 patent.1 I understand that the Board relied on Petitioner’s positions and
`
`Dr. Lee’s opinions in its Decision. As such, when I respond to Petitioner’s
`
`positions and Dr. Lee’s opinions in this declaration, I am necessarily responding to
`
`the Board’s Decision as well. My findings are set forth below.
`
`VI. CLAIM CONSTRUCTION
`
`
`1 If I do not address a particular statement made by Petitioner, the Board, or Dr.
`
`Lee, that does not mean that I necessarily agree with that statement.
`
`8
`
`Page 10 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`I understand that Petitioner identified certain terms for construction in
`
`20.
`
`the Petition. (Pet. at 28-31; see also Ex. 1013 at ¶¶ 79-90.) Below is what I
`
`understand to be a summary of the constructions proposed by Petitioner and Patent
`
`Owner, along with the construction (if any) adopted by the Board in its institution
`
`decision.
`
`A.
`
`“an insulating spacer along a sidewall of the [second] patterned
`conductive layer” (Claims 1, 11, 12, 15, and 18)2
`
`Petitioner’s Proposed
`Patent Owner’s Proposed
`Construction
`Construction
`Plain and ordinary meaning an insulating spacer, along
`a sidewall of the [second]
`patterned conductive layer,
`that prevents etch damage
`to the field isolation layer if
`the contact hole is
`misaligned
`
`Board’s Construction
`
`No construction
`proposed
`
`
`2 I identify only the challenged claims that expressly recite the terms at issue.
`
`9
`
`Page 11 of 67
`
`

`
`“an insulating layer” (Claims 1, 2, 8, 11, 12, 14-18)
`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`
`B.
`Patent Owner’s Proposed
`Construction
`a structure comprising one
`or more electrically
`insulating sublayers
`
`Petitioner’s Proposed
`Construction
`Plain and ordinary meaning No construction
`proposed
`
`Board’s Construction
`
`C.
`
`“forming a trench in said substrate, and wherein said field
`isolation layer fills said trench” (Claim 6)
`
`Petitioner’s Proposed
`Patent Owner’s Proposed
`Construction
`Construction
`Plain and ordinary meaning Plain and ordinary meaning No construction
`proposed
`
`Board’s Construction
`
`
`
`21.
`
`I also understand that the Board construed “dummy pattern,” which is
`
`a term recited in claims 1, 11, 12, 15, and 18, as “a patterned conductive layer that
`
`serves no electrical purpose and is electrically isolated from the substrate and
`
`circuits thereon.” (Decision at 7.)
`
`22.
`
`I have considered the constructions proposed by the Petitioner, the
`
`Patent Owner, and the Board. My analysis and conclusions as set forth below in
`
`Section VIII remain the same under any of these constructions. For the remaining
`
`claim terms of the ’902 patent that were not identified for construction by any
`
`party (including the Board), I have given those terms their plain and ordinary
`
`meaning, as would be understood by a person of ordinary skill in the art, at the
`
`time of the invention, having taken into consideration the language of the claims,
`
`the specification, and the prosecution history of record.
`
`10
`
`Page 12 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`VII. OVERVIEW OF THE ’902 PATENT AND CITED REFERENCES
`A. Overview of the ’902 Patent
`23. The ’902 patent is directed to a method of providing improved
`
`alignment tolerances for contact holes made to scaled microelectronic structures.
`
`(Ex. 1001 at 2:44-48.) A problem that the ’902 patent addresses is how to reliably
`
`make contact holes for MOSFETs in smaller and smaller spaces on a wafer when
`
`device integration density increases. (Id. at 2:10-41.) For instance, the ’902 patent
`
`notes that a misaligned contact hole 24 may expose a portion of the active region
`
`of a MOSFET and an adjacent field region that may lead to the flow of leakage
`
`currents into the well area of the MOSFET. (Id. at 2:10-20, Fig. 2.)
`
`24. To remedy the above problem resulting from contact hole
`
`misalignment, the ’902 patent discloses an exemplary method of forming etch
`
`inhibiting layers on the field isolation region adjacent to the active region (where
`
`transistors are formed). The etch inhibiting layer improves alignment tolerance for
`
`a contact hole between a first patterned conductive layer on an active region of the
`
`substrate and an adjacent field region (which isolates an active region). (Id. at
`
`4:41-50.) The exemplary solution disclosed in the ’902 patent may be better
`
`understood by referring to the description associated with figures 4-8.
`
`25. Figure 4 of the ’902 patent discloses an exemplary embodiment in
`
`which a contact hole 50 is placed between first and second patterned conductive
`
`11
`
`Page 13 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`layers 44, 44a to make contact to the doped area 43 (source or drain of a transistor)
`
`in the active region. (Id. at 4:10-37.)
`
`
`
`
`
`26. An insulating layer 48 covering the first and second patterned
`
`conductive layers 44, 44a, active region 43, and field isolation layer 42 is etched to
`
`form contact hole 50. (Id. at 5:62-65, 6:8-11, Fig. 7.)
`
`27. Conductive layer 44a (annotated in pink below), which is formed on
`
`the field isolation layer 42, in combination with sidewall spacers 46a (annotated in
`
`blue below) acts as an etch inhibiting layer protecting the field isolation layer from
`
`any undesired etching in case of a contact hole misalignment. (Id. at 6:1-18, Fig. 8
`
`(annotated below).) Conductive layer 44a, which is electrically isolated and is a
`
`dummy pattern that protects against contact hole misalignment. (Id. at 4:25-30,
`
`5:33-44, 6:20-23.) According to the ’902 patent, forming an electrically isolated
`
`12
`
`Page 14 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`conductive layer 44a that serves no electrical function was “unlike methods of the
`
`prior art.” (Id. at 5:33-44.)
`
`
`
`
`
`(Id. at Fig. 8 (annotated).)
`
`28. Claims 1-18 of the ’902 patent recite some of the novel features
`
`discussed above that protect the field region from contact-hole misalignment,
`
`resulting in improved margins for forming contact holes. For instance, claim 1 of
`
`the ’902 patent recites, inter alia, “forming an etch inhibiting layer on said field
`
`isolation layer adjacent said active region of said substrate, . . . wherein said etch
`
`inhibiting layer comprises a second patterned conductive layer and an insulating
`
`spacer along a sidewall of the second patterned conductive layer, . . . wherein the
`
`second patterned conductive layer is a dummy pattern electrically isolated from the
`
`substrate and circuits thereon.” (Ex. 1001, claim 1.)
`
`B. Overview of Dennison
`
`13
`
`Page 15 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`29. Dennison relates to a “process for fabrication of a stacked capacitor
`
`DRAM.” (Ex. 1007 at 1:11-13.) The various embodiments of Dennison are
`
`disclosed “in terms of silicon-based CMOS technology” where CMOS
`
`(complementary metal oxide semiconductor) refers to an integrated circuit “in
`
`which both N-channel and P-Channel MOSFETS . . . are used in a complimentary
`
`fashion.” (Id. at 1:40-49.)
`
`30. An exemplary memory cell is disclosed by Dennison in Fig. 14, an
`
`annotated version of which is reproduced below from the declaration of
`
`Petitioner’s declarant, Dr. Jack Lee.
`
`(Id. at Fig. 14 (annotated); Ex. 1013 at ¶ 41.)
`
`
`
`14
`
`Page 16 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`31. Figure 1 of Dennison “shows a cross-sectional view of a portion of a
`
`partially fabricated DRAM integrated circuit . . . .” (Ex. 1007 at 8:42-50.) Figure
`
`1 (reproduced below) illustrates two transistor gate members 20B and 20C, each of
`
`which includes an oxide layer 14, gate conducting layer 22 (referred to as a “word
`
`line”), and an insulating protective layer 28. (Id. at 10:52-61.) “The gate
`
`conducting layer 22, or word line, preferably comprises a polysilicon layer 24,
`
`referred to alternatively as the transistor poly or poly 1 herein, and a tungsten
`
`silicide . . . layer 26.” (Id. at 10:52-61.) As shown in figure 1, insulating spacer
`
`members are formed on either side of each gate 20B and 20C. (Id. at 10:62-64, Fig.
`
`1.)
`
`(Id. at Fig. 1 (annotated).)
`
`15
`
`
`
`Page 17 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`32. As illustrated in figure 1 above, Dennison also discloses a third gate
`
`structure above field oxide area 16 and a transistor gate member 20A, which is
`
`formed in peripheral area 13 of wafer 10. (Id. at 10:1-4, 15:50, Fig. 1.)
`
`Dennison’s disclosure is silent on the constituent layers of the third gate structure,
`
`but based on the patterns shown in figure 1, one of ordinary skill in the art would
`
`have understood that the third gate structure has the same layers as gates 20B and
`
`20C. That is, the third gate structure would also include a conductive portion, i.e.,
`
`gate conducting layer 22. But Dennison does not explicitly disclose the function of
`
`any of the layers constituting the third gate structure. Moreover, because Dennison
`
`does not disclose a plan view in any of its figures; it is not possible to determine
`
`whether any of the layers in the third gate structure are electrically isolated from
`
`other circuits. Dennison, however, discloses a stacked capacitor DRAM cell,
`
`which was invented in 1978, and one of ordinary skill in the art at the time of
`
`Dennison’s filing would have understood that the conductive portion of the third
`
`gate structure in such a stacked capacitor DRAM cell would be a word line.
`
`33. Specifically, the stacked capacitor DRAM cell structure was invented
`
`by M. Koyanagi in the 1970s. (Ex. 2007 at 1.) Mr. Koyanagi explained the
`
`structure of the stacked capacitor cell previously disclosed by him in the 1970s in a
`
`paper published in 2008, entitled “The Stacked Capacitor DRAM Cell and Three-
`
`Dimensional Memory,” which is attached herewith as Ex. 2007. (Id. at 1.) As
`
`16
`
`Page 18 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`seen from figure 1 of Ex. 2007, the third gate structure has a conductive portion
`
`disposed on top of a field isolation layer, wherein the conductive portion is a “word
`
`line.” (Id. at 1.)
`
`
`(Ex. 2007 at 1, illustrating the basic structure of a stacked capacitor cell.)
`
`34. One of ordinary skill in the art would have understood that the “gate”
`
`in figure 1 of Ex. 2007 corresponds to gate 20B in Dennison and the layer marked
`
`as “word line” corresponds to the conductive portion of the third gate structure in
`
`Dennison.
`
`35. As shown below, figure 14 of Dennison (which corresponds to the
`
`partially fabricated device shown in figure 1 of Dennison) has the same basic
`
`structure as the above well-known stacked capacitor DRAM cell, thereby
`
`indicating that the conductive portion in the third gate structure is a word line and
`
`not “electrically isolated.” Because the conductive portion is a word line, it serves
`
`an electrical purpose and is not a “dummy pattern.” (Id.)
`
`17
`
`Page 19 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`
`
`
`(Ex. 1007 at Fig. 14, annotated.)
`
`36. Another stacked capacitor DRAM cell from the early 1990s is shown
`
`below in annotated figure 4 of U.S. Patent No. 5,142,438 (“the ’438 Patent,” Ex.
`
`2008). The annotated figure shows three wordlines 11A, 11B, and 11C.
`
`According to the ’438 Patent, “wordlines 11A and 11C are traversing field oxide
`
`regions 12A and 12B respectively. Wordline 11B, on the other hand is traversing
`
`an active area of substrate 13, thus forming an access transistor in combination
`
`with storage-node junction 14 and access-node junction 15.” (Ex. 2008 at 2:20-27,
`
`emphasis added.) A stacked capacitor is formed at the storage node junction by a
`
`tantalum oxide dielectric layer 33 interposed between polysilicon cell plate layer
`
`42 and storage-node plate 31. (Id. at 4:57-5:15, claim 1.)
`
`18
`
`Page 20 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`
`
`
`(Id. at Fig. 4, annotated.)
`
`37. Again, the structure of the stacked capacitor cell in the ’438 patent is
`
`analogous to figure 14 of Dennison and is further evidence that the conductive
`
`portion of the third gate structure would have been understood by one of ordinary
`
`skill in the art to be a word line and not an electrically isolated dummy pattern.
`
`38. Based on the figures in Dennison, one of ordinary skill in the art
`
`would have also understood that gate member 20A in Dennison has the same
`
`layers as gate members 20B and 20C, because of the similar cross-hatched layers.
`
`Gate member 20A is utilized to contact the gates of gate members 20B and 20C.
`
`Specifically, as shown in Fig. 2, contacts to gate members 20B and 20C are formed
`
`in the peripheral region 13 by forming a contact hole 38 to gate conducting layer
`
`22 over field oxide area 16. (Ex. 1007 at 11:40-45, 61-65.) One of ordinary skill
`
`in the art would have understood, based on the disclosure and the knowledge of
`
`such a person, that for a contact to be made with gate conducting layer 22 in region
`
`19
`
`Page 21 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`38, gate conducting layer 22 would have to be extended to the peripheral region 13,
`
`i.e., from active region 29A to field oxide area 16. This extension of a gate
`
`conducting layer to the field oxide region for forming a gate contact is not
`
`explicitly shown in the figures of Dennison, because Dennison does not show a
`
`plan view. But such a feature would have been apparent to one of ordinary skill in
`
`the art as an industry-standard design rule requirement.
`
`C. Overview of Agnello
`39. Agnello is directed to a method of fabricating “a self-aligned insulator
`
`on [a] gate conductor.” (Ex. 1008 at 1:6-9.) More particularly, Agnello is
`
`“concerned with a process for fabricating a gate structure in a CMOS device.” (Id.
`
`at 2:49-50.)
`
`40. The fabrication process begins with the formation of a gate stack
`
`consisting of a gate isolation layer 8, a polycrystalline silicon layer 9, a sacrificial
`
`gate cap layer 17, and sidewall spacers 18. (Id. at 3:36-6:10, Fig. 7.) Once this
`
`gate stack is created, an interlayer dielectric 16 is “blanket deposited over the
`
`entire wafer.” (Id. at 6:11-12.) The blanket deposited dielectric layer 16 is then
`
`planarized to expose the top of the gate stack. (Id. at 6:14-30.)
`
`41. Agnello notes that the planarization of the dielectric layer 16 may
`
`result in a “dishing” effect. (Id. at 6:31.) A “dishing” effect refers to the creation
`
`of an uneven surface level. To prevent dishing of the dielectric layer 16, Agnello
`
`20
`
`Page 22 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`proposes using the conventional practice of placing “additional” gate shapes on the
`
`substrate. (Id. at 6:31-40.) These additional gate shapes serve no electrical
`
`purpose but are provided solely to increase the number of gates and ensure a
`
`uniform distribution of gates “to enable more uniform planarization of the ILD,”
`
`i.e., prevent “dishing” of the ILD. (Id.)
`
`D. Overview of Figura
`42. Figura discloses a method for creating a type of field oxide region,
`
`specifically creating narrow and wide field oxide regions having different
`
`characteristics at the same time. (Ex. 1009 at 3:36-37.) The problem Figura was
`
`trying to solve was how to create “trench-like” isolation structures in tight areas on
`
`a chip while maintaining LOCOS-style isolation on the wide open field regions. (Id.
`
`at 2:15-18) In the method of Figura, the substrate is first covered with oxide and
`
`nitride. (Id. at 3:5-25.) A photomask and dry etch are then used to remove the
`
`portion of the nitride, oxide and the Si substrate where the field oxide is to be
`
`grown. (Id. at 3:31-35.) Into the trench, a thin layer of oxide is grown, and then a
`
`layer of nitride is deposited. (Id. at 3:64-4:14.) A sacrificial layer is then added
`
`over the entire area. (Id. at 4:15-17.) Because the sacrificial layer is deposited
`
`conformally until it fills the narrow field oxide area, the sacrificial layer depth is
`
`larger in the narrow field oxide area than in the wide field oxide area as shown in
`
`Figure 2. (See id. at 4:16-25.) The sacrificial film layer 6 is then removed by
`
`21
`
`Page 23 of 67
`
`

`
`Declaration of Dr. Richard B. Fair
`IPR2015-01320
`etching, except that some of the sacrificial layer remains in the narrow field oxide
`
`regions 11 due to the sacrificial layer being initially thicker in the narrow regions.
`
`(Id. at 4:26-35, Fig. 3.) The nitride layer 5 is then removed from everywhere
`
`except where it is covered by the remaining sacrificial layer 6. (Id. at 4:36-43.) In
`
`the wide field oxide area, oxidation occurs to fill the region 12. (Id. at 4:44-64.) In
`
`the narrow isolation area 11, the oxidation occurs using the sacrificial layer.
`
`Because the amount of sacrificial layer remaining in the narrow isolation area is
`
`limited, the amount of oxide created is also limited in this area. (Id. at 4:56-5:6.)
`
`VIII. RESPONSE TO PETITIONER’S MAPPING OF THE CLAIMED
`FEATURES TO THE CITED REFERENCES
`A.
`43.
`
`I understand that independent claim 12 recites, inter alia, that the
`
`Independent Claim 12
`
`“patterned conductive layer is a dummy pattern electrically isolated from the
`
`substrate and circuits thereon.” It is also my understanding that Petitioner and Dr.
`
`Lee contend that Dennison discloses this feature and, to the extent Dennison does
`
`not disclose this feature, such a feature would have been obvious in view of
`
`Agnello. (Pet. at 35-39; Ex. 1013 at ¶¶ 10