throbber
MOSIS Scalable CMOS Design Rules
`
`(revision 7)
`
`J671-] Pi
`
`the M0515' Service
`Information Sciences Institute
`
`University of Southern California
`4676 Adrniralty Way
`Mariiia del Rey, CA 90292
`pi@isi.edu
`August 1, 1995
`
`1
`
`Introduction
`
`1.1
`
`SCMOS Design Rules
`
`This document defines the official layout design rules for MOSIS scalable CMOS (SCMOS)
`design technology. It supercedes all previous revisions. Ti
`In SCMOS technology, circuit geometries are drawn according to Mead and Coi1wa_v”s
`,\—based methodology
`The unit of measurement, A, can easiIy be scaled to different
`fabrication processes as semiconductor technology advances.
`A user design submitted to MOSIS in SCMOS technology should be in either Calma
`GDSII format
`[1] or Caltech Intermediate Form (CIF Version 2.0)
`Each design has
`a technology rlesigmitiozi. that goes with it for the purpose of MOSlS‘s data prep. At the
`moment, three designations are used to specify CMOS processes. Each designation may have
`one or more options associated for the purpose of either (1) special features for the target
`process or
`the presence of novel device in the design. At the time of writing, MOSIS is
`offering six CMOS processes from three different foundries with drawn feature sizes ranging
`from 2.0 pm down to 0.6 pm.
`A list of the things that. have either been revised or added since our last release can be
`found in Appendix A. Please refer to the specific sections for detailed descriptions.
`
`2 Standard SCMOS
`
`The standard CMOS technology accessed by MOSIS is a single polysilicon, double metal,
`bulk CMOS process with enhance1nent—mode n—MOSFET and p—MOSFET devices
`
`SAMSUNG EXHIBIT2003
`
`NVIDIA V. SAMSUNG
`
`TRIAL IPR2015—01327
`
`SAMSUNG EXHIBIT 2003
`NVIDIA v. SAMSUNG
`Trial IPR2015-0132(cid:19)
`
`Page 1 of 28
`
`

`

`2.1 Well Flavor
`
`Three types of desigrzation are used to indicate the flavor of the Well substrate) used for
`fabrication as shown in Table 1.
`
`Description
`Scalable CMOS N—well
`
`|
`
`
`
`Scalable CMOS P—Wcll
`
`Scalable CMOS l*lither—Well
`
`II
`
`C1\'
`
`Table 1: SCMOS Well flavor designations
`
`The SCN and SUP designations with a submitted project are designed for fabrication
`of the specified well only. For convenience, in both cases, a project may include the ’other’
`Well, but it will always be ignored. SCE projects are used for fabrication in any CMOS
`process, N—Well or 13-well (either). A project with SCE designation must include both Wells
`(and correspondingly, well/ substrate contacts for proper bias). For any given fabrication
`process, the ’other° Well will be ignored during the mask generation.
`lf twin—tub processes
`are offered in the future. both wells will be used.
`
`2.2
`
`SCMOS Options
`
`SCMOS options are used to designate projects which use additional layers beyond the stan—
`dard CMOS technology. Each option is named by a designator that is tacked onto the basic
`designator for its well flavor. Reader should note that not all possible combinations (With
`Well flavor) are actually available. The currently available SC MOS options are listed in Table
`2.
`
`two undeclared options also exist. One with
`In addition to the options in Table 2,
`respect. to the existence of big/1 voltage MOSFET devices; the other. a tz'gh.t metal rule for
`high—density metal interconnections. For options available to specific process, please refer to
`Table 3 for the current MOSIS offerings.
`
`2.3
`
`SCMOS Oiferings
`
`M0813 is currently offering the fabrication processes as shown in Table 3. For each process,
`the list of appropriate SCMOS technology designations is listed. Note that Whenever SCNXX
`appears in the table, SCEXX is also appropriate. Likewise, whenever SCPXX appears. SCEXX
`is also appropriate.
`
`2(7CD layer not included.
`2CCD layer not included.
`
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`

`

`Designation Long form
`E
`Electrode
`
`Description
`Adds ii. second polysilicon layer (electrode)
`that can serve as either one of electrode of a poly
`capacitor or as a. gate for transistors. A Contact
`
`layer (electrode_contact) to metal also exists. Adds electrode layer (as i11 E option) plus a
`
`
`
`pbase layer for the construction of Vertical NPN
`transistor. A buried_ccd layer is also present.
`for buried—cha.nnel CCD applications
`Adds second via (via2) and third metal (111etal3T
`layers.
`
`Triple Metal
`
`Linear Capacitor Adds a cap_well layer for the implementation ori
`linear capacitors.
`L
`Micromeclianical Adds two new layers, mems_open and
`Systems
`mems_etch_stop for the purpose of micro
`niechanical device construction.
`
`3M
`
`LC
`
` 4
`
`
`_MEMS
`
`Table ‘2: SCMOS technology options
`
`Process
`
`
`2.0 pm N—well
`2.0 pm P—Well
`1.5 pm N-Well
`AMI
`1.2 pm N—Well
`Orbit
`AMOSI/CMOS34
`HP
`HP
`Cl\«lOS26B/G
`
`
`
`
`
`
`Lambda
`
`
`
`SCNA, SCNE, SCN. SCNA_MEMS M
`
`1.0 pm
`1.0 pm
`J ., SCP, SCPE_MEMS
`0.8 pm SCNA1, SCNE, SCN, High Voltage
`0.6 pm SCNA2
`0.6 pm SCNLC, sc1\', Tight Metal
`0.5 gm SClN3lVl, SCN, Tight l\'letal
`
`
`
`
`
`Foundry
`Orbit
`Orbit
`
`
`
`Table 3: MOSIS SCMOS technology offerings
`
`Page 3 of 28
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`Page 3 of 28
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`

`

`3 CIF and GDS Layer Specification
`
`Design geometries (or mask features) can be represented either in GDS~Il or Caltech lnter—
`mediate Form (CIF Version 2.0). While the former is coded in binary format, the latter is a
`plain text file and can be easily interpreted. For detailed syntax and semantic specifications
`of Calma/GDS-II or CIF, please refer to [1] and
`respectively.
`In GDS II format, a mask layer is specified by a layer number between 0 and 63. MOSIS
`now reserves layers numberd from 21 to 62 for mask specification and future extension.
`Layers defined out of this range can be used by customers for their own purpose. MOSIS
`will ignore all geometry information on these layers (0 to 20 and 63) and map it to the CIF
`comment layer (CX) if necessary. In this revision. 6 new layers are added starting from layer
`number 21.
`
`o CVP (layer 21) is used to indicate high—voltage p—type area. More comprehensive
`information can be found in
`
`0 CVN (layer 22) is used to indicate higlrvoltage p—type area.
`
`0 COP (layer 23) is used to indicate substrate pit opening area for MEMS devices.
`
`0 CPS (layer 211) is used to indicate substrate p+ etching—stop area for MEMS devices.
`
`0 CCC (layer 25) is used for generic contact.
`
`0 XP (layer 26) is used to indicated pad location.
`
`Users should be aware that there exist only one type of physical contact (i.e. between
`first metal and poly or active). though several have been defined for historical reason and
`are retained for backward compatibility. A complete list of SC)/IOS layers can be found in
`Table 4 on next page.
`
`4 Sub-micron Rules
`
`The SCMOS design rules have been historically designed for 1.0 — 3.0 micron CMOS tech-
`nology. To take full advantage of advanced submicron process technology, a set of rules have
`been selected to be modified to fit our foundry’s rules.
`Table -5 lists those rules in MOSlS’s HP CMOSZGG process that are different between
`SCl\"3l\/I and SCN3M_26G technology specification with /\ equals to 0.5 and 0.4 pm respec-
`tively.
`
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`

`

`
`
`C117’ name
`SCMOS layer
`P_HIGH_VOLTAGE
`CVP
`
` GDS H number GUS H type
`
`
`
`HACfiO‘lO1u;»‘IoI>-fa-:Jr-lb->-J\—*>4‘a>-J“—»-Is>$‘\—t"['l‘l\JL\D
`~1o:L\3»—c>©¢_o:o1A‘~—wLo~o‘€4‘\1C3to»—
`
`CI.)
`
`CH C}!
`
`K\'4'<3)OJC;\Qn_JC7[\.'>I-—'CDO0
`
`I
`
`3
`
`63
`
`
`
`
`
`CVN
`N_HIGH_VO LTAGE
`COP
`l\’IE1\'IS_OPEN
`MEMS_ETCH_STOP CPS
`PADS
`XI’
`
`P_\/VELL
`
`N _VV ELL
`ACTIVE
`P_PLUS_SElJE(:7T
`N_PLUS_SELEC'/T
`POLY
`
`CVVP
`
`C/'\"\r’1\'
`CAA
`CSP
`CSN
`CPG
`
`CONTACT
`NI ETAL 1
`VIA
`
`META L2
`GLASS
`ELECTRODE
`
`BUR.IED_CCD
`PBASE
`CAP-“/ELL
`VIA2
`METAL3
`
`CCC, CCP. C-CA, CC/E
`C IVIF
`C/VA
`
`C MS
`COG
`CEL
`
`C/Cl.)
`CTBA
`CVVC
`CVS
`CM T
`
`J£_Ol\"U\/1EI\VT
`
`_j CX
`
`Table 4: SCMOS technology CIF and GDS layers
`
`Page 5 of 28
`
`Q7!
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`Page 5 of 28
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`

`

`SCMOS
`
`SCMOS
`
`SCMOS_26G
`
`/\ = 0.5;Lm
`
`(Tight Metal)
`/\ = 0.v3[LI11
`
`A = 0.4,um
`12
`
`.
`
`‘
`
`~rs
`CT!
`
`Cz~JU1Ca.'Jv.)Ca.'>C~C~bU
`>-\BO‘3>-P*k’.~7Q~'JC«Ol:\Dl\'3Q‘(
`
`Description
`
`VVELL_W
`WELL_S_DIFF
`WELL_O_ACT_XTOR
`WELL_S_ACT_XTOR
`POLY_S
`
`CON_S
`MLW
`MLS
`M2_W
`
`M2_S
`M3_W
`
`M3_S
`
`Table 5: SCMOS options for CMOS26G
`
`Page 6 of 28
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`Page 6 of 28
`
`

`

`5
`
`SCMOS Design Rules
`
`Well (CWN, CWP)
`
`1.1 Mirlimum Width
`
`1\/1111111111111 spacing betWee11 Wells at diffe1‘e11t potelltial
`1.2
`.\«’111l11'I111IIl spacing betWee11 wells at same p0te11tia1
`1.3
`1.4 Millimum spacing between wells of (1iiTere11t type
`(if both are drawn)
`
`10
`
`9
`0 01‘ 6
`
`0
`
`1.2
`fp
`
`1.3
`pp
`
`..................
`
`1_1
`
`........... ..<.:..v.v.1%f
`
`Page 7 of 28
`
`7
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`

`

`Active (CAA)
`
`2.1
`
`.\/Iinimum width
`
`2.2 Minimum spacing
`2.3
`Source / drain active to Well edge
`2.4
`Stibstrate/Well Contact active to Well edge
`2.5
`Minimum spacing between active of different implant
`
`OI4
`
`2.2
`
`2.5
`
`."""‘“‘“""""'1"'"'
`E
`1
`E
`
`CAA
`
`------------
`Z Z M 2 ‘ _ _ "E $ 2.4
`1
`~
`
`CAA
`
`:
`
`I
`:
`
`E
`
`I
`I
`E
`19%? .................................. L .... __C_S_N_:
`
`21$
`
`21$
`
`CAA
`CAA
`LC.sN_ _______________
`P—1'egi0n
`23
`N_ regioii ________________________
`E
`2
`
`CAA
`
`CAA
`
`2.2
`
`2.5
`
`Page 8 of 28
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`

`

`Poly (CPG)
`
`3.1
`
`3.2
`
`3.3
`
`3.4
`
`3.5
`
`Minimum Width
`
`Minimum spacing
`
`Mi11imum gate extension of active
`
`Minimum active extension of ploy
`Minimum field poly to active
`
`I--‘C»Dk'J[\Dl\D
`
`3.5
`
`cm
`
`CPG
`
`CAA
`
`W
`
`i
`
`W
`
`3.1
`
`3.2 t
`
`i 3-4
`
`CAA
`
`3.3
`
`Page 9 of 28
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`

`

`Select (CSN, CSP)
`
`4.1 Minimum select spacing to channel of transistor to
`ensure adequate source / drain Width
`4.2 Minimum select overlap of active
`
`4.3 Minimum select overlap of Contact
`
`4.4 Minimum select width and spacing
`(Note: P—se1ect and N—se1ect may be coincident, but
`must not overlap)
`
`l\.'J!—‘l\3OJ
`
`
`
`4 . 2
`
`CWP
`
`CWN
`
`Page 10 of 28
`
`10
`
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`

`

`Simple Contact to Poly (CCP)
`
`5.1.a Exact C011ta(*’r size
`
`-5.2.21 Mi11i1n11111 poly overlap
`
`Mi11i111um Contact spacing
`
`Page 11 of 28
`
`11
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`

`

`Simple Contact to Active (CCA)
`
`6.1.a Exact Contact size
`
`6.2.a Miiiimum active overlap
`
`6.3.a Minimum Contact spacing
`
`6.4.a Minimum spacing to gate of transistor
`
`2x2
`
`1.5
`
`6.4.a
`
`6.3.a
`
`CCA
`I I
`CAA
`
`CAA
`
`6.2.a
`
`W
`
`i
`
`6.1.a
`
`CPG
`
`Page 12 of 28
`
`12
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`

`

`Alternative3 Contact to Poly (CCP)
`
`5.1.b
`
`5.2.b
`
`5.3.b
`
`5.4.13
`
`-5 -5 b
`5i6:b
`
`Exact Contact size
`
`Mi11imu1'I1 poly overlap
`
`MiI1imu1I1 contact spacing
`Minimum spacing to other poly
`Minimum spacing to active (one contact)
`Minimum spacing to active (imaily contacts)
`
`C»Jl\’)H‘—l\D»—Il\')
`
`5.1.b
`
`5.2.1)
`
`i
`
`T
`
`CPG
`
`5.4.b
`
`CAA
`
`mi _
`
`5.3.b
`
` CAA¢
`
`5.5.b
`
`3If you have difficulties with half lambda rule.
`
`13
`
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`

`

`AlternatiVe4 Contact to Active (CCA)
`
`6.1.b
`
`Exact Contact size
`
`6.2.b
`
`6.3.b
`
`6.4.b
`
`6.-5.b
`
`6.6.b
`
`6.7.b
`
`6.8.b
`
`Minimum active overlap
`
`Mi11in1um Contact spacing
`
`Minimum spacing to diffusion active
`Minimum spacing to gate of transistor
`Minimum sapcing to field poly (one. contact)
`Minimum spacing to field poly (many contacts)
`Minimum spacing to poly Contact
`
`r-l‘A0J[\'JlO(‘.Tl\D+—‘[\')
`
`6.6.b
`
`6.3.b
`
`CCA
`l I l I I I
`
`a4b1
`
`6gb
`
`CAA
`
`
`
`4If you have difficulties with half lambda rule.
`
`14
`
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`

`Metall (CMF)
`
`7.1 Minimum Width
`
`7.2.21 Minimum spacing
`7.2.b5 Minimum tight metal spacing
`7.3 Minimum overlap of poly COI1ta4Ct
`
`7.4 Minimum overlap of active Contact
`
`|—‘i—‘[\'JO-300
`
`
`
`7.3
`
`CP
`
`$ 7.2
`
`7.4
`
`CPG
`
`5Only allowed between miniinum width wires, otherwise use regular spacing rule.
`
`15
`
`Page 15 of 28
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`

`Vial (CVA)
`
`8.1
`
`8.2
`
`8.3
`
`8.4
`
`8.5
`
`Exact size
`
`Minimum Vial spacing
`
`Minimum overlap by metall
`
`Minimum spacing to Contact
`
`Minimum Spacing to poly or active edge
`
`2><2
`
`l\Dt\'J!—‘
`
`
`
`Page 16 of 28
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`

`Metal2 (CMS)
`
`9.1
`
`MiI1i1nu1n width
`
`9.2.a Mi11i111um spacing
`9.2.b6 Mi11imum tight metal spacing
`9.3
`Mi11iI11u1I1 overlap of Vial
`
`I—\c,0»-J‘—OJ
`
`9.2.a i
`9.2.b
`
`CMS
`
`r__CVA
`CMS I
`
`'
`'—1
`I
`;
`lCMFl
`
`l 9-1
`
`¢
`
`l
`
`9.3
`
`GOnly allowed between minimum Width Wires, otherwise use regular spacing rule.
`
`17
`
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`

`Overglass7 (CO G)
`
`10.1 Minimum bonding pad Width
`
`10.2 Minimum probe pad width
`
`Pad overlap of glass opening
`10.3
`10.4 Minimum pad spacing to unrelated 1neta128
`10.5
`Minimum pad Spacing to unrelated metall, poly,
`electrode or active
`
`pm
`
`100 X 100
`
`75 X 75
`
`6
`
`30
`
`15
`
`10.3 1
`
`101 102 >
`
`
`
`CMS
`
`10.4
`
`CMS
`
`105
`
`CMF
`
`7Rulcs in this section are in unit of pm.
`8And metal3 if triple metal used.
`
`18
`
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`

`Electrode for Capacitor (CEL - Analog Option)
`
`11.1
`
`11.2
`
`11.3
`
`11.4
`
`11.5
`
`Mi111111111'n Widtl1
`
`Mi11im11Ir1 spacing
`
`Mi11imu1'11 poly overlap
`
`Mi11im11m spacing to acttive or well edge
`
`Mininlum spacing to poly Contact
`
`11.3
`
`11
`
`1
`
`ll.2
`
`CEL
`E I
`
`CEL
`I E
`
`1. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __'
`
`ll.5
`l__________________
`
`g
`
`;
`
`I
`
`'_ _ _ _ _ _ _ , , . _ ‘J
`
`CPG
`
`__________
`
`ll.l
`
`ll.4
`
`Page 19 of 28
`
`19
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`

`Electrode for Transistor (CEL - Analog Option)
`
`12.1
`
`12.2
`
`12.3
`
`12.4
`
`12.5
`
`12.6
`
`Minimum width
`
`Minimum spacing
`
`Minimum electrode gate overlap of active
`
`Minimum spacing to active
`
`Minimum spacing or overlap of poly
`
`Minimum spacing to poly or active Contact
`
`<Lol\')r—-\N)O0mD
`
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`
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`:
`
`E
`;
`I
`51
`
`125
`
`1
`;
`ICEL
`
`:rCCE-"H
`
`12-2.
`
`CCA
`I 22
`-.C.PG
`: I
`
`$12.6
`
`I
`
`12.2
`
`_,.<_
`
`Page 20 of 28
`
`20
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`

`Electrode Contact (CCE - Analog Option)
`
`13.1
`
`13.2
`
`13.3
`
`13.4
`
`13.5
`
`Exact co11tact size
`
`Mi11im11m Contact spacing
`
`Mi11iII1uIn electrode overlap (M011 capacitor)
`.\/Iinim11111 ele(‘t1‘0de overlap (1101: 011 Capacit01')
`Mi11i111um spacing to poly or active
`
`2x2
`
`13.3
`
`1
`
`T
`
`CAA
`
`1 CMF I
`;
`
`CELE
`: I
`E
`r’
`
`5 I 5
`:
`;
`s I 2
`
`1 CEL 1
`
`CPG
`
`13.1
`
`1
`
`“
`
`1
`
`13.2
`
`1
`
`CPG
`
`13.5
`
`13 5
`
`Page 21 of 28
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`21
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`

`Via2 (CVS — Triple Metal Option)
`
`14.1
`
`Exact size
`
`14.2 Minimum spaci11g
`
`14.3 Minimum overlap by meta12
`
`14.4 Minimum spa.Ci11g to Vial
`
`2><2
`
`14.1
`
`914.4
`
`14.1
`
`1
`
`1
`
`cvs
`I I I ICVA
`
`CMT
`
`-CVA
`
`CMS
`
`Page 22 of 28
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`22
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`

`Meta13 (CMT - Triple Metal Option)
`
`15.1 Minimum Width
`
`15.2
`
`1\/Ii11i1num spacing to meta13
`
`15.3 Mi11i111um overlap of V1312
`
`H‘-
`
`15.2
`
`CMT
`
`CMT
`
`15.1
`
`15.3
`
`- CVS
`
`Page 23 of 28
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`23
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`

`NPN Bipolar Transistor (CBA - Analog Option)
`
`16.1 All active Contact
`
`16.2 Mi11imuIn select overlap of emitter Contact
`
`16.3 Mi11imuIn pbase overlap of emitter select
`
`2 X 2
`
`3
`
`2
`
`16.4 Minimum spacing between emitter select and base select 4
`
`16.5 Minimum pbase overlap of base select
`
`2
`
`16.6 Minimum select overlap of base contact
`
`16.7 Minimum nwell overlap of pbase
`
`16.8 Minimum spacing between pbase and collector active
`
`16.9
`
`.Vlinimum active overlap of collector contact
`
`16.10 Minimum nwell overlap of Collector active
`
`16.11 Minimum select overlap of collector active
`
`Page 24 of 28
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`24
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`Capacitor Well (CWC - Linear Capacitor Option)
`
`7.
`
`Mi11i1'nu11'1 width
`
`17.2
`
`17.3
`
`Mi11i1I1u111 spacing
`
`.\»Ii11i111u111 spacing to eXter11a1 active
`
`17.4 Minimum overlap of active
`
`10
`
`9
`
`5
`
`3
`
`17.1
`%—— %
`
`CAA
`
`CAA
`
`17.3
`é %
`
`17.2
`€:— %
`
`CWC
`
`CWN
`CWP
`CWC
`
`éé
`
`17.4
`
`Page 25 of 28
`
`25
`
`Page 25 of 28
`
`

`

`Linear Capacitor (Linear Capacitor Option)
`
`18.1 Minimurn Width
`
`18.2 Miniinum poly extension of active
`
`18.3 Minimum active overlap of poly
`
`18.4 Minimum poly Contact to active
`
`18.-5 Minirnum active Contact to poly
`
`Hl‘—R3C»Ql—‘C0
`
`18.2
`
`CWC
`
`- - CAA
`CCA
`
`18.3
`
`18.5
`
`18.4
`
`linear
`capacitor
`
`E
`i
`}
`E
`E
`3
`I
`CPG
`:
`1 gI I Ifi
`
`1
`
`1 8. 1
`
`Page 26 of 28
`
`26
`
`Page 26 of 28
`
`

`

`Buried Channel CCD (CCD - Analog Optiong)
`
`19.1 Minimum CCD chaiiilel active width
`
`19.2 Miiiinium CCD channel active spacing
`
`19.3 Mi11i1nun1 CCD implant overlap of Chailnel active
`
`19./-1 Minimum outside Contact to CCD implalit
`
`19.-5
`
`l\’1l1llII11lII1 select overlap of electrode (or poly)
`
`19.6 Minimum poly/ electrode Overlap \vitl1i11 Cl1a1111€l active
`19.7 Mi11i111um Contact to Cl1an11el electrode (or poly)
`
`9Not for all processes
`
`27
`
`Page 27 of 28
`
`Page 27 of 28
`
`

`

`References
`
`[1] Cadence Design Systems, Inc./Calma. GDSH S't7‘eam. Format Jlifanual, Feb. 1987. Release
`6.0, Docuinentation No.2 1397133060.
`
`J.—I. Pi, C. Pifia, and
`[2] J. Marshall, M. Gaitan, M. Zaghloul, D. Novotny, V. Tyree,
`W’. Hansford. Realizing suspended structures on chips fabricated by CMOS foundry
`processes through the MOSIS service. Technical Report NIS’l‘lR—540‘2, National Institute
`of Standards and Technology, U .S. Department of Commerce, Gaithersburg, MD, 1994.
`
`C. Mead and L. Conway. Introduction to VLSI Systems. Addison~V\/'es1ey, 1980.
`
`[4]
`
`H. E. VVeste and K. Eshraghian. Pr2'ncz’p/es of CMOS VLSI Design:
`.5pectz'v6. Addison—Wes1ey, 2nd. edition, 1993.
`
`/1 System P67“-
`
`Page 28 of 28
`
`28
`
`Page 28 of 28
`
`

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