Filed on behalf of: NVIDIA Corp.
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`Entered: December 28, 2015
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________
`
`NVIDIA CORPORATION,
`Petitioner,
`
`v.
`
`SAMSUNG ELECTRONICS COMPANY, LTD.,
`Patent Owner.
`
`______________
`
`Case IPR2015-01318
`U.S. Patent No. 8,252,675 B2
`______________
`
`
`
`
`
`
`Before JAMESON LEE, PATRICK R. SCANLON, and
`JUSTIN BUSCH, Administrative Patent Judges.
`
`PETITIONER’S REQUEST FOR REHEARING
`UNDER 37 C.F.R. § 42.71
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`
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`Entered: December 28, 2015
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________
`
`NVIDIA CORPORATION,
`Petitioner,
`
`v.
`
`SAMSUNG ELECTRONICS COMPANY, LTD.,
`Patent Owner.
`
`______________
`
`Case IPR2015-01318
`U.S. Patent No. 8,252,675 B2
`______________
`
`
`
`
`
`
`Before JAMESON LEE, PATRICK R. SCANLON, and
`JUSTIN BUSCH, Administrative Patent Judges.
`
`PETITIONER’S REQUEST FOR REHEARING
`UNDER 37 C.F.R. § 42.71
`
`
`
`IPR2015-01318
`Patent 8,252,675 B2
`I.
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`INTRODUCTION
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`Pursuant to 37 C.F.R. § 42.71(d), NVIDIA Corp. (“Petitioner”) hereby
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`requests rehearing of the Board’s Decision denying institution of Inter Partes
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`Review of U.S. Patent No. 8,252,675 (’675 patent). Paper No. 8, Dec. 7, 2015
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`(“Bd. Dec.”). The Board reviews a request for rehearing for abuse of discretion.
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`For the reasons set forth below, that standard is met and accordingly rehearing is
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`respectfully requested.
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`II. LEGAL STANDARD
`Under 37 C.F.R. § 42.71(c), “[w]hen rehearing a decision on petition, a
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`panel will review the decision for an abuse of discretion.” “An abuse of discretion
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`occurs where the decision is based on an erroneous interpretation of the law, on
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`factual findings that are not supported by substantial evidence, or represents an
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`unreasonable judgment in weighing relevant factors.” Bernard v. Dep’t of Agric.,
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`788 F.3d 1365, 1367 (Fed. Cir. 2015) (citing Star Fruits S.N.C. v. United States,
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`393 F.3d 1277, 1281 (Fed. Cir. 2005)). “A decision based on an erroneous view of
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`the law, however, invariably constitutes an abuse of discretion.” Atl. Research
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`Mktg. Sys., Inc. v. Troy, 659 F.3d 1345, 1359 (Fed. Cir. 2011) (internal citations
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`omitted).
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`III. THE BOARD ERRED IN DECIDING WHETHER YAMAKAWA IS
`ANTICIPATING
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`The sole basis for the Board’s Decision not to institute an inter partes review
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`1
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`IPR2015-01318
`Patent 8,252,675 B2
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`on all grounds and claims of the ‘675 patent was the Board’s view that Petitioner’s
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`reliance on Yamakawa’s Figure 18 for limitation 1(i) and Yamakawa’s Figures 16
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`and 17 for limitations 1(a), 1(b), 1(c), 1(d), 1(e), and 1(h) is improper for an
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`anticipation analysis. The Board did not find that Figure 18 fails to meet the
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`limitation 1(i)—rather it found that Figure 18 is a different embodiment than
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`Figures 16 and 17. The Board found “Yamakawa itself does not appear to make
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`clear what process steps are common between its embodiment of Figure 18 and its
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`embodiment of Figures 16–17, and Petitioner has not provided an adequate
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`explanation.” Bd. Dec. at 17. Petitioner respectfully requests the Board to
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`reconsider its Institution Decision in light of substantial intrinsic evidence which
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`clearly shows that Yamakawa discloses what semiconductor process steps of
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`Figures 16 and 17 are in common and that they are directly related to the process
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`steps of Figure 18.
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`“A reference anticipates a claim if it discloses the claimed invention such
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`that a skilled artisan could take its teachings in combination with his own
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`knowledge of the particular art and be in possession of the invention.” In re
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`Graves, 69 F.3d 1147, 1152 (Fed. Cir. 1995) (emphasis added) (internal quotation
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`marks and citation omitted). The Board’s Decision relies on Net MoneyIN, Inc. v.
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`VeriSign, Inc., 545 F.3d 1359, 1370 (Fed. Cir. 2008), stating that “to establish
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`anticipation, each and every element in a claim, arranged as recited in the claim,
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`2
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`IPR2015-01318
`Patent 8,252,675 B2
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`must be found in a single prior art reference.” Bd. Dec. at 9. In Net MoneyIN, the
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`Court held that an “Internet payment system” was not anticipated by a prior art
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`reference that disclosed all components of the invention in two separate payment
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`protocols, each of which contained only a subset of the claimed components. 545
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`F.3d at 1371. But, the PTAB has distinguished Net MoneyIN where a POSITA
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`would understand that two separately disclosed methods could be used in the same
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`program, even without express disclosure of their combination. Groupon, Inc. v.
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`Blue Calypso, LLC, No. CBM2013-00033, 2014 WL 7273561, at *21-22 (P.T.A.B.
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`Dec. 17, 2014); see also In re Preda, 401 F.2d 825, 826 (C.C.P.A. 1968) (“[I]t is
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`proper to take into account not only specific teachings of the reference but also the
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`inferences which one skilled in the art would reasonably be expected to draw
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`therefrom.”). In this instance, Yamakawa provides an expressed explanation that
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`would allow a POSITA to readily see how the process steps of Figures 16 and 17
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`are related to the process steps of Figure 18.
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`The Board further cites In re Arkley, 455 F.2d 586, 587 (C.C.P.A. 1972) that
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`“for a proper anticipation analysis, one may not pick and choose selectively from
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`different embodiments to satisfy the claimed invention.” Bd. Dec. at 10. But In re
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`Arkley clarifies that for anticipation, one may not pick and choose from “various
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`disclosures not directly related to each other by the teachings of the cited
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`reference.” 455 F.2d at 587 (emphasis added). However, here, Yamakawa does
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`3
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`IPR2015-01318
`Patent 8,252,675 B2
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`provide such an express disclosure of relatedness.
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`The Board focuses on Petitioner’s reliance on Figure 17(2) to meet
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`limitation 1(h) and Figure 18(4) to meet limitation 1(i). Bd. Dec. at 16.
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`Specifically, the Board notes that Figure 17(2) shows “removal of cap film or
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`buffer electrode layer 50,” while “there is no such removal in the pMOS region of
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`the device shown in Figure 18(2).” Id. For this reason, the Board found
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`“Yamakawa’s Figure 18 embodiment is not the same as the embodiment illustrated
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`in and discussed in connection with Yamakawa’s Figures 16-17.” Id. at 15 (citing
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`Prelim. Resp. at 6-7). However, the Decision failed to take into account that
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`Yamakawa expressly disclosed that the embodiments in Figure 18 and Figures 16-
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`17 are in fact related and that a POSITA would have readily recognized the same.
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`Yamakawa describes a method of manufacturing a single transistor as a so-
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`called “fourth example” in Figures 16 and 17. See Ex. 1003, Yamakawa at [0133].
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`The Board failed to recognize that Yamakawa expressly states that in the fourth
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`example shown in Figures 16-17, the cap film 50 may optionally remain in the
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`gate electrode:
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`Incidentally, while it is constituted that the cap film 50 is removed in
`the fourth example described above, the cap film 50 may be left as it
`is as a part of the gate electrode. In this case, the cap film 50 may be
`left as a work function controlling layer described in the structure of
`the device, and it suffices to select a material properly and use the
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`4
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`IPR2015-01318
`Patent 8,252,675 B2
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`material.
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`Id. at [0148] (emphases added). Immediately following is the “fifth example” in
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`Figure 18, in which Yamakawa discloses a method for fabricating two transistors
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`in a CMOS configuration—a pMOS transistor next to a nMOS transistor. Id. at
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`[0149]. And Yamakawa clearly explains that the fourth example (in Figures 16
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`and 17) is applied to the fifth example in Fig. 18:
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`Fig. 18 is a diagram representing a procedure for fabricating a
`semiconductor device of a CMOS configuration to which the fourth
`example as described above is applied and in which the gate
`electrodes of a p-type field-effect transistor and an n-type field-effect
`transistor are formed differently. A fifth example of a semiconductor
`device manufacturing method to which the present invention is
`applied will be described below with reference to the diagram. . . .
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`In this case, by the same procedure as in the fourth example, as
`shown in (1) of Fig. 18, a dummy gate 27a is provided on a gate
`insulating film 5 via a cap film 50.
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`
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`Id. at [0149-0150] (emphases added). A POSITA would have observed the cap
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`film 50 in Figure 18(4) and understood that it may not be removed by the process
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`applied in the fourth example, as provided for expressly in the specification. See
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`id. at [0148-0149].
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`Indeed, Yamakawa’s entire disclosure for fabricating a semiconductor
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`device relies on a manufacturing method and how to apply that method to six
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`5
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`IPR2015-01318
`Patent 8,252,675 B2
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`related examples. For example, Yamakawa describes a semiconductor device of a
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`field-effect transistor in Figure 1. Ex. 1003, Yamakawa at [0043]. Yamakawa
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`then describes a first and second example of a semiconductor device
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`manufacturing method in Figures 2 to 6 and 10 to 13 having “the constitution
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`described with reference to Fig. 1.” Id. at [0060, 0096]. Yamakawa then describes
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`a “third example of the manufacturing method” as “an example of modification of
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`the second example described.” Id. at [0119]. Yamakawa’s fourth example “is an
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`example of modification of the second example and the third example . . . above.”
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`Id. at [0133]. Both of Yamakawa’s fifth and sixth examples are procedures “to
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`which the fourth example . . . is applied” to build two transistors in a CMOS
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`configuration. Id. at [0149, 0157]. The fifth and sixth examples leave the cap film
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`50 in one or both gates and modify the process of the fourth example to adjust
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`work function. Id. at [0158-0159, Fig. 19(5)]. Thus a POSITA would have
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`understood Yamakawa’s examples are directly related to one another and how they
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`are applied to each other.
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`Petitioner’s declarant Dr. Jack Lee1 explained how Yamakawa applied the
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`fourth example for fabricating a single transistor to form each of two transistors
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`1 Dr. Lee’s Declaration applied the perspective of a person of ordinary skill in the
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`art at the time of the filing of the ‘675 patent. Ex. 1006, Lee Decl. at ¶ 21.
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`6
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`IPR2015-01318
`Patent 8,252,675 B2
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`shown in the fifth example (Figure 18). For example, the Lee Declaration
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`describes Yamakawa’s process for building a single transistor, using both fourth
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`and fifth examples. Ex. 1006, Lee Decl. at ¶¶ 45-50. After showing the
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`completion of the single transistor, Dr. Lee explained that “the above embodiment
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`is shown below in Fig. 18(5) as a PMOS transistor (right side), which can be
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`formed alongside an NMOS transistor (left side).” Id. at ¶ 51. Moreover, Dr. Lee
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`explained that the patterning step of the fourth example is applied to the CMOS
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`configuration of the fifth example (Figure 18) to form the second transistor:
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`Yamakawa further discloses applying the ‘fourth example,’ including
`patterning of a dummy gate electrode layer and first metal gate
`electrode layer as shown in Fig. 16(5), to a ‘procedure for fabricating
`a semiconductor device of a CMOS configuration.’
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`Id. at ¶¶ 120, 121.
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`
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`While the Board does not address limitations 1(f) and 1(g), Dr. Lee
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`understood that Yamakawa describes fabrication methods in a second and third
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`example, which Yamakawa applies to the fourth example.2 See Pet. at 31-32
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`2 Dr. Lee explains that Yamakawa discloses the process of covering the dummy
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`gate electrode and spacers with a mold layer and then removing an upper portion
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`of the mold layer to expose the dummy gate electrode in Figures 12(3) and 12(4)
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`and paragraph 110. Yamakawa expressly discloses applying this process to the
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`7
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`IPR2015-01318
`Patent 8,252,675 B2
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`(citing Ex. 1006, Lee Decl. at ¶¶ 86, 87); Ex. 1003, Yamakawa at [110, 139]. Thus
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`Yamakawa repeatedly confirms—and a POSITA would have understood—that the
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`six examples disclosed in the specification are expressly related to each other and
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`appropriately combined for anticipation purposes as set forth in Petitioner’s
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`petition.
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`Petitioner respectfully submits that based on the correct legal standard and
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`the intrinsic record of Yamakawa, the Board should institute trial as to Grounds 1
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`and 2.
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`IV. CONCLUSION
`For the reasons discussed herein, Petitioner requests rehearing and
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`institution on Grounds 1 and 2.
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`Respectfully submitted,
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`
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`By: /Robert Steinberg/
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`Dated: December 28, 2015
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`Robert Steinberg (Reg. No. 33144)
`Bob.Steinberg@lw.com
`Latham & Watkins LLP
`355 South Grand Avenue
`Los Angeles, CA 90071-1560
`213.485.1234; 213.891.8763 (Fax)
`
`Julie Holloway (Reg. No. 44769)
`Julie.Holloway@lw.com
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`fourth example, despite the presence of different layers in the gate electrode in
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`Figure 12. Ex. 1003 at [139], Fig. 12, Fig. 17.
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`8
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`IPR2015-01318
`Patent 8,252,675 B2
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`
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`Latham & Watkins LLP
`505 Montgomery Street, Suite 2000
`San Francisco, CA 94111
`415.391.0600; 415.395.8095 (Fax)
`
`Clement Naples (Reg. No. 50663)
`Clement.Naples@lw.com
`Latham & Watkins LLP
`885 Third Avenue
`New York, NY 10022-4834
`212.906.1200; 212.751.4864 (Fax)
`
`Counsel for Petitioner
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`9
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`IPR2015-01318
`Patent 8,252,675 B2
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`CERTIFICATE OF SERVICE
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`Pursuant to 37 C.F.R. § 42.6(e), I certify that on this 28th day of
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`December, 2015 a copy of Petitioner’s Request for Rehearing Under 37 C.F.R.
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`§ 42.71 was served by electronic mail on Patent Owner’s lead and backup counsel
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`at the following email addresses:
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`Naveen Modi (Reg. No. 46,224)
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`Paul Hastings LLP
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`875 15th St. N.W.
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`Washington, DC 20005
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` nVidia-Samsung-IPR@paulhastings.com
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`
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`Joseph E. Palys (Reg. No. 46,508)
`Paul Hastings LLP
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`875 15th St. N.W.
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`Washington, DC 20005
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` nVidia-Samsung-IPR@paulhastings.com
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`By: /Robert Steinberg/
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`
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`Robert Steinberg (Reg. No. 33144)
`Bob.Steinberg@lw.com
`Latham & Watkins LLP
`355 South Grand Avenue
`Los Angeles, CA 90071-1560
`213.485.1234; 213.891.8763 (Fax)
`
`Counsel for Petitioner
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