`Filed: September 10, 2015
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`Filed on behalf of: Samsung Electronics Company, Ltd.
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`By: Naveen Modi (nVidia-Samsung-IPR@paulhastings.com)
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`Joseph E. Palys (nVidia-Samsung-IPR@paulhastings.com)
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`Paul Hastings LLP
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`NVIDIA CORPORATION
`Petitioner
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`v.
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`SAMSUNG ELECTRONICS COMPANY, LTD.
`Patent Owner
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`Case IPR2015-01318
`Patent No. 8,252,675
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`Patent Owner’s Preliminary Response
`to Petition for Inter Partes Review
`of U.S. Patent No. 8,252,675
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`I.
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`II.
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`Case IPR2015-01318
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`TABLE OF CONTENTS
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`Introduction ...................................................................................................... 1
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`The Petition Fails to Show a Reasonable Likelihood that the Petitioner
`Will Prevail With Respect to the Challenged Claims ..................................... 1
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`A.
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`B.
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`C.
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`D.
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`Petitioner Has Not Shown that Yamakawa Anticipates Claims
`1-8 and 10-15 Because the Petition Improperly Combines
`Elements from Distinct Embodiments of Yamakawa ........................... 2
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`Petitioner Has Not Shown that Yamakawa Discloses the
`Limitations of Claim 9 ........................................................................ 12
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`Petitioner Has Not Shown that Yamakawa Discloses “Said
`Second and Third Metal Gate Electrode Layers Comprise[]
`Different Materials,” as Recited in Claims 6-15 ................................. 13
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`Petitioner Has Not Shown that Yamakawa Discloses the
`Features of Claims 12-14 .................................................................... 18
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`III. Conclusion ..................................................................................................... 21
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`i
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`TABLE OF AUTHORITIES
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`Case IPR2015-01318
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` Page(s)
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`Federal Cases
`Application of Arkley, 455 F.2d. 586 (CCPA 1972) .......................................... 17, 19
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`Net MoneyIN, Inc. v. VeriSign, Inc.,
`545 F.3d 1359 (Fed. Cir. 2008) ............................................................ 2, 8, 17, 19
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`Panasonic Corp., et al. v. Optical Devices, LLC,
`IPR2014-00302, Paper No. 9 (July 11, 2014) .............................................passim
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`Shopkick Inc. v. Novitaz, Inc.,
`IPR2015-00279, Paper No. 7 (May 29, 2015) .................................................... 14
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`Symantec Corp. v. RPost Communications Ltd.,
`IPR2014-00357, Paper No. 14 (July 15, 2014) ...........................................passim
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`Federal Statutes
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`35 U.S.C. § 102 .......................................................................................................... 1
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`35 U.S.C. § 103(a) ..................................................................................................... 2
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`35 U.S.C. § 313 .......................................................................................................... 1
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`35 U.S.C. § 314(a) ..................................................................................................... 1
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`Federal Rules
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`37 C.F.R. § 42.65(a) ................................................................................................. 14
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`37 C.F.R. § 42.107 ..................................................................................................... 1
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`ii
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`I.
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`Introduction
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`Case IPR2015-01318
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`Patent Owner Samsung Electronics Company, Ltd. (“Patent Owner” or
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`“Samsung”) respectfully submits this preliminary response in accordance with 35
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`U.S.C. § 313 and 37 C.F.R. § 42.107, responding to the Petition for Inter Partes
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`Review (the “Petition”) filed by nVidia Corporation (“Petitioner” or “nVidia”)
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`against Samsung’s U.S. Patent No. 8,252,675 (“the ’675 patent”). The Board
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`should not institute inter partes review because Petitioner has not met its burden of
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`demonstrating a reasonable likelihood of prevailing with respect to any of the
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`challenged ’675 patent claims.
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`For instance, Petitioner improperly relies on multiple distinct embodiments
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`in the primary reference to support its anticipation positions. In addition,
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`Petitioner fails to show how the prior art discloses or renders obvious certain
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`features. For each of these and other reasons discussed below, the Board should
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`deny the Petition and not institute an inter partes review of the ’675 patent.
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`II. The Petition Fails to Show a Reasonable Likelihood that the Petitioner
`Will Prevail With Respect to the Challenged Claims
`In order for an inter partes review to be instituted, the Petition must show a
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`“reasonable likelihood that the petitioner would prevail with respect to at least 1 of
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`the claims challenged in the petition.” 35 U.S.C. § 314(a). Here, the Petition
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`contends that claims 1-8 and 10-15 of the ’675 patent are unpatentable under
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`35 U.S.C. § 102 based on U.S. Patent Publication No. 2009/0065809 to Yamakawa
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` 1
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`(“Yamakawa”), and that claim 9 is unpatentable under 35 U.S.C. § 103(a) based on
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`Case IPR2015-01318
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`Yamakawa and U.S. Patent No. 8,039,381 to Yeh (“Yeh”). (Pet. at 3.) However,
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`as discussed below, the Petition fails to establish a reasonable likelihood that the
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`Petitioner will prevail with respect to even one claim challenged in the Petition.
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`A.
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`Petitioner Has Not Shown that Yamakawa Anticipates Claims 1-8
`and 10-15 Because the Petition Improperly Combines Elements
`from Distinct Embodiments of Yamakawa
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`Petitioner cannot establish anticipation of claims 1-8 and 10-15 because it
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`improperly combines elements from distinct embodiments in Yamakawa. See, e.g.,
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`Panasonic Corp., et al. v. Optical Devices, LLC, IPR2014-00302, Paper No. 9 at
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`13-14 (July 11, 2014) (noting that “picking and choosing” from different
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`embodiments “has no place in the making of a 102, anticipation rejection”) (citing
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`Application of Arkley, 455 F.2d 586, 587-88 (CCPA 1972)); Symantec Corp. v.
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`RPost Communications Ltd., IPR2014-00357, Paper No. 14 at 20 (July 15, 2014)
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`(explaining that Petitioner cannot rely on “alternative” embodiments in an
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`anticipation rejection); Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1371
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`(Fed. Cir. 2008) (same).
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`For example, independent claim 1 recites, inter alia,
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`patterning the dummy gate electrode layer and the buffer
`gate electrode layer in sequence to define a buffer gate
`electrode on the gate insulating layer and a dummy gate
`electrode on the buffer gate electrode; . . .
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`removing the dummy gate electrode from between the
`spacers by selectively etching back the dummy gate
`electrode using the mold layer and the spacers as an
`etching mask;
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`depositing a first metal layer onto an upper surface of the
`mold layer and onto inner sidewalls of the spacers and
`onto an upper surface of the buffer gate electrode.
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`(Ex. 1001 at 11:1-19, emphases added.) Petitioner contends that Yamakawa
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`discloses these features based on the teachings of two distinct embodiments—the
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`embodiment of Figures 16-17, and the embodiment of Figure 18. (Pet. at 28-29
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`and 32-34.) But this position that relies on distinct embodiments cannot form the
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`basis of an anticipation ground. See, e.g., Panasonic, Paper No. 9 at 13-14;
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`Symantec, Paper No. 14 at 20.
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`Specifically, Yamakawa discloses “a semiconductor device and a
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`manufacturing method thereof.” (Ex. 1003 at ¶ [0001].) Yamakawa discloses
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`several distinct methods of manufacturing a semiconductor device. For instance,
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`Yamakawa discloses with reference to Figures 2-6, a “first example of a
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`semiconductor manufacturing method.” (Id. at ¶¶ [0022]-[0026], [0060].) With
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`respect to Figures 10-13, Yamakawa discloses “a second example of a
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`semiconductor device manufacturing method.” (Id. at ¶¶ [0030]-[0033], [0096].)
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`Yamakawa further discloses “a third example of a semiconductor device
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`manufacturing method” with respect to Figures 14 and 15. (Id. at ¶¶ [0034]-
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`[0035], [0119].) Yamakawa further discloses a “fourth example” in connection
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`with Figures 16-17. (Id. at ¶¶ [0036]-[0037], [0133].) A “fifth example of a
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`semiconductor device manufacturing method,” is disclosed with respect to Figure
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`18. (Id. at ¶¶ [0038], [0149].)
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`Petitioner contends that Yamakawa discloses the claimed “patterning the
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`dummy gate electrode layer and the buffer gate electrode layer in sequence to
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`define a buffer gate electrode on the gate insulating layer and a dummy gate
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`electrode on the buffer gate electrode” based on the Figures 16-17 embodiment,
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`i.e., the “fourth example of a semiconductor device manufacturing method.” (Pet.
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`at 28-29, Ex. 1003 at ¶ [0133].) Specifically, Petitioner contends that Yamakawa
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`discloses this feature of claim 1 because Yamakawa allegedly discloses defining a
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`dummy gate electrode film 27 (alleged “dummy gate electrode”) on a cap film 50
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`(alleged “buffer gate electrode”) in Figure 16(5). (Pet. at 27-29.)
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`(Ex. 1003 at Fig. 16(5), annotated to reflect Petitioner’s positions.)
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`Petitioner further contends with respect to Figure 17(2) that Yamakawa
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`discloses “removing the dummy gate electrode from between the spacers by
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`selectively etching back the dummy gate electrode using the mold layer and the
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`spacers as an etching mask,” as recited in claim 1. (Pet. at 32-33, citing Ex. 1003
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`at Fig. 17(2).) While Figure 17(2) discloses that the dummy gate electrode 27(a) is
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`removed, Yamakawa also discloses with respect to Fig. 17(2) that the alleged
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`buffer gate electrode (cap film 50) is removed. (See Ex. 1003 at Fig. 17(2),
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`reproduced below with annotations; see also id. at ¶ [0140], explaining that “the
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`cap film 50 is selectively removed by wet etching or dry etching . . .”.)
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`(Id. at Fig. 17(2), annotated showing Petitioner’s positions.)
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`The fact that cap film 50 (alleged “buffer gate electrode”) is removed in the
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`process associated with Figure 17(2) is relevant because the very next feature of
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`claim 1 requires “depositing a first metal layer . . . onto an upper surface of the
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`buffer gate electrode” (claim feature 1[i]). (Ex. 1001 at 13-19.) Because cap film
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`50 is removed, Petitioner cannot show feature 1[i] based on Figure 17(2).
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`Therefore, Petitioner takes a leap from the embodiment of Figures 16-17 to the
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`embodiment of Figure 18 to support its position that Yamakawa allegedly discloses
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`“depositing a first metal layer . . . onto an upper surface of the buffer gate
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`electrode” (feature 1[i]). (Pet. at 33-34.) Specifically, Petitioner contends that
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`Yamakawa discloses this feature because, “[i]n Fig. 18(4), the work function
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`controlling layer 53 is deposited . . . onto an upper surface of the buffer gate
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`electrode.” (Id., citing Ex. 1006 at ¶ 91.) But, as noted above, the process
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`disclosed by Yamakawa in connection with Figure 18 is a different embodiment
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`than that of Figures 16-17. (See Ex. 1003 at ¶¶ [0036]-[0038].
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`Indeed, Petitioner recognizes the issue with relying on Figure 17(2) given
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`that the Petition incorrectly notes that Figure 17(2) includes cap film 50. This
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`incorrect representation is demonstrated in the figures reproduced below from the
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`Petition and Yamakawa:
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`(Pet. at 32)
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`(Ex. 1003 at Fig. 17(2))
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`The figure above on the left is the one presented by Petitioner on page 32 of the
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`Petition, which Petitioner represents is “Fig. 17(2).” (Pet. at 32.) But Figure 17(2)
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`of Yamakawa, which is shown above on the right, is a different figure than that
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`represented by Petitioner, and in line with Yamakawa’s disclosure that cap film 50
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`“is removed” in the process associated with Figure 17(2). (Ex. 1003 at Fig. 17(2)
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`showing dotted lines for cap film 50, ¶ [140], stating that “the cap film 50 is
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`selectively removed . . . .”) In fact, the figure presented in the Petition on page 32
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`is not Figure 17(2) as represented by Petitioner, but instead apparently is taken
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`from Figure 18(2), as demonstrated below.
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`(Pet. at 32)
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`(Ex. 1003 at Fig. 18(2), excerpt)
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`As can be seen above, Figure 18(2) (shown above on the left) is identical to the
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`figure shown on page 32 of the Petition (shown above on the right), which
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`Petitioner represents is Figure 17(2). Thus, despite Petitioner’s representation, the
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`Petition relies on the different embodiments (e.g., Figures 16-17 embodiment and
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`Figure 18 embodiment) to support its positions that Yamakawa allegedly discloses
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`the features of claim 1.
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`Such a picking and choosing of features from distinct embodiments is
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`improper and cannot establish a reasonable likelihood of prevailing with respect to
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`claim 1 because for an anticipation ground, Petitioner must demonstrate that all of
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`the claimed features are either expressly or inherently present in a single
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`embodiment. See, e.g., Panasonic, Paper No. 9 at 13-14; Symantec, IPR2014-
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`00357; Net MoneyIN, 545 F.3d at 1371.
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`Like in Panasonic and Symantec, Petitioner improperly relies on distinct
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`embodiments to allegedly show anticipation. Indeed, as explained above, Figures
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`16-17 describe “a fourth example of a semiconductor device manufacturing
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`method” and Figure 18 describes “a fifth example of a semiconductor device
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`manufacturing method.” (Id. at ¶¶ [0133], [0149].) Furthermore, the embodiment
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`of Figures 16-17 relates to the manufacture of a single semiconductor device
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`whereas Figure 18 relates to the manufacture of a CMOS device, which is the
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`combination of an nMOS and pMOS device. (Compare id. at Fig. 17(4),
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`describing a single semiconductor device, with id. at Fig. 18(5), describing a
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`pMOS and an nMOS device on the same substrate.) Indeed, the embodiment of
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`Figure 18 requires several steps that are unnecessary in the embodiment of Figures
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`16-17. For instance, in the embodiment of Figure 18, an nMOS device is created
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`that has a different gate electrode structure compared to the pMOS device. (Id. at ¶
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`[0155], describing that the nMOS device does not have the cap film 50, which is
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`present in the pMOS device; see also id. at Figure 18(5).) To accomplish this
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`different gate electrode structure, the pMOS device has to be covered in photo
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`resist 51 while the cap film 50 is etched from the nMOS device. (Id. at ¶ [0153],
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`Fig. 18(3).) These steps, which are necessitated by the presence of two different
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`devices on the same substrate, are not necessary in the embodiment of Figures 16-
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`17. Thus, the processes disclosed in connection with Figures 16-17 and 18 are
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`distinct embodiments.
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`Moreover, Petitioner provides no explanation on the relationship between
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`9
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`these two embodiments and how they somehow relate to the same process and
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`involve the same features required to support the anticipation ground presented in
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`the Petition. This is unsurprising given that Yamakawa is unambiguous in
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`describing the differences between the embodiments disclosed in the reference,
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`despite Petitioner’s attempts to blur the distinction between Figure 17(2) and
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`Figure 18(2) as addressed above. As a result, the reliance on the different
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`processes disclosed by Yamakawa to support the Petitioner’s anticipation position
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`is improper and should be rejected.
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`For at least the reasons set forth above, Petitioner has failed to establish a
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`reasonable likelihood of prevailing with respect to independent claim 1, which
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`should result in a denial of institution. Institution should also be denied with
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`respect to claims 2-5 given that they depend from claim 1, and thus suffer from the
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`same above noted deficiencies.
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`Institution should be similarly denied for claims 6-8 and claims 10-15
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`because the Petition suffers from the same above-noted deficient analysis for
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`independent claim 6. For example, claim 6 recites “removing the dummy gate
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`electrode from between the spacers by selectively etching back the dummy gate
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`electrode using the spacers as an etching mask.” (Ex. 1001 at 11:55-57.)
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`Petitioner contends that Yamakawa discloses this feature based on Figure 17(2).
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`(Pet. at 40, “Yamakawa discloses limitation [6f] for the reasons set forth above for
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`limitation [1h] of claim 1”; see also id. at 32-33, referring to Fig. 17(2).1) Claim 6
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`also recites “depositing a second metal gate electrode layer . . . onto an upper
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`surface of the patterned first metal gate electrode layer.” (Ex. 1001 at 11:58-60.)
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`Like it did for claim 1, Petitioner takes a leap from the embodiment of Figures 16-
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`17 and contends that this feature is disclosed by the embodiment of Figure 18
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`(specifically Figure 18(4)_, which is a different embodiment. (Pet. at 40,
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`“Yamakawa discloses limitation [6g] for the reasons set forth above for limitation
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`[1i] of claim 1”; see also id. at 33-34, referring to the embodiment involving Fig.
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`18(4).)2
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`Therefore, like Petitioner did for claim 1, Petitioner relies on two distinct
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`embodiments of Yamakawa to support its anticipation position for claim 6. And as
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`explained above for claim 1, such “picking and choosing” from distinct
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`embodiments is improper and cannot support the anticipation ground for claim 6.
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`See, e.g., Panasonic, Paper No. 9 at 13-14; Symantec, Paper No. 14 at 20.
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`Accordingly, for reasons similar to those discussed above with respect to claim 1,
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`1 As noted above for claim 1, Petitioner’s representation that the figure on page 32
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`of its Petition is Fig. 17(2) is not accurate.
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`2 Petitioner equates the “second metal gate electrode layer” of claim 6 with the
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`“first metal layer” of claim 1, and the “patterned first metal gate electrode layer” of
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`claim 6 with the “buffer gate electrode” of claim 1. (Pet. at 40-41.)
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`11
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`the Board should also deny institution with respect to claim 6. (See analysis above
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`regarding claim 1 and the improper reliance of different embodiments of a single
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`reference to support an anticipation position.) Institution should also be denied
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`with respect to claims 7-8 and 10-15 given that they depend from claim 6, and thus
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`suffer from the same above noted deficiencies.
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`B.
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`Petitioner Has Not Shown that Yamakawa Discloses the
`Limitations of Claim 9
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`Claim 9 depends from independent claim 6 via dependent claim 8 and thus
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`includes all of the limitations of those claims. (Ex. 1001 at 12:16, 12:22).
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`Petitioner alleges that claim 9 is obvious over Yamakawa and Yeh. (Pet. at 57-60.)
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`While Petitioner relies on Yeh for limitations of claim 9, Petitioner does not rely on
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`Yeh to disclose any of the features of independent claim 6, and does not present
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`any obviousness position relating to the features of claim 6. Instead, Petitioner
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`relies on the positions set forth in Ground 1 to allegedly show that Yamakawa by
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`itself discloses all of the features of claim 6. (Pet. at 38-44.) As a result, the same
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`deficiencies discussed above in connection with claim 6 infect the Petition’s
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`challenge of claim 9. (See supra Part II.A regarding the deficiencies in the
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`Petition’s challenge of claim 6.)
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`In particular, as explained above, Petitioner relies on different embodiments
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`of Yamakawa to allegedly show how the reference discloses all of the limitations
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`of claim 6. (See id.) But, Petitioner does not explain in its challenge of claim 6 or
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`12
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`in its challenge of claim 9 how the embodiments relating to Figures 16-17 and
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`Figure 18 are related much less how the different processes would have been
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`combined or used together in a way that shows they collectively disclose the
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`limitations of claim 6. (See Part II.A; Pet. at 38-44, 57-60.) Accordingly, for
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`reasons similar to those set forth above for claim 6, and because Petitioner fails to
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`show that a single embodiment in Yamakawa discloses the limitations of claim 6,
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`or how the multiple embodiments of Figures 16-17 and Figure 18 would have been
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`combined to disclose the limitations of claim 6, the obviousness position of
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`Ground 2 in the Petition should not be adopted and institution with respect to claim
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`9 should be denied.
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`C.
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`Petitioner Has Not Shown that Yamakawa Discloses “Said Second
`and Third Metal Gate Electrode Layers Comprise[] Different
`Materials,” as Recited in Claims 6-15
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`For claims 6-15, the Petition should be denied for the additional reason that
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`Yamakawa fails to disclose “depositing a third metal gate electrode layer onto the
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`second metal gate electrode layer to thereby fill a space between the inner
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`sidewalls of the spacers, said second and third metal gate electrode layers
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`comprising different materials,” as required by independent claim 6. (Ex. 1001 at
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`12:1-3, emphasis added.) Petitioner contends that a gate electrode material film 7a
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`corresponds to the claimed “third metal gate electrode layer” and a work function
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`controlling layer 53 corresponds to the claimed “second metal gate electrode
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`13
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`layer.” (Pet. at 41, citing Yamakawa at Fig. 18(4), ¶ [0154].)
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`Petitioner does not contend that the Figure 18 embodiment discloses that the
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`gate electrode material film 7a and the work function controlling layer 53 comprise
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`differential materials, as required by claim 6. (See Pet. at 41-42.) Instead,
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`Petitioner relies on a few theories, each of which should be rejected.
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`First, Petitioner contends that “the gate electrode film 7a and the work
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`function controlling layer are patterned differently, and a POSITA would
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`understand the figure to show that 7a and 53 comprise differential materials.” (Id.
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`at 42, citing Ex. 1006 at ¶ 113.) Petitioner does not, however, provide any
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`evidence in the Petition to support this claim. (Id.) Neither does Petitioner’s
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`alleged expert, Dr. Jack Lee, rectify this deficiency because his declaration simply
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`parrots the position in the Petition. (Compare id. at 42, with Ex. 1006 at ¶ 113.)
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`For instance, the Petition and Dr. Lee provide no explanation regarding why 7a and
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`53 comprise different materials. To the extent that the use of different illustration
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`markings are used in Figure 18(4), those simply reflect different layers, but do not
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`necessarily and unequivocally disclose that different materials are used for those
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`layers. As such, Dr. Lee’s conclusory testimony should be given no weight. See
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`37 C.F.R. § 42.65(a) (“Expert testimony that does not disclose the underlying facts
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`or data on which the opinion is based is entitled to little or no weight.”); Shopkick
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`Inc. v. Novitaz, Inc., IPR2015-00279, Paper No. 7 at 19-20 (May 29, 2015)
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`14
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`(finding that expert opinion has no probative value unless it supported by
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`persuasive facts or other evidence).
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`Second, Petitioner contends that gate electrode film 7a “may comprise a
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`variety of metals or metal compounds” such as “Ti, Ru, Hf, Ir, Co, W, Mo, La, Ni,
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`Cu, Al, a Si compound, or a N compound of these metals.” (Pet. at 42, citing Ex.
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`1003 at ¶¶ [0052], [0085].) Petitioner next contends that “the work function
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`controlling layer may be formed with ‘Ti, V, Ni, Zr, Nb, Mo, Ru, Hf, Ta, W, Pt
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`and the like or alloys including these metals,’ including metal nitride and metal
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`silicide compounds of these metals.” (Id., citing Ex. 1003 at ¶ [0054].) Because of
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`the apparent presence of a few non-overlapping materials between these two lists,
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`Petitioner contends that Yamakawa discloses that the second and third metal gate
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`electrode layers comprise different materials. (Id., citing Ex. 1006 at ¶ 113.)
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`Petitioner’s second theory should also be rejected for the following reasons.
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`Yamakawa’s ¶ [0052] discloses that “[a] metal such as Ti, Ru, Hf, Ir, Co, W,
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`Mo, La, Ni, Cu, Al, a Si compound, or a N compound of these metals . . . is used as
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`a main metallic layer forming the gate electrode layer 7.” (Ex. 1003 at ¶ [0052].)
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`But as seen from Figure 1, the gate electrode layer 7 is a single metallic layer, i.e.,
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`it is not composed of multiple layers (e.g., a gate electrode film and the work
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`function controlling layer) and is not the same as gate electrode film 7a. (Compare
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`id. at Fig. 1, with id. at Fig. 18(4).) Yamakawa further discloses that “[i]n case of a
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`laminated structure, a plurality of metallic layers may be laminated . . . .” (Id.)
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`But Yamakawa does not disclose what material each laminated layer would
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`comprise. (See id.) Just because the previously disclosed single and non-
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`laminated metallic electrode 7 can be formed from “Ti, Ru, Hf, Ir, Co, W, Mo, La,
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`Ni, Cu, Al, a Si compound, or a N compound of these metals” does not mean that
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`Yamakawa also discloses the material composition for its laminated layers if
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`electrode 7 takes the form of a laminated structure. That is, even if electrode 7 was
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`laminated into layers including gate electrode film 7a, it is unclear from Yamakawa
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`what materials would be available for gate electrode film 7a. Hence, Petitioner’s
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`statement that gate electrode film 7a “may comprise a variety of metals or metal
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`compounds” such as “Ti, Ru, Hf, Ir, Co, W, Mo, La, Ni, Cu, Al, a Si compound, or
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`a N compound of these metals” has no support in Yamakawa’s disclosure.
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`Because Petitioner has not established the composition of the gate electrode film
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`7a, the Petition fails to show that gate electrode film 7a (alleged “third metal gate
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`electrode layer”) and the work function controlling layer 53 (alleged “second metal
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`gate electrode layer”) comprise different materials.
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`Even assuming arguendo that gate electrode film 7a comprises “Ti, Ru, Hf,
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`Ir, Co, W, Mo, La, Ni, Cu, Al, a Si compound, or a N compound of these metals,”
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`which Patent Owner does not concede, and that the work function controlling layer
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`53 may be formed with “Ti, V, Ni, Zr, Nb, Mo, Ru, Hf, Ta, W, Pt and the like,”
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`Yamakawa still does not anticipate claim 6. This is because there are several
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`overlapping materials in the two groups as a result of which it is possible to pick
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`either the same or different materials for gate electrode film 7a and the work
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`function controlling layer 53. The fact that one could pick two different materials
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`given the available metals is not enough to show anticipation because such picking
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`and choosing is not proper for an anticipation rejection. Net MoneyIN, 545 F.3d at
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`1371 (explaining that it is not enough for an anticipation rejection “that the prior
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`art reference . . . includes multiple, distinct teachings that the artisan might
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`somehow combine to achieve the claimed invention”); Arkley, 455 F.2d. at 587-88.
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`Because Yamakawa does not “‘clearly and unequivocally’ direct[] those skilled in
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`the art to make” the selection suggested by Petitioner, i.e., pick two different
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`metals, Yamakawa cannot anticipate claim 6. Arkley, 455 F.2d. at 588.
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`For the above reasons, Petitioner has failed to meet its burden of establishing
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`a reasonable likelihood of prevailing with respect to independent claim 6.
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`Institution should also be denied with respect to claims 7-8 and 10-15 given that
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`they depend from claim 6, and thus suffer from the same above noted deficiencies.
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`While Petitioner proposes an obviousness ground with respect to claim 9,
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`Petitioner does not allege that Yeh remedies the above-noted deficiencies of
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`Yamakawa. (Pet. at 57-60.) Therefore, these deficiencies would also apply to the
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`proposed obviousness ground with respect to claim 9. (See also discussion above
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`regarding similar deficiencies for claim 9 in Part II.B.)
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`D.
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`Petitioner Has Not Shown that Yamakawa Discloses the Features
`of Claims 12-14
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`For claims 12-14, the Petition should be denied for the additional reason that
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`Yamakawa fails to disclose “the portion of third metal gate electrode layer of the
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`PMOS transistor and the upper metal gate electrode of the NMOS transistor
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`comprise different metals,” as required by claim 12. (Ex. 1001 at 12:48-50,
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`emphasis added.) Petitioner contends that the gate electrode film 7a corresponds to
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`the claimed “third metal electrode layer of the PMOS transistor.” (Pet. at 49.)
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`Petitioner further contends that the combination of the work function controlling
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`layer 53 and the gate electrode film 7a corresponds to the claimed “upper metal
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`gate electrode of the NMOS transistor.” (Id.) Because the gate electrode film 7a is
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`common to both the nMOS and the pMOS transistor (see, e.g., Ex. 1003 at Fig.
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`18(5), ¶ [0155]), Petitioner attempts to show the claimed feature by asserting that
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`the work function controlling layer 53 and the gate electrode film 7a comprise
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`different metals. (See Pet. at 49-50.) To make this showing, Petitioner makes
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`essentially the same argument it made with respect to claim feature 6[h].
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`(Compare id. at 49-50, citing Ex. 1003 at ¶¶ [0052], [0055], with Pet. at 41-42.)
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`That is, Petitioner contends that the gate electrode film 7a may comprise “Ti, Ru,
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`Hf, Ir, Co, W, Mo, La, Ni, Cu, Al, a Si compound, or a N compound of these
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`metals,” and that the work function controlling layer 53 may be formed with “Ti,
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`V, Ni, Zr, Nb, Mo, Ru, Hf, Ta, W, Pt and the like,” resulting in certain non-
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`overlapping or different metals (“V, Zr, Nb, Ta and Pt”) between the two layers.
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`(Id. at 49-50.)
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`But as discussed above with respect to claim 6, it is not necessary that both
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`the gate electrode film 7a and the work function controlling layer 53 have different
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`materials. (See supra Part II.C.) Yamakawa has no explicit disclosure, nor does
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`Petitioner contend otherwise, of whether two different metals should be picked for
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`the gate electrode film 7a and the work function controlling layer 53. The fact that
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`one could pick two different metals given the available metals is not enough to
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`show anticipation. Net MoneyIN, 545 F.3d at 1371; Arkley, 455 F.2d. at 587-88.
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`Because Yamakawa does not “‘clearly and unequivocally’ direct[] those skilled in
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`the art to make” the selection suggested by Petitioner, i.e., pick two different
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`metals for the claimed features, Yamakawa does not and cannot anticipate claim
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`12. Id.
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`Perhaps recognizing the deficiencies in its position, Petitioner contends that
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`Yamakawa discloses that it would have been desirable to form different metals in
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`the nMOS and pMOS transistors. (Pet. at 51, citing Ex. 1003 at ¶¶ [0053], [0055].)
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`The cited portions disclose that a different material could be used for the nMOS
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`and pMOS gate electrodes. (Ex. 1003 at ¶¶ [0055], [0056].) But such a disclosure
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`is not applicable to the embodiment of Figure 18, which Petitioner alleges
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`19
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`discloses the claimed “portion of third metal gate electrode layer of the NMOS
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`transistor” and the “upper metal gate electrode of the NMOS.” This is because,
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`under Petitioner’s analysis, the embodiment of Figure 18 has the same metal layers
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`for the nMOS and pMOS transistor. For example, the only difference in the gate
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`electrodes of the nMOS and pMOS transistors in Yamakawa is that the nMOS
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`transistor is missing the cap film 50. (Id. at Fig. 18(5), reproduced below.)
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`(Id. at Fig. 18(5).) But under Petitioner’s analysis, the cap film would be included
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`in the nMOS transistor underneath layer 53 (Pet. at 48-49, analysis for claim
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`feature 11[a].) Therefore, the nMOS and pMOS transistor gate electrodes would
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`be identical and Petitioner’s theory that it would be desirable to have different
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`metals for the nMOS and pMOS gate electrodes is incompatible with its own
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`analysis with respect to the embodiment of Figure 18.
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`Petitioner proposes yet another theory for how Yamakawa discloses the
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`features of claim 12. But this theory should also be rejected because it requires the
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`combination of two distinct embodiments—the embodiment of Figure 18 and the
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`embodiment of Figure 19 (see Pet. at 49-53). (See Ex. 1003 at ¶¶ [0038], [0039],
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`[0149], [0157], explaining that Figure 18 is a fifth example, and Figure 19 is a
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`different sixth