IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`Petition for Inter Partes Review of USP 8,252,675
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`In re Inter Partes Review of:
`U.S. Patent No. 8,252,675
`Issued: August 28, 2012
`Application No.: 12/942,763
`Filing Date: November 9, 2010
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`For: Methods of Forming CMOS Transistors with High Conductivity Gate
`Electrodes
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`FILED VIA PRPS
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`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,252,675
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`For ease of reference, Petitioner refers to this Petition as “the ’675 Petition”
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`challenging all claims of the ’675 patent.
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`I.
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`II.
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`Petition for Inter Partes Review of USP 8,252,675
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`TABLE OF CONTENTS
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`INTRODUCTION ........................................................................................... 1
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`REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW .......... 1
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`A. Grounds for Standing (37 C.F.R. § 42.104(a)) ..................................... 1
`B.
`Notice of Lead and Backup Counsel and Service Information ............. 1
`C.
`Notice of Real-Parties-in-Interest (37 C.F.R. § 42.8(b)(1)) .................. 2
`D. Notice of Related Matters (37 C.F.R. § 42.8(b)(2)) .............................. 2
`Fee for Inter Partes Review .................................................................. 2
`E.
`F.
`Proof of Service ..................................................................................... 2
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`III.
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`IDENTIFICATION OF CLAIMS BEING CHALLENGED
`(§ 42.104(B)) ................................................................................................... 2
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`IV. DESCRIPTION OF PURPORTED INVENTION .......................................... 3
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`A.
`B.
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`Technology Background ....................................................................... 3
`The ’675 Patent Disclosure ................................................................... 6
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`V.
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`LEVEL OF ORDINARY SKILL IN THE ART IN THE RELEVANT
`TIMEFRAME ................................................................................................ 12
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`VI. OVERVIEW OF THE PRIOR ART ............................................................. 12
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`A. U.S. Pub. No. 2009/0065809 (“Yamakawa”) ..................................... 13
`B.
`U.S. Patent No. 8,039,381 (“Yeh”) ..................................................... 19
`C.
`’675 Patent Prosecution History .......................................................... 22
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`VII. MOTIVATIONS TO COMBINE THE PRIOR ART REFERENCES ......... 23
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`A. Motivation To Combine Yamakawa with Yeh ................................... 23
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`VIII. CLAIM CONSTRUCTIONS ........................................................................ 26
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`IX. PRECISE REASONS FOR THE RELIEF REQUESTED ........................... 26
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`A. Ground 1: Claims 1-8 and 10-15 are anticipated by Yamakawa. ...... 26
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`Petition for Inter Partes Review of USP 8,252,675
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`Ground 2: Claim 9 is rendered obvious by Yamakawa in
`combination with Yeh. ........................................................................ 57
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`B.
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`Petition for Inter Partes Review of USP 8,252,675
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`EXHIBIT LIST
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`1001
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`1002
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`1003
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`1004
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`1005
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`1006
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`1007
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`1008
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`U.S. Patent No. 8,252,675 (the “’675 patent”)
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`File History for ’675 patent
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`U.S. Pub. No. 2009/0065809 (“Yamakawa”)
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`U.S. Patent No. 8,039,381 (“Yeh”)
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`Curriculum Vitae of Dr. Jack Lee
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`Declaration of Dr. Jack Lee in support of Petition for Inter Partes
`Review of U.S. Patent No. 8,252,675 (“Lee Decl.”)
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`Provisional App. No. 61/109,317 (“Yeh Provisional”)
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`Joint Identification of Claim Terms for Construction, Samsung
`Electronics Co. Ltd., et al. v. NVIDIA Corp. et al., 3:14-cv-00757-
`REP (E.D. Va.)
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`iii
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`I.
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`INTRODUCTION
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`Petition for Inter Partes Review of USP 8,252,675
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`On behalf of NVIDIA Corp. (“Petitioner”) and under 35 U.S.C. § 311 and
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`37 C.F.R. 42.100, inter partes review of claims 1–15 (“challenged claims”) of U.S.
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`Patent No. 8,252,675 (“’675 patent”), titled “Methods of Forming CMOS
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`Transistors with High Conductivity Gate Electrodes,” is requested. According to
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`United States Patent and Trademark Office (“Patent Office”) records, the ’675
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`patent was originally assigned to, and is currently owned by, Samsung Electronics
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`Co., Ltd. (“Patent Owner”). A copy of the ’675 patent is attached as Ex. 1001, and
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`the prosecution history is attached as Ex. 1002.
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`II. REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW
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`A. Grounds for Standing (37 C.F.R. § 42.104(a))
`Petitioner certifies that the ’675 patent is available for inter partes review
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`and that Petitioner is not barred or estopped from requesting inter partes review of
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`the challenged claims of the ’675 patent on the grounds below.
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`B. Notice of Lead and Backup Counsel and Service Information
`Under 37 C.F.R. §§ 42.8(b)(3), 42.8(b)(4), and 42.10(a), Petitioner provides
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`the following designation of Lead and Back-Up counsel.
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`LEAD COUNSEL
`Robert Steinberg (Reg. No. 33144)
`(bob.steinberg@lw.com)
`Postal & Hand-Delivery Address:
`Latham & Watkins LLP
`355 South Grand Avenue
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`BACKUP COUNSEL
`Clement Naples (Reg. No. 50663)
`Clement.Naples@lw.com
`Latham & Watkins LLP
`885 Third Avenue
`New York, NY 10022-4834
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`Petition for Inter Partes Review of USP 8,252,675
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`Los Angeles, CA 90071-1560
`T: 213-485-1234, F: 213-891-8763
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`T: 212.906.1200, F: 212.751.4864
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`Julie Holloway (Reg. No. 44769)
`Julie.Holloway@lw.com
`Latham & Watkins LLP
`505 Montgomery Street Suite 2000
`San Francisco, CA 94111
`T: 415.391.0600, F: 415.395.8095
`
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`Under 37 C.F.R. § 42.10(b), a Power of Attorney is attached.
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`C. Notice of Real-Parties-in-Interest (37 C.F.R. § 42.8(b)(1))
`The real-party-in-interest is NVIDIA Corporation. No other party exercised
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`or could have exercised control over this petition; no other party funded or directed
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`this petition. (See Office Patent Trial Practice Guide, 77 Fed. Reg. 48759–60.)
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`D. Notice of Related Matters (37 C.F.R. § 42.8(b)(2))
`Samsung Electronics Co., Ltd., et al. v. NVIDIA Corp. et al., 3:14-cv-00757-
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`REP (E.D. Va.). According to Patent Office records, no applications claim the
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`benefit of priority to the filing date of the ’675 patent.
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`E. Fee for Inter Partes Review
`The Director is authorized to charge the fee specified by 37 C.F.R.
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`§ 42.15(a) to Deposit Account No. 506269.
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`F. Proof of Service
`Proof of service of this Petition on the Patent Owner at the correspondence
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`address of record for the ’675 patent is attached.
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`III.
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`IDENTIFICATION OF CLAIMS BEING CHALLENGED
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`Petition for Inter Partes Review of USP 8,252,675
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`(§ 42.104(B))
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`Claims 1-15 of the ’675 patent (the “challenged claims”) are unpatentable in
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`view of the following prior art: (i) U.S. Pub. No. 2009/0065809 (“Yamakawa”)
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`(Ex. 1003); and (ii) U.S. Patent No. 8,039,381 (“Yeh”) (Ex. 1004).
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`Specifically, the challenged claims are invalid under 35 U.S.C. §§ 102/103
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`on the following grounds:
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`Ground 1: claims 1-8 and 10-15 are anticipated by Yamakawa.
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`Ground 2: claim 9 is rendered obvious by Yamakawa in combination with Yeh.
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`IV. DESCRIPTION OF PURPORTED INVENTION
`The ’675 patent relates generally to a method for forming the layers of a
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`metal gate electrode. Ex. 1006 (Declaration of Dr. Jack Lee in support of Petition
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`for Inter Partes Review of U.S. Patent No. 8,252,675) (“Lee Decl.”) at ¶ 41.
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`A. Technology Background
`1.
`NMOS and PMOS Transistors
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`There are two basic types of metal-oxide-semiconductor (MOS) transistors,
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`in accordance with the channel type which is induced beneath the gate electrode:
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`NMOS transistors and PMOS transistors. ’675 patent at 1:24-26. CMOS is a
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`common design technique that uses complementary and matching pairs of NMOS
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`and PMOS transistors. See id. at 2:4-8. A threshold voltage is the minimum gate-
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`to-source voltage differential required to form the channel, or induce the
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`corresponding flow of charge carriers, beneath the PMOS and NMOS transistors.
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`While conventional MOS transistors used a gate electrode formed of
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`polysilicon, the ’675 patent focused on the use of metal materials to form the MOS
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`gates. It had been known for some time that metal materials could be used to form
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`gate electrodes which provided superior electric conductivity to the polysilicon
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`material. Id. at 1:20-24. Further, the gate electrodes of the NMOS and PMOS
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`transistors may be formed of different metals so that the NMOS transistor and the
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`PMOS transistor have different threshold voltages. The operating voltages of
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`NMOS and PMOS transistors may also be different. Id. at 1:27-30, 6:24-25.
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`2. Gate-First versus Gate-Last
`MOS transistors are fabricated on a semiconductor substrate, using material
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`deposition and etching processes. Multiple layers are deposited on a substrate,
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`before the individual gates are patterned using a mask and etch-back process.
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`Various processes are used to form other basic structures on the semiconductor
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`device, such as spacers on the gates, contact holes and vias to provide
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`interconnection, field oxide layers to provide isolation between active regions,
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`diffusion regions, etc. Metal layers provide interconnection throughout the device.
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`Lee Decl. at ¶ 24.
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`Historically, MOS transistors were fabricated with the gate-first approach.
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`First, the layers of a gate electrode are formed and patterned. Spacers are formed
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`on the sides of the patterned gate stacks. The gate stack and spacers serve as a
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`mask for source and drain ion implantation on the active region of the substrate—
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`this is a self-aligning process to ensure the source and drain form just outside the
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`edges of the gate electrode. After ion implantation, a high-temperature anneal is
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`applied to activate the dopants and repair the damage done during implantation.
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`Lee Decl. at ¶ 25.
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`With a high-K metal gate stack, the gate-last process (aka the dummy gate
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`replacement gate process) is considered because the high-temperature source/drain
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`anneal step can negatively impact the long-term integrity of the gate stack. In a
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`gate-last process, first dummy gates (aka sacrificial gates) using material such as
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`polysilicon are formed through the patterning process. Just as in the gate-first
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`process, a source/drain implantation and high-temperature anneal follows using the
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`dummy gates as masks—but this time, the actual metal gate has not yet been
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`formed, and thus is not subject to the high temperature process. Instead, once
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`anneal is complete, the dummy gates are removed, forming a trench where
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`subsequent metal layers are deposited to form the actual gate electrode. The
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`advantage of this gate-last process is that the gate stacks do not suffer damage from
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`high-temperature source/drain formation processes, while still maintaining the
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`benefits of using the gate stacks for self-alignment. Lee Decl. at ¶ 26.
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`Before the ’675 patent was filed, companies had known of these particular
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`steps for replacing a dummy gate with metal layers. The ’675 patent describes
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`basic and well-known fabrication techniques for creating a PMOS and NMOS
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`transistor using the gate-last process. Lee Decl. at ¶ 28.
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`The ’675 Patent Disclosure
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`B.
`The ’675 patent describes a method for fabricating metal PMOS and NMOS
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`gate electrodes of a CMOS device. The ’675 patent relies on well-known
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`techniques of forming gates with spacers on a substrate, for example:
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`• Layers comprising the gate, such as dielectric, dummy polysilicon, or metal
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`layers are deposited using a method such as chemical vapor deposition
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`(CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD);
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`• Spacers are formed on the sidewalls of gates;
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`• Layers are planarized using chemical mechanical polishing (CMP) after a
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`fill-in layer is deposited or mold layer is formed, to expose the top of the
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`gate or a particular layer of the gate;
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`• Photo resist patterns are used to mask and selectively etch gate stacks or
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`remove dummy poly
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`Lee Decl. at ¶ 29. The fabrication steps are described in more detail below.
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`First, the initial layers for forming a dummy gate electrode are deposited on
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`a substrate 10. Starting from the bottom, a gate insulating layer 18, a buffer gate
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`electrode 20, and a dummy gate electrode 22 are formed and stacked on the
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`substrate 10, as shown in Fig. 2:
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`Id. at Fig. 2, 3:28-30. A photo-lithography process and etching process are then
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`performed to pattern dummy gate stacks, from layers 18, 20, and 22. Id. at 3:45-
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`47. In a photo-lithography process, a first photo resist pattern is formed on the
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`dummy gate electrode 22. Id. at 3:48-50. The dummy gate electrode 22, the buffer
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`gate electrode 20, and the gate insulating layer 18 are etched in succession to
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`define a gate stack according to the photo resist pattern. Id. at 3:50-53. Fig. 3
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`shows two patterned gate stacks:
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`Id. at Fig. 3.
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`Following formation of the dummy gate stacks, spacers 28 are formed on a
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`sidewall of the stacks, as shown in Fig. 6:
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`Id. at Fig. 6. Spacers are formed through a process depositing a silicon nitride
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`layer conformally on the gate stacks and substrate, through a chemical vapor
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`deposition process. Id. at 4:9-12. The silicon nitride layer is anisotropically
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`etched, so that only the spacers 28 remain on the sidewalls of the gate stacks. Id. at
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`4:14-16.
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`After the source/drain regions are formed, a mold insulating layer 32 is
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`deposited using a vapor deposition process to cover the substrate and the dummy
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`gate stacks. Id. at 4:47-49. The mold insulating layer comprises an insulating
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`material, such as silicon oxide. Id. at 4:49-50. The mold insulating layer 32 is
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`then planarized to the top of the dummy gate electrode 22, as shown in Fig. 9:
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`Id. at Fig. 9, 4:53-54. Planarization may be performed by “chemical mechanical
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`polishing (CMP) or etch-back.” Id. at 4:54-57.
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`In the first phase described above, the dummy gate stacks are formed, and
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`spacers placed along their sides. In a subsequent phase as described below, the
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`dummy gate stacks are replaced with metal layers with appropriate work functions,
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`to form the gate electrodes. The following figures show an embodiment where
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`PMOS (on the right) and NMOS (on the left) gates are formed in separate
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`processes with different layers, to vary the metal composition between the PMOS
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`and NMOS.
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` Fig. 10 shows selective removal of dummy gate electrode 22 (shown in Fig.
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`9) by forming a photo resist pattern 34 to cover the second active region, and
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`etching the dummy gate electrode 22 in a dry or wet etching process:
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`Id. at Fig. 10, 4:58-64. The photo resist pattern 34, mold layer 32, spacers 28, and
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`buffer gate electrode 20 are used as an etch mask in the etching process to remove
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`the dummy gate. Id. at 4:64-67. The removal of the dummy gate forms a trench
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`35. Id. at 4:58-60.
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`With the dummy gate 22 remaining on the left side, and a trench 35 etched
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`out on the right side, a first metal layer 36 is formed on the entire surface of the
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`substrate through a CVD or ALD process. Id. at 5:4-5.
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`Id. at Fig. 11, 5:4-5. The first metal layer may comprise titanium nitride, for
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`example. Id. at 5:5-8. When the first metal layer 36 is formed, the ‘675 patent
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`expresses a concern that an “overhang” in the metal 36 may form at the top of the
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`trench, as shown in annotated Fig. 11:
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`Id. at Fig. 11, 5:11-15. The overhang, if severe enough, would result in the
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`formation of a “void” in the trench. Id. This is more clearly illustrated in Fig. 4 of
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`U.S. Patent No. 8,039,381 (“Yeh”), cited in the prosecution history of the ‘675
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`patent for the formation of an overhang 404 and void 408:
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`(Ex. 1004, Yeh at Fig. 4, 5:1-15.) Such formations may lead to deterioration in the
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`operation characteristic of the transistor. Id. at 6:36-41.
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`To alleviate the risk of forming a void, a method of forming a second
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`dummy filler layer into the trench 50, and then planarizing the dummy filler layer
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`while removing an upper portion of the first metal layer 36 is performed,
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`represented by Figs. 12-14 in the ’675 patent. In Fig. 15, the dummy filler layers
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`have been removed, leaving the recessed first metal layer 36 in a trench 40 on the
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`right side, and a trench 43 with no metal layers on the left side:
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`Id. at Fig. 15, 5:45-49.
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`A second metal layer 42 is deposited on the entire surface to fill the trenches
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`40 and 43, as shown in Fig. 16:
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`Id. at Fig. 16, 5:63-66. The second metal 42 may comprise aluminum, tungsten,
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`titanium, or tantalum. Id. at 5:66-6:1. Because the second metal 42 fills in on top
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`of the first metal layer, it is formed without a void in the trench 40. Id. at 6:2-3.
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`Finally, the second metal layer 42 is planarized to expose the mold
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`insulating layer 32, defining PMOS gate 46 and NMOS gate 48 on the active
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`regions, as shown in Fig. 17:
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`Id. at Fig. 17, 6:4-8. Using selective processes, the PMOS and NMOS gates
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`comprise different compositions of metals.
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`V. LEVEL OF ORDINARY SKILL IN THE ART IN THE RELEVANT
`TIMEFRAME
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`For purposes of this review, a person of ordinary skill is a person with an
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`undergraduate degree in electrical engineering (or equivalent subject) with either:
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`(1)
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`three
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`to
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`four years of post-graduate experience designing
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`semiconductor devices and fabrication processes;
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`(2)
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`or a master’s degree in electrical engineering (or equivalent subject)
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`together with one to two years of post-graduate experience in
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`designing semiconductor devices and fabrication processes.
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`Lee Decl. at ¶ 19. A person of ordinary skill also would have been familiar with
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`the gate-last (or gate replacement) technique of forming metal gate electrodes. Id.
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`This description is approximate, and a higher level of education or skill might
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`make up for less experience, and vice-versa. Id.
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`VI. OVERVIEW OF THE PRIOR ART
`For the Board’s ease of reviewing the prior art references, the declarant, Dr.
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`Lee, has provided a glossary mapping terms in the ’675 patent to corresponding
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`terms used by the Yamakawa reference discussed herein. See Lee Decl. at ¶ 69.
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`A. U.S. Pub. No. 2009/0065809 (“Yamakawa”)
`Sony Corporation filed a US patent application that was published as U.S.
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`Pub. No. 2009/0065809, listing Shinya Yamakawa as an inventor and titled
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`“Semiconductor Device and Method of Manufacturing Semiconductor Memory
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`Device.” (Ex. 1003, “Yamakawa”.) Yamakawa was published on March 12,
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`2009. Yamakawa is thus prior art to the ’675 patent under 35 U.S.C. § 102(b) and
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`was not before the examiner during prosecution of the ’675 patent.
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`The ’675 patent describes a combination of steps for forming metal gate
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`electrodes, using a dummy gate replacement (known as “gate last”) process. Lee
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`Decl. ¶ 41. These steps are disclosed in Yamakawa. Yamakawa discusses an
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`inherent problem of forming a metallic gate stack first, before forming the source
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`and drain regions. Yamakawa at [0005]. In a conventional “gate-first” process,
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`the metal gate stack is created first, and a high temperature heat treatment is
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`subsequently applied for impurity activation. Id. A negative consequence of
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`forming the metal gate stack first is that the heat treatment causes the metallic
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`materials in the gate to react with the adjacent gate insulating film. Id.
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`To solve this problem, Yamakawa discloses a gate process forming the
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`metal layers of the gate electrode after forming the source and drain regions. Id. at
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`[0006]. This is known as a “gate-last” process, or a “gate-replacement” process,
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`because the actual metal gate stack is formed last. First, a dummy gate is formed
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`as a placeholder, with sidewall spacers. Id. The heat treatment for impurity
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`activation in the source/drain is applied, while the gate stack still comprises a
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`dummy material. After the heat treatment, the dummy gate is removed and
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`replaced with the actual metal gate stack, using deposition of layers. Id. Because
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`the source/drain region was previously formed, no additional high heat treatment is
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`required. Id.
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`As discussed below, Yamakawa discloses the basic steps for the gate-last
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`process, which are identical to the steps claimed in the ’675 patent. While
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`Yamakawa further adds various improvements to the process, for example forming
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`in one embodiment a slight recess in the substrate to apply stress to the channel,
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`Yamakawa provides the same conventional steps of the gate-last process as
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`disclosed in the ’675 patent. See, e.g., id. at [0005], [0018].
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`First, a gate insulating film 5 made of a high dielectric constant material is
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`formed on the surface of a semiconductor substrate 3. Id. at [0134], [0135]. A
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`metal titanium nitride layer, called a “cap film” 50 is formed on the gate insulating
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`layer by a deposition method, as shown in Fig. 16(3):
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`Id. at Fig. 16(3), [0135]. Yamakawa shows in its figures a recess 3a in the
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`substrate, an improvement to apply stress to the channel. But Yamakawa
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`recognizes that in a different embodiment, as well as in other prior art, a recess is
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`not formed and the gate insulating layer and cap layer are deposited on a planar
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`substrate surface. See id. at Figs. 2-4, 20-21.
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`Then, a dummy gate electrode layer 27 of polysilicon or amorphous silicon
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`is formed on the cap layer 50, as shown in Fig. 16(4):
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`Yamakawa at Fig. 16(4), [0136]. The dummy gate electrode layer 27, metal layer
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`cap film 50, and insulating film 5 are then patterned in sequence, by etching from
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`over the patterned hard mask layer 29, as shown in Fig. 16(5):
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`Yamakawa at Fig. 16(5), [0137].
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`Yamakawa then discloses applying a conventional method for forming
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`sidewalls on both sides of the dummy gate structure A, described step by step in an
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`earlier disclosed embodiment in Figs. 10, 11, and 12 and accompanying text [0104]
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`to [0109]. Id. at [0139] (“After the above [process of Figure 16], the process
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`described with reference to FIG. 11 and FIG. 12 is performed …”). First,
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`insulative side walls 11-1 are formed, as shown in Fig. 10(5):
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`Yamakawa at Fig. 10(5), [0104]. A second set of insulative side walls 11-2 are
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`formed on the outside of the first side walls 11-1:
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`Id. at Fig. 12(1), [0109]. As further shown in Fig. 12(1), an impurity ion
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`implantation is then performed, with a heat treatment to activate the impurity. As
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`discussed by Yamakawa, the heat treatment has no effect on the eventual metal
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`gate stack, which has not been formed yet.
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`Then, an interlayer insulating film 13 is formed over the source/drain region
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`and the dummy gate structure A, as shown in Fig. 12(3):
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`Yamakawa at Fig. 12(3), [0110]. The insulating film comprises silicon oxide, and
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`is subsequently polished by a CMP method until the dummy gate electrode 27a is
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`exposed. Yamakawa shows the resulting gate structure in Fig. 17(1), after the
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`[clarify]sidewall process has been performed to provide insulating spacers 11-1
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`and 11-2 on both sides of the dummy gate structure A:
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`Yamakawa at Fig. 17, [0139] (process described with reference to Fig. 12 is
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`performed as in the described example); see also id. at [0110], Fig. 12(4).
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`Now, the dummy gate is ready to be replaced. An etching process is used to
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`remove the dummy gate electrode 27a:
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`Yamakawa at Fig. 17(2), [0140]. The space left after the dummy gate is removed
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`is a “groove pattern 15,” forming the space for deposition of the metal gate stack.
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`Id. at [0141]. A work function controlling layer 53 is first deposited conformally
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`into the groove pattern 15, followed by deposition of a gate electrode material film
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`7a, which fills the groove pattern and covers the substrate, including the insulating
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`film and work function controlling layer 53:
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`Yamakawa at Fig. 18(4), [0154]. Finally, the gate electrode material film 7a and
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`work function controlling layer 53 are planarized via CMP, to form a metal gate
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`stack having a metal fill-in layer 7a, U-shaped cross section 53, and planar cap
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`layer 50:
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`Yamakawa at Fig. 18(5), [0155].
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`The above embodiment is shown below in annotated Fig. 18(5) as a PMOS
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`transistor (right side), which can be formed alongside an NMOS transistor (left):
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`Petition for Inter Partes Review of USP 8,252,675
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`Yamakawa at Fig. 18(5), [0149]. Yamakawa teaches that it is generally desirable
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`for NMOS and PMOS transistors to have different work function levels. Id. at
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`[0053] (“[A] difference in the work function of the gate electrode 7 between the n-
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`type and the p-type is desirably 0.3 eV or more.”). Thus, it is desirable to form
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`different metals in the NMOS and PMOS transistors, with different layers as
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`shown in Fig. 18(5). Yamakawa further teaches the use of various metals, with
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`certain metals desirable in the NMOS transistor, and other metals more desirable in
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`the PMOS transistor. Id. at [0055].
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`B. U.S. Patent No. 8,039,381 (“Yeh”)
`The ’675 patent claims in claim 9 a method of forming a gate structure using
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`a dummy structure, in which the metal layer is etched back to a height lower than
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`that of the mold layer (’675 patent at Fig. 14, 5:31-44), to minimize formation of
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`voids in a metal gate. Id. at 6:1-3. While Yamakawa does not explicitly disclose
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`these steps, these limitations are explicitly disclosed by Taiwan Semiconductor
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`Manufacturing Company, Ltd. in U.S. Patent No. 8,039,381 (“Yeh”), listing Yeh et
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`al. as inventors, titled “Semiconductor Device and Method of Manufacturing
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`Semiconductor Memory Device.” Lee Decl. at ¶ 52. Yeh was filed June 3, 2009
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`and claims priority to a provisional application filed September 12, 2008 and with
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`corrected figures on October 29, 2008 (“Yeh Provisional”) (Ex. 1007), which
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`contains the same disclosure as Yeh. Yeh is thus prior art under 35 U.S.C. §
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`102(e).
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`While Yeh does not describe the individual process steps in as much detail
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`as Yamakawa, Yeh discloses the same method for forming a semiconductor device
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`by replacing a polysilicon “dummy” gate with a metal gate electrode. Yeh at 1:19-
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`29. Like Yamakawa, Yeh also recognizes that the “gate last” process allows for
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`the formation of the gate stack to happen after high temperature processing. Id. at
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`1:24-29. Accordingly, Yeh discloses first forming a gate dielectric 110 comprising
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`a high-k material such as hafnium oxide. Id. at 3:51-58. Like Yamakawa, Yeh
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`discloses that a metal layer may be formed on the gate dielectric prior to forming
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`the dummy layer. Id. at 3:58-4:3.
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`Yeh further discloses forming a dummy gate with sidewall spacers, forming
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`the source/drain regions, covering the gate with an insulating layer, planarizing to
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`expose the dummy gate, and etching the dummy gate to form a trench. Id. at Fig.
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`9, 5:39-6:4. A work function metal layer 702 is subsequently deposited in the
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`trench on top of 110, which includes the gate dielectric and capping layer (7:19-
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`20):
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`Id. at Fig. 10. Yeh further recognized a problem in forming a metal layer in a
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`trench, wherein “the deposition of a first metal such as a metal liner and/or work
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`function metal may provide an overhang at the aperture of the trench.” Id. at 5:10-
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`12. “The subsequent deposition of metal layer 406 may form one or more voids”
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`in the trench, as shown by Yeh in Fig. 4 and denoted by 408:
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`Id. at Fig. 4, 5:14-15.
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`
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`To minimize the risk of voids, Yeh discloses a process of using a photoresist
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`layer 710 formed “over the first metal layer” 702 by a spin-coating process,
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`allowing the photoresist layer to “fill in the remainder of the trench.” Yeh at Fig.
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`11, 6:27-32. The photoresist layer, which is a dummy filler layer to be removed
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`later, fills a space between the inner sidewalls of the spacers 116 and contacts the
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`metal layer 702 as shown in Fig. 11.
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`Then, a wet etch process is used to “selectively remove portions of the metal
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`layer 702 (e.g., work function metal pull back)” as shown in Fig. 13:
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`Yeh at Fig. 13, 6:46-48. The “overhang 704 and portions 720, 722 of the metal
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`layer 702 at the aperture of the trench 302 may be removed” in an etch process.
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`Accordingly, the upper portions of the metal layer are removed from between the
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`inner sidewalls 116 and the dummy filler layer, described as a photoresist layer
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`712, to define the second metal gate electrode layer 730 having a U-shaped cross-
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`section. After removing the photoresist layer 712, well-known techniques are used
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`to form the final metal gate electrode. Id. at Fig. 15. As taught by Yeh, the
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`removal of the upper portion of conformal metal layer 730 reduces the formation
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`of voids when filling in the metal 740.
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`’675 Patent Prosecution History
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`C.
`In the prosecution history of the ’675 patent, the Patent Office did not
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`discuss or cite Yamakawa. Thus, the Examiner likely did not consider this
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`reference. While the Patent Office did discuss Yeh, the examiner found that Yeh
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`disclosed certain limitations of a draft independent claim 1: “a method of forming a
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`Petition for Inter Partes Review of USP 8,252,675
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`gate structure using a dummy structure, in which the metal layer is etched back to a
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`height lower than that of the mold layer and that this configuration provides
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`improved formation of the metal gate and minimizes/eliminates the formation of
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`voids.” Ex. 1002, ’675 Prosecution History, Jan. 19, 2012 Office Action, pp. 5-6.
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`In response to the examiner’s finding, the applicant removed those limitations from
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`draft independent claim 1. Id., Feb. 28, 2012 Amendment, p. 2. The limitations
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`presently exist in dependent claim 9 of the ’675 and are currently challenged in this
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`petition on the grounds of obviousness based on Yamakawa in combination with
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`Yeh. While the examiner already found the limitations of claim 9 disclosed by
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`Yeh in the prosecution history (Id., Jan. 19, 2012 Office Action, pp. 2-3), this
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`disclosure is explicitly discussed below.
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`In the Reasons for Allowance, the examiner merely recited the limitations of
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`the independent claims and stated “these limitations in combination with the other
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`limitations as set forth in the claims are neither taught nor suggested in the prior
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`art.” For the dependent claims, the examiner only stated that they depend from the
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`independent claims and are allowable for at least that reason. As discussed below,
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`Yamakawa and Yeh disclose this combination of limitations in the independent
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`claims and dependent claims.
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`VII. MOTIVATIONS TO COMBINE THE PRIOR ART REFERENCES
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`A. Motivation To Combine Yamakawa with Yeh
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`Same Technology
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`1.
`A person of ordinary skill in the art would have been motivated to look to
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`Yeh because both Yamakawa and Yeh are directed to forming a metal gate
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`transistor using a gate last, or gate replacement, approach. Lee Decl. at ¶ 66.
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`Yamakawa describes the semiconductor fabrication steps in more detail than Yeh,
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`but both Yamakawa and Yeh discuss the basic processes. In particular, as shown
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`above, both patents disclose forming first a gate dielectric layer on top of a
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`substrate, and a metal layer on top of the gate dielectric layer. Both patents teach
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`forming a dummy layer on top of the metal layer and gate dielectric layer, then
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`patterning the gate and fo