US008252675B2
`
`(12) United States Patent
`Lee et a].
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 8,252,675 B2
`Aug. 28,2012
`
`(54) METHODS OF FORMING CMOS
`TRANSISTORS WITH HIGH CONDUCTIVITY
`GATE ELECTRODES
`
`(75) Inventors: J ongWon Lee, HWaseong-si (KR); Boun
`Yoon, Seoul (KR); Sang Yeob Han,
`Anyang-si (KR); Chae Lyoung Kim,
`HWaseong-si (KR)
`
`(73) Assignee: Samsung Electronics Co., Ltd. (KR)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl.No.: 12/942,763
`
`(22) Filed:
`
`Nov. 9, 2010
`
`(65)
`
`(30)
`
`Prior Publication Data
`
`US 2011/0136313 A1
`
`Jun. 9, 2011
`
`Foreign Application Priority Data
`
`Dec. 8, 2009 (KR) ...................... .. 10-2009-0121108
`
`(51) Int. Cl.
`(2006.01)
`H01L 21/336
`(2006.01)
`H01L 21/44
`(2006.01)
`H01L 21/88
`(2006.01)
`H01L 21/4 763
`(52) US. Cl. ...... .. 438/592; 438/299; 438/637; 438/926;
`438/183; 257/E21.177; 257/E21.621; 257/E21.626;
`257/E21.64
`(58) Field of Classi?cation Search ................. .. 438/296
`See application ?le for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`10/2000 Liang et a1.
`6,130,123 A
`12/2000 Bai et a1.
`6,166,417 A
`
`6,265,258 B1
`6,373,111 B1
`6,492,217 B1
`
`7/2001 Liang et a1.
`4/2002 Zheng et a1.
`12/2002 Bai et a1.
`(Continued)
`
`JP
`JP
`JP
`KR
`KR
`KR
`
`FOREIGN PATENT DOCUMENTS
`2002-329794
`11/2002
`2005-197748
`7/2005
`2006-351580
`12/2006
`1020020075732 A 10/2002
`1020050073541 A
`7/2005
`1020060129959 A 12/2006
`
`OTHER PUBLICATIONS
`
`Steigerwald, Joseph M., “Chemical Mechanical Polish: The
`Enabling Technology,” 2008 IEEE, pp. 37-40.
`
`Primary Examiner * Fernando L Toledo
`Assistant Examiner * Valerie N BroWn
`(74) Attorney, Agent, or Firm * Myers Bigel Sibley &
`Sajovec, P.A.
`
`ABSTRACT
`(57)
`Provided is a method for manufacturing a MOS transistor.
`The method comprises providing a substrate having a ?rst
`active region and a second active region; forming a dummy
`gate stack on the ?rst active region and the second active
`region, the dummy gate stack comprising a gate dielectric
`layer and a dummy gate electrode; forming source/drain
`regions in the ?rst active region and the second active region
`disposed at both sides of the dummy gate stack; forming a
`mold insulating layer on the source/drain region; removing
`the dummy gate electrode on the ?rst active region to form a
`?rst trench on the mold insulating layer; forming a ?rst metal
`pattern to form a second trench at a loWer portion of the ?rst
`trench, and removing the dummy gate electrode on the second
`active region to from a third trench on the mold insulating
`layer; and forming a second metal layer in the second trench
`and the third trench to form a ?rst gate electrode on the ?rst
`active region and a second gate electrode on the second active
`region.
`
`15 Claims, 19 Drawing Sheets
`
`NVIDIA Corp.
`Exhibit 1001
`Page 001
`
`

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`US 8,252,675 B2
`Page 2
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`US. PATENT DOCUMENTS
`6,573,134 B2
`600% Maetal‘
`.
`6,620,713 B2
`9/2003 Arghavamet a1.
`6,696,333 B1
`2/2004 Zheng 6161.
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`6,790,731 B2
`9/2004 Zheng 6161.
`6,794,232 B2
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`6,806,146 B1
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`6,809,017 B2 10/2004 AIghaVaIll 6161.
`6,825,506 B2 11/2004 Chau 6161.
`6,849,509 B2
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`6,867,102 B2
`3/2005 BraSk 6161.
`6,879,009 B2
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`6,890,807 B2
`5/2005 Chau 6161.
`6,893,927 B1
`5/2005 $11611 6161.
`6,939,815 B2
`9/2005 Br6s1<6161
`6,974,764 B2 12/2005 BraSk 6161.
`6,998,686 B2
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`7,030,430 B2
`4/2006 D662y 6161.
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`5/2006 BraSk 6161.
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`7,060,568 B2
`6/2006 M612 6161.
`7,064,066 B1
`6/2006 M612 6161.
`7,074,680 B2
`7/2006 D662y 6161.
`7,078,282 B2
`7/2006 Chau 6161.
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`8/2006 D662y 6161.
`7,087,476 B2
`8/2006 M612 6161.
`7,122,870 B2 10/2006 B6m61<6161
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`7,126,199 B2 10/2006 D662y6161.
`7,129,182 B2 10/2006 BraSk 6161.
`.
`7,138,323 B2 11/2006 Kavaheros et a1.
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`7,153,784 B2 12/2006 Brask et a1.
`
`7,157,378 B2
`1/2007 Brask 6161.
`7,160,767 B2
`1/2007 Br6s1<6161
`7,160,779 B2
`1/2007 Doczy et a1.
`-
`7,166,506 B2
`1/2007 Pnnce et 31.
`7,176,075 B2
`2/2007 Chauet 61.
`7,176,090 B2
`2/2007 BraSk 6161.
`7,180,109 B2
`2/2007 Chauet 61.
`7,183,184 B2
`2/2007 Doczy et a1.
`-
`7,187,044 B2
`3/2007 Llang 6161.
`7,192,856 B2
`3/2007 Doczy et a1.
`7,193,253 B2
`3/2007 Doczyetal.
`7,208,361 B2
`4/2007 $11611 6161.
`7,220,635 B2
`5/2007 BraSk 6161.
`-
`7,271,045 B2
`9/2007 Pnnce et 31.
`7,285,829 B2 10/2007 D6y16 6161.
`7,317,231 B2
`1/2008 M612 6161.
`7,323,423 B2
`1/2008 BraSk 6161.
`7,326,599 B2
`2/2008 L66h16f61d 6161.
`7,326,656 B2
`2/2008 BraSk 6161.
`-
`7,332,439 B2
`2/2008 L1n616r16161.
`3/2008 sh6h66616161.
`7,338,847 B2
`7,354,832 B2
`4/2008 R66hm6dy 6161.
`7,355,281 B2
`4/2008 Br6s1<6161
`7,361,958 B2
`4/2008 BraSk 6161.
`7,381,608 B2
`6/2008 BraSk 6161.
`7,384,880 B2
`6/2008 BraSk 6161.
`7,387,927 B2
`6/2008 TUIkOt, Jr. 6161.
`7,390,709 B2
`6/2008 Doczy et a1.
`7,420,254 B2
`9/2008 Chauet 61.
`7,422,936 B2
`9/2008 B6ms6161.
`7,439,113 B2 10/2008 D662y6161.
`7,439,571 B2 10/2008 D662y6161.
`7,442,983 B2 10/2008 D662y 6161.
`7,449,756 B2 11/2008 M612 6161.
`,.
`-
`7,871,915 B2
`1/2011 L1m 6161. .................... .. 438/592
`8,039,381 B2 10/2011 Y6h6161.
`2002/0058374 A1* 5/2002 Kim 6161. ................... .. 438/228
`2006/0008968 A1* 1/2006 BraSk 6161. ..
`438/206
`2006/0051957 A1* 3/2006 BraSk 6161. ................. .. 438/637
`2006/0278934 A1 12/2006 N6 61161116
`g
`
`* cited by examiner
`
`NVIDIA Corp.
`Exhibit 1001
`Page 002
`
`

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`US. Patent
`
`Aug. 28, 2012
`
`Sheet 1 0f 19
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`US 8,252,675 B2
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`Fig. 1
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`Fig. 2
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`12
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`10
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`22
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`2O
`18
`12
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`1O
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`NVIDIA Corp.
`Exhibit 1001
`Page 003
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`

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`US. Patent
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`Aug. 28, 2012
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`Sheet 2 0f 19
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`US 8,252,675 B2
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`Fig. 8
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`Fig. 4
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`25
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`22
`2O 24
`18
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`12
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`NVIDIA Corp.
`Exhibit 1001
`Page 004
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`

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`US. Patent
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`Aug. 28, 2012
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`Sheet 3 0f 19
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`US 8,252,675 B2
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`Fig. 5
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`NVIDIA Corp.
`Exhibit 1001
`Page 005
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`Aug. 28, 2012
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`Sheet 4 0f 19
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`US 8,252,675 B2
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`Fig. '7
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`29
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`NVIDIA Corp.
`Exhibit 1001
`Page 006
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`US. Patent
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`Aug. 28, 2012
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`Sheet 5 0f 19
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`US 8,252,675 B2
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`NVIDIA Corp.
`Exhibit 1001
`Page 007
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`US. Patent
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`Aug. 28, 2012
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`Sheet 6 0f 19
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`US 8,252,675 B2
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`Fig. 11
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`Fig. 12
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`NVIDIA Corp.
`Exhibit 1001
`Page 008
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`US. Patent
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`Aug. 28, 2012
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`Sheet 7 0f 19
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`US 8,252,675 B2
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`Fig. 13
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`NVIDIA Corp.
`Exhibit 1001
`Page 009
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`US. Patent
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`Aug. 28, 2012
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`Sheet 8 0f 19
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`US 8,252,675 B2
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`NVIDIA Corp.
`Exhibit 1001
`Page 010
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`

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`US. Patent
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`Aug. 28, 2012
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`Sheet 9 0f 19
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`US 8,252,675 B2
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`NVIDIA Corp.
`Exhibit 1001
`Page 011
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`Aug. 28, 2012
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`Sheet 10 0f 19
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`NVIDIA Corp.
`Exhibit 1001
`Page 012
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`US. Patent
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`Aug. 28, 2012
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`Sheet 11 0f 19
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`US 8,252,675 B2
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`NVIDIA Corp.
`Exhibit 1001
`Page 013
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`Aug. 28, 2012
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`US 8,252,675 B2
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`Aug. 28, 2012
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`US 8,252,675 B2
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`Exhibit 1001
`Page 015
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`Exhibit 1001
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`NVIDIA Corp.
`Exhibit 1001
`Page 017
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`US 8,252,675 B2
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`NVIDIA Corp.
`Exhibit 1001
`Page 018
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`US 8,252,675 B2
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`NVIDIA Corp.
`Exhibit 1001
`Page 019
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`NVIDIA Corp.
`Exhibit 1001
`Page 020
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`Sheet 19 of 19
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`NVIDIA Corp.
`Exhibit 1001
`Page 021
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`

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`US 8,252,675 B2
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`1
`METHODS OF FORMING CMOS
`TRANSISTORS VVITH HIGH CONDUCTIVITY
`GATE ELECTRODES
`
`REFERENCE TO PRIORITY APPLICATION
`
`This application claims priority to Korean Patent Applica-
`tion No. 10-2009-0121 108, filed Dec. 8, 2009, tl1e contents of
`which are hereby incorporated herein by reference.
`
`FIELD OF THE INVENTION
`
`This invention relates to methods for manufacturing MOS
`transistors and, more particularly, to methods for manufac-
`turing MOS transistors having gate electrodes formed of dif-
`ferent metals.
`
`BACKGROUND OF THE INVENTION
`
`A MOS transistor is widely used as switching devices. In
`contrast to conventional MOS transistors containing a gate
`electrode which is fonned of poly silicon, a metal material
`with superior electric conductivity better than the poly silicon
`have been used as the gate electrode ofMOS transistors. MOS
`transistors are classified as n-MOS transistors orp-MOS tran-
`sistors in accordance with the chaimel type which is induced
`beneath the gate electrode. The gate electrodes of the 11-MOS
`transistor and the p-MOS transistor may be fonned of differ-
`ent metals so that the n-MOS transistor and the p-MOS tran-
`sistor have different threshold voltages.
`SUMMARY
`
`'
`
`Methods of forming insulated-gate field effect transistors
`according to embodiments of tlie invention includes fonning
`a gate insulating layer on a substrate and forming a dummy
`gate electrode on the gate insulating layer. Electrically insu-
`lating spacers are formed on sidewalls of the dummy gate
`electrode. These spacers and the dummy gate electrode are
`covered with an electrically insulating mold layer. An upper
`portion of the mold layer is then removed to expose an upper
`surface of the dummy gate electrode. The dummy gate elec-
`trode is then removed from between the spacers by selectively
`etching back the dummy gate electrode using the mold layer
`and the spacers as an etching mask. A first metal layer is
`deposited onto an upper surface of the mold layer and onto
`inner sidewalls of the spacers. A space between the inner
`sidewalls of the spacers is filled with a dummy filler layer
`(e.g., polysilicon) that contacts the first metal layer. An upper
`portion of the first metal layer is removed from between the ,
`inner sidewalls ofthe spacers and the dummy filler layer. The
`dummy filler layer is then removed from between the inner
`sidewalls of the spacers to expose the first metal layer. A
`second metal layer is then deposited onto a portion ofthe first
`metal layer extending between the inner sidewalls of the
`spacers, to thereby define a metal gate electrode containing a
`composite of the first and second metal layers.
`According to some ofthese embodiments ofthe invention,
`the step of filling a space between the inner sidewalls of the
`spacers is followed by a step of planarizing the dummy filler
`layer to expose a portion of the first metal layer on the upper
`surface of the mold layer. In addition, the step of forming a
`dummy gate electrode on the gate insulating layer may be
`preceded by fonning a buffer gate electrode containing tita-
`nium nitride or tantalum nitride on the gate insulating layer. In
`addition, the step of removing an upper portion of the first
`metal layer may include selectively etching the first metal
`
`2
`layer using the dummy filler layer and the mold layer as an
`etching mask. This first metal layer may include titanium
`nitride.
`Still further embodiments ofthe invention include methods
`of forming CMOS transistors by forming first and second
`gate insulating layers on a substrate and forming first and
`second dummy gate electrodes on the first and second gate
`insulating layers, respectively. First and second electrically
`insulating spacers are formed on sidewalls of the first and
`second dummy gate electrodes, respectively. These first and
`second spacers and the first and second dummy gate elec-
`trodes are covered with an electrically insulating mold layer.
`An upper portion of the mold layer is removed to expose an
`upper surface of the first dummy gate electrode and an upper
`surface oftlie second dummy gate electrode. The first dummy
`gate electrode is selectively removed from between the first
`spacers using a mask to prevent removal of the second
`dummy gate electrode. A first metal layer is deposited onto a11
`~ upper surface oftl1e mold layer and onto inner sidewalls ofthe
`first spacers. A space between the iimer sidewalls of the first
`spacers is filled with a dummy filler layer that contacts the
`first metal layer. An upper portion of the first metal layer is
`removed from between the inner sidewalls ofthe first spacers
`and the dummy filler layer. The dummy filler layer is removed
`from between the inner sidewalls ofthe first spacers to expose
`the first metal layer. This step is performed concurrently with
`removing the second dummy gate electrode from between
`inner sidewalls ofthe second spacers. A second metal layer is
`then deposited onto a portion ofthe first metal layer extending
`between the iimer sidewalls of the first spacers to thereby
`define a first metal gate electrode including a composite ofthe
`first and second metal layers. This step is performed concur-
`rently with depositing the second metal layer into a space
`between the inner sidewalls of the second spacers to thereby
`define a second metal gate electrode.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The accompanying drawings are included to provide a
`fiirther understanding of the inventive concept, and are incor-
`porated in and constitute a part of this specification. The
`drawings illustrate exemplary embodiments of the inventive
`, concept and, together with the description, serve to explain
`principles of the inventive concept. In the figures:
`FIGS. 1 through 17 are cross—sectional views illustrating a
`method for manufacturing a MOS transistor according to a
`first embodiment of the inventive concept; and
`FIGS. 18 through 37 are cross—sectional views illustrating
`a method for manufacturing a MOS transistor according to a
`second embodiment of the inventive concept.
`DETAILED DESCRIPTION OF TI IE
`EMBODIMENTS
`
`Exemplary embodiments of the inventive concept will be
`described be ow i11 more detail with reference to the accom-
`panying drawings. The embodiments ofthe inventive concept
`may, however, be embodied in different forms and should not
`be construed as limited to the embodiments set forth herein.
`Rather, these embodiments are provided so that this disclo-
`sure will be thorough and complete, and will fully convey the
`scope of the inventive concept to those skilled in the art.
`Hereinafter, exemplary embodiments ofthe inventive con-
`cept will be described in detail with reference to the accom-
`panying drawings.
`
`NVIDIA Corp.
`Exhibit 1001
`Page 022
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`

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`US 8,252,675 B2
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`3
`FIGS. 1 through 17 are cross—sectional views illustrating a
`method for manufacturing a MOS transistor according to a
`first embodiment of the inventive concept.
`Referring to FIG. 1, a first well and a second Well may be
`respectively formed in a first activc rcgion 14 and a sccond 5
`active region 16 which are defined by a device isolation layer
`12 on a substrate 10. The first well may be formed in an ion
`implantation process ir1 which impurities ofa first conductiv-
`ity type are injected in the substrate 10. The impurity of the
`first conductivity type may comprise a donor ion such as
`phosphorus or arsenic. For example, the impurities ofthe first
`conductivity type may be injected at an energy of about 100
`KeV—-300 KeV and a concentration of about
`l><1013
`ca/cm3~l><l016 ca/cm3. The second well may bc formed by
`an ion implantation process in which impurities of a second
`conductivity type opposite to the first conductivity type are
`injected in the substrate 10. Tl1e impurity of the seco11d con-
`ductivity type may comprise an acceptor ion such as boron.
`For example, the impurities of the second conductivity type
`may be injected at an energy of about 70 KeV~200 KeV and
`a concentration of about 1x1 0'3 ea/cm3~l x 10' 6 ea/cm3 . The
`device isolation layer 12 may be formed after forming the first
`well and thc sccond Well. The device isolation layer 12 may
`comprise silicon oxide that is formed by a plasma enhanced
`chemical vapor deposition (PECVD). The silicon oxide is
`formed iii a trench where a predetennined depth of tlie sub-
`strate 10 is removed.
`Referring to FIG. 2, a gate insulating layer 18, a buffer gate
`electrode 20 and a dummy gate electrode 22 may be stacked
`on the substrate 10. The gate insulating layer 18 may be
`formed of a high-k dielectric layer such as a hafnium oxide
`layer, a tantalum oxide layer and a silicon oxide layer. The
`gate insulating layer 18 may be formed to have thickness of
`about 30 A—-200 A by a method such as chemical vapor
`deposition (CVD), atomic layer deposition (ALD) or rapid
`thermal process (RTP). The buffer gate electrode 20 may
`comprise a titanium nitride layer or a tantalum nitride layer.
`The buffer gate electrode 20 may be formed to have thickness
`of about 20 A~50 A by a method such as CVD or ALD. The
`dummy gate electrode 22 may comprise poly silicon that is
`formed by a chemical vapor deposition.
`Referring to FIG. 3, a dummy gate stack 24 comprising the
`gate insulating layer 18, the buffer gate electrode 20 and the
`dummy gate electrode 22 may be formed on the first active
`region 14 and the second active region 16. The dummy gate
`stack 24 may be pattcrncd using a photo lithography process
`and an etching process. The photo lithography and the etching
`process may be performed as follows. Initially, a first photo
`resist pattern (not shown) may be formed on the dummy gate
`electrode 22. The dummy gate electrode 22, the buffer gate ,
`electrode 20 and the gate insulating layer 18 may be succes-
`sively etched using the first photo resist pattern as an etch
`mask.
`Referring to FIG. 4, a second photo resist pattern25 may be
`formed to cover the sccond active region 16. A lightly doped
`drain (LDD) 26 is formed using the second photo resist pat-
`tern 25 and the dummy gate electrode 22 as an ion implanta-
`tion mask. The impurities of the second conductivity type
`may be injected into the first active region 14. The impurities
`of the second conductivity type may be injected at an energy
`of about 1 KeV ~20 KeV and a concentration of about 1x10”
`ea/cm3 ~ l X l 01 6 ea/cm3 . The second photo resist pattern 25 is
`removed.
`Referring to FIG. 5, a third photo rcsist pattern 27 may be
`formed to cover the first active region 14. A LDD 26 may be
`formed in the second active region using the third photo resist
`pattern 27 and the dummy gate electrode 22 as an ion implan-
`
`4
`tation mask. Impurities of the first conductivity type may be
`injected into the second active region 1 6. The impurities ofthe
`first conductivity type may be injected at an energy of about
`5 KeV~30 KeV and a concentration of about
`l><l0l3
`ca/cm3~l><l016 ca/cm3. Thc LDDs 26 may be fomicd of the
`same depth in the first active region 14 and the second active
`region 16, and diffused to the same distant below the dummy
`gate stack 24. The photo resist pattern 27 is removed.
`Referring to FIG. 6, a spacer 28 may be formed on a
`sidewall of the dummy gate stack 24. The spacer 28 may
`comprise a silicon nitride layer which is formed by a chemical
`vapor deposition process. The spacer 28 may be formed by a
`selfalignment method. For example, a silicon nitride layer is
`formed to cover the dummy gatc stack 24, and the silicon
`nitride layer is then anisotropically etched to remain on the
`sidewall of the dummy gate stack 24.
`Referring to FIG. 7, a fourth photo resist pattern 29 may be
`formed to cover the second active region 16. A source/drain
`region 30 may be formed in the first active region using the
`fourth photo resist pattern 29, the dummy gate electrode 22
`and the spacer 28 as an ion implantation mask. The source/
`drain region 30 may comprise impurities of the second con-
`ductivity type. The impuritics ofthc sccond conductivity type
`may be injected at an energy of about 10 KeV~40 KeV and a
`concentration of about l><l0“3 ea/cm3~l><l017 ea/cm3. The
`fourth photo resist pattern 29 or1 the second active region 16 is
`removed.
`Referring to FIG. 8, a fifth photo resist pattern 31 is formed
`to cover the first active region 14. A source/drain region 30
`may be formed in the second active region 16 using the fifth
`photo resist pattern 31, the dummy gate electrode 22 and the
`spacer 28 as an ion implantation mask. The source/drain
`region 30 in the second active region 16 may comprise impu-
`rities ofthe first conductive type. For example, The impurities
`of the first conductivity type may be injected iii the second
`active region 16 at an energy of about 10 KeV~5O KeV and a
`concentration of about l><l016 ca/cm3~l><l017 ca/cm3. Thc
`source/drain regions 30 in the first active region 14 and the
`second active region may be the same depth. The photo resist
`pattern 31 may be then removed.
`Although not shown in drawings, the source/drain region
`30 may be formed by removing portions of the first active
`region 14 and the second active region 16 and filling an
`epitaxial silicon germanium with impurities of respective
`, conductivity type in the removed portions of the first active
`rcgion 14 and the second active region 16.
`Referring to FIG. 9, a mold insulating layer 32 is formed to
`cover the source/drain region 30 a11d the dummy gate stack
`24. The mold insulating layer 32 may comprise a silicon
`oxide layer. The mold insulating layer 32 may be formed in a
`low pressure chemical vapor deposition (LPCVD) process or
`plasma enhanced chemical vapor deposition (PECVD) pro-
`cess. The mold insulating layer 32 may be planarized such
`that the dummy gate electrode 22 may be formed. The pla-
`narization of the mold insulating layer 32 may be performed
`by a method such as chemical mechanical polishing (CMP) or
`etch-back.
`Referring to FIG. 10, the dummy gate electrode 22 on the
`first active region 14 may be selectively removed to form a
`first trench 35. The removing ofthe dummy gate electrode 22
`may comprise forming a sixth photo resist pattern 34 to cover
`the second active region 16 while exposing the dummy gate
`electrode 22 on the first active region 14, and etching the
`durmny gatc clcctrodc 22 in a dry or wet ctching process. The
`sixth photo resist pattern 34, the mold insulating layer 32 and
`the spacer 28 on the substrate 10 may be used as an etch mask
`while the dummy gate electrode 22 is removed. The buffer
`
`NVIDIA Corp.
`Exhibit 1001
`Page 023
`
`

`
`US 8,252,675 B2
`
`5
`gate electrode 20 may be used as an etch stop layer during the
`dummy gate electrode 22 etching. The sixth photo resist
`pattern 34 forr11ed on the second active region 16 is removed.
`Referring to FIG. 11, a first metal layer 36 may be formed
`on the entire surface of the sub stratc 10. The first metal layer
`36 may comprise a titanium nitride layer that is formed by a
`chemical vapor deposition (CVD) or an atomic layer deposi-
`tion (ALD). The first metal layer 36 may be formed of the
`same thickness on the bottom surface and the sidewall of the
`mold insulating layer 32 as well as a top surface of the mold
`insulating layer 32. If the first metal layer 36 is buried in the
`first trer1cl1 35, tl1e first metal layer 36 in tlie first trench 35
`may comprise a Void formed by overhang of the first metal
`layer 36. The void may be caused by losing conductive reli-
`ability of the first metal layer 36. Therefore, the first metal
`layer 36 may be formed of uniform thickness on the bottom
`and tl1e sidewall of the first trench 35.
`Referring to FIG. 12, a dummy filler layer 38 may be
`stacked on the first metal layer 36. The dummy filler layer 38
`may be formed of the same material as the dummy gate
`electrode 22. The dummy filler layer 38 may comprise poly
`silicon. The dummy filler 38 may be completely fill the first
`trcnch 35 on the first active region 14. The poly silicon may be
`formed by a chemical vapor deposition method. The dummy
`filler layer 38 may comprise a void in the first trench 35.
`Referring to FIG. 13, the dummy filler layer 38 may be
`planarized to expose the first metal layer 36. The planariza-
`tion of the dummy filler layer 38 may be performed by a
`chemical mechanical polishing (CMP) or an etch—back. The
`dummy filler layer 38 may remain in the first trench 35.
`Referring to FIG. 14, the first metal layer 36 on the mold
`insulating layer 32 is removed. And, an upper portion of the
`first metal layer 36 disposed between the mold insulating
`layer 32 and the dummy filler layer 38 becomes recessed. The
`removing process ofthe first 111etal layer 36 may be performed
`in a
`or wet etching method in which etching selectivity to
`the first metal layer 3 6 is two or more times greater than to the
`dummy filler layer 38 and the mold insulating layer 32. The
`first metal layer 36 may remain o11 the bottom surface and a
`lower sidewall of the first trench 35. The first metal layer 36
`may be formed symmetrically on both sidewall of the first
`trench 35. Therefore, the first metal layer 3 6 may be remained
`in the first trench 35 to form a first metal pattern with a ‘U‘
`shaped section.
`Referring to FIG. 15, the dummy filler layer 38 on the first
`active region 14 and the dummy gate electrode 22 on the
`second active region 15 may be removed to form a second
`trench 40 on the first active region 14 and a third trench 43 on
`the second active region. The dummy gate electrode 22 and
`the dummy filler layer 38 may be removed simultaneously in ,
`an etching process because the dummy gate electrode 22 and
`the dummy filler layer 38 are fomied ofpoly silicon. Thus, the
`method for manufacturing a MOS transistor according to first
`embodiment can improve or maximize the productivity.
`The first metal layer 36 may be expo scd in the second
`trench 40 on the first active region 14, and the buffer gate
`electrode 20 may be exposed in the third trench 43 on the
`second active region 16. The second trench 40 may be shal-
`lower than the third trench 43. The first metal layer 3 6 may be
`disposed on the bottom surface and the lower sidewall of the
`second trench 40. The second trench 40 and the third trench
`43 may be different from each other in thickness.
`Referring to FIG. 16, a second metal layer 42 may be
`formed on the entire surface of the substrate 10. The second
`metal layer 42 may fill the second trench 40 and the third
`trench 43. The second metal layer 42 may comprise at least
`one of aluminum, ttmgsten, titanium and tantalum that is
`
`5
`
`6
`formed by a method such as PVD or CVD. The second metal
`layer 42 may be formed without a void in the second trench 40
`or1tl1e first active region 14.
`Referring to FIG. 17, the second metal layer 42 is pla-
`narized to expose the mold insulating layer 32. A first gate
`electrode 46 and a second gate electrode 48 may be formed on
`the first active region 14 and the second active region, respec-
`tively. The first gate electrode 46 and t11e second gate elec-
`trode 48 may be extended in a vertical direction to the direc-
`tion of the source/drain regions 30 arrangement. The second
`metal layer 42 may be planarized by a method such as CMP
`or etch-back. The second metal layer 42 may be planarized to
`separate the first gate electrode 46 and the second gate elec-
`trodc 48. The first gate electrode 46 and the second gate
`electrode 48 may be formed to have top surfaces of substan-
`tially equal level. The first gate electrode 46 may comprise the
`buffer gate electrode 20, the first metal layer 36 and the
`second metal layer 42. The first gate electrode 46 may com-
`pose a p-MOS transistor on the first active region 14. The
`‘ second gate electrode 48 may comprise the buffer gate elec-
`trode 20 arid the second metal layer 42. Tl1e second gate
`electrode 48 may compose an n-MUS transistor on the second
`active region 16.
`In general, the operating voltage of the n—MOS transistor
`and the p-MOS transistor may be different from each other.
`Current of the 11-MOS transistor may be adjusted in accor-
`dance with a switching voltage. Thus, the second gate elec-
`trode 48 may comprise less than two metal layers in order to
`simplify the estimation of an electric resistance or a work
`function according to combination of the r11etal layers. The
`p-MOS transistor may be different from the n-MOS transistor
`in operating voltage. The first gate electrode 46 may comprise
`at least two metal layers because the p-MOS transistor per-
`forms a simple switching operation. For example, the oper-
`ating voltage may be lower to tl1e p-MOS transistor than to the
`n-MOS transistor. If a void is formed in the first gate electrode
`46, opcration characteristic of the p-MOS transistor may be
`deteriorated. According to the first embodiment, the first gate
`electrode 46 does not have a void to thereby prevent the
`operation characteristic of the p-MOS transistor from dete-
`rioration.
`Not shown in drawings, the mold insulating layer 32 on the
`source/drain region 30 may be removed to form a contact
`hole, and a source/drain electrode may be formed in the
`, contact hole.
`FIGS. 18 through 37 are cross-scctional views illustrating
`a method for manufacturing a MOS transistor according to a
`second embodiment of the inventive concept. Referring to
`FIG. 18, a first well and a second well may be formed in a first
`active region 14 and a second active region 16 that are defined
`by a device isolation layer 12 on a substrate 10. The first well
`may be formed by injecting impurities of a first conductivity
`type. The impurities of the first conductivity type may com-
`prise donor ions such as phosphorus or arsenic ions. The
`impurities ofthe first conductivity type may be ir1j ccted in the
`first well at an energy of about 100 KeV~300 KeV and a
`concentration of about 1x 1 0' 3 ea/cm3~l x l 0' 6 ea/cm3. The
`second well may be formed by injecting impurities ofa sec-
`ond conductivity type opposite to the first conductivity type.
`The impurities of the second conductivity type may be
`injected in the second well at an energy of about 70 KeV~200
`KeV and a concentration of about l><1013 ea/cm3~1><l0l5
`ea/cm3. The device isolation layer 12 may be formed after
`forming the first and the second wells. The device isolation
`layer 12 may comprise a silicon oxide layer that is formed in
`a trench by a PECVD method. The substrate may be removed
`at a predetermined depth to form the trench.
`
`NVIDIA Corp.
`Exhibit 1001
`Page 024
`
`

`
`US 8,252,675 B2
`
`7
`Referring to FIG. 19, a gate insulating layer 18, a buffer
`gate electrode 20 and a dummy gate electrode 22 may be
`stacked on the substrate 10. The gate insulating layer 18 may
`comprise at least one of hafnium oxide, tantahun oxide, sili-
`con oxide and other high-k dielectric layer. The gate insulat-
`ing layer 18 may be formed to have a depth ofabout 30 A~200
`A by a method such as CVD, ALD or RTP. The buffer gate
`electrode 20 may comprise a titanium nitride layer or a tan-
`talum nitride layer. The buffer gate electrode 20 may be
`formed to have a depth of about 20 A~50 A. The dummy gate
`electrode 22 may comprise poly silicon that is formed by
`CVD.
`Referring to FIG. 20, a dummy gate stack 24 may be
`formed on the first active region 14 and the second active
`region 16. The dummy gate stack 24 may comprise the gate
`insulating layer 18,
`the buffer gate electrode 20 and the
`dummy gate electrode 22. The dummy gate stack 24 may be
`patterned in a photo lithography process and an etching pro-
`cess. For example, the photo lithography process and the
`etching process may comprise forming a first photo resist
`pattern on the dummy gate electrode 22, and successively
`etching the dummy gate electrode 22, the buffer gate elec-
`trode 20 and the gate insulating layer using the first photo
`resist pattern as an etching mask.
`Referring to FIG. 21, a second p