Silicon Image, Inc.Silicon Image, Inc.
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`Silicon Image, Inc.
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`Technology
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`™
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`____________________________________________________________________________________________Revision 0.401Preliminary SiI100/101Subject to Change without Notice
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`PanelLinkPanelLink
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`Silicon Image, Inc.
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`Version 0.40October 1996DS100/101 001-002-0.40
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`NVIDIA Corp.
`Exhibit 1008
`Page 001
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`Silicon Image, Inc.Silicon Image, Inc.
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`Copyright Notice
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`This manual is to be copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, orsend/transmit any part of this documentation without the express written permission of Silicon Image, Inc..
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`Trademark Acknowledgment
`PanelLink
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`PanelLinkTM is a trademark of Silicon Image, Inc.VESA® is a registered trademark of Video Electronics Standards Association.All other trademarks are the property of their respective holders.
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`Disclaimer
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`This document is provided for technical information for the user. Silicon Image, Inc. reserves the right to modify theinformation in this document as necessary (the customer should make sure that it has the most recent data sheetversion). Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customersshould take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image,Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon suchrights.
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`____________________________________________________________________________________________Revision 0.402Preliminary SiI100/101Subject to Change without Notice
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`NVIDIA Corp.
`Exhibit 1008
`Page 002
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`Silicon Image, Inc.Silicon Image, Inc.
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`Revision History
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`Revision Date Comment
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`0.11 11/95Internal Draft0.1311/95First Draft. Added pin identification0.15 12/95Removed PixelBlaster. Added signal mapping for Bypass and 18/24/36-bit I/F mode.0.171/96Added control signal mapping description to 36-bit mode section. Added packagingdiagrams.0.181/96Added additional information for Product Summary in section 1. Added no connects(N/C) to the 101 pin description. Added further DE/Data edge description to Data CaptureLogic section 3.1. DCLK was changed to ODCK in Panel Interface Logic section 4.1.0.20 2/96Added detailed description information at beginning, replacing introduction. Changed SiI101 pin description for OVCC from input pad protection to output pad protection.0.21 3/96Added Technology after use of
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`PanelLink
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` mark.0.223/96Modified section 3.1 for latching data on the rising ‘or’ falling edge from the VGAcontroller to the SiI100 transmitter. Updated PVCC and AVCC pin description.0.305/96Added DSTN support. Added Voltage Tables in Pin Description sections. Added DF0function timing diagrams. Added Voltage Swing equation to Voltage Swing Adjustsection. Added functional description of DCK_INV and DF0 pin to Panel Interface LogicBlock subsection. Added timing diagrams to Panel Interface Logic section. Removedcolor reference in Signal Mapping section. Added AC/DC specifications.SiI100 Pin Changes:Renamed pin 33 from EXT_RES to EXT_SWING.Made pin 32 No ConnectSiI100 Pin Description Changes:Added input requirement of IDCKAdded input requirement of DEAdded polarity change requirement of Control signalsAdded voltage swing equation to EXT_SWINGAdded BYPASS mode cannot be used to drive panelsSiI101 Pin Changes:Removed EXT_SWING function and made pin 75 No ConnectChanged pin 79 from CKSEL to ZOCONTChanges pin 80 from RXCK to DCK_INVSiI101 Pin Description Changes:Added BYPASS mode cannot be used to drive panelsChanged DF0 from high to low during Blank TimeRemoved polarity description of CLT20.31 6/96Corrected RCX- and RCX+ pin assignment on page 13 to match page 15. Added more description on Impedance Matching Circuit on page 25. Moved VOL and VOH DC specification from SiI100 to SiI101 table on page 29.0.32 8/96Removed NDA Required and Confidential Information. Rephrased Jitter Filtering section.Clarified High/Low voltage for Configuration pins. Added more AC timing specifications.0.40 10/96Added ES3 Pin Changes. Added DSTN Panel support description. Removed BypassMode support. Added more functional description to SiI100 and SiI101. Added Numerical Pin Description section. Added more AC/DC Specifications
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`____________________________________________________________________________________________Revision 0.403Preliminary SiI100/101Subject to Change without Notice
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`NVIDIA Corp.
`Exhibit 1008
`Page 003
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`Silicon Image, Inc.Silicon Image, Inc.
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`(This Page Intentionally Left Blank)
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`____________________________________________________________________________________________Revision 0.404Preliminary SiI100/101Subject to Change without Notice
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`NVIDIA Corp.
`Exhibit 1008
`Page 004
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`Silicon Image, Inc.Silicon Image, Inc.
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`Table of Contents
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`Revision History............................................................................................................................................................3Table of Contents...........................................................................................................................................................5List of Figures................................................................................................................................................................7List of Tables.................................................................................................................................................................8Feature Review..............................................................................................................................................................91.0 Product Summary...................................................................................................................................................11Introduction..............................................................................................................................................................11Low Power...............................................................................................................................................................11Low EMI..................................................................................................................................................................11Design Flexibility.....................................................................................................................................................11Low Cost Cable Requirements, Long Distance Support and Fiber Optics Ready....................................................12Skew Tolerant Reliable Transmission......................................................................................................................12Input Clock Jitter Filtering.......................................................................................................................................122.0 Pin Description......................................................................................................................................................132.1 SiI100 Pin Diagram...........................................................................................................................................132.2 SiI100 Pin Description.......................................................................................................................................142.2.1 Pins Grouped by Functionality....................................................................................................................14Input Pin Description.......................................................................................................................................14Test Output Pin Description.............................................................................................................................15Synchronization Pin Description......................................................................................................................15Configuration Pin Description.........................................................................................................................15Analog Data Transmission Pin Description.....................................................................................................16Power and Ground Pin Description..................................................................................................................162.2.2 Pins Grouped in Numerical Order..............................................................................................................17Numerical Pin Description...............................................................................................................................17Numerical Pin Description (cont’d).................................................................................................................18Numerical Pin Description (cont’d).................................................................................................................192.3 SiI101 Pin Diagram...........................................................................................................................................212.4 SiI101 Pin Description.......................................................................................................................................222.4.1 Pins Grouped by Functionality....................................................................................................................22Data Output Pin Description............................................................................................................................22Test Output Pin Description.............................................................................................................................23Synchronization Pin Description......................................................................................................................23Analog Data Reception Pin Description..........................................................................................................23Configuration Pin Description.........................................................................................................................24Power and Ground Pin Description..................................................................................................................252.4.2 Pins Grouped in Numerical Order..............................................................................................................26Numerical Pin Description...............................................................................................................................26Numerical Pin Description (cont’d).................................................................................................................27Numerical Pin Description (cont’d).................................................................................................................283.0 SiI100 Functional Description...............................................................................................................................293.1 Data Capture Logic............................................................................................................................................303.2 DC-balanced Encoder........................................................................................................................................323.3 Voltage Swing Adjust........................................................................................................................................333.4 PLL Synchronization.........................................................................................................................................344.0 SiI101 Functional Description...............................................................................................................................35Interface Block to SiI100 Transmitter.................................................................................................................35Data Recovery Block...........................................................................................................................................35Channel Synchronization Block...........................................................................................................................35Decoder Block.....................................................................................................................................................36Panel Interface Logic Block.................................................................................................................................36
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`____________________________________________________________________________________________Revision 0.405Preliminary SiI100/101Subject to Change without Notice
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`NVIDIA Corp.
`Exhibit 1008
`Page 005
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`Silicon Image, Inc.Silicon Image, Inc.
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`____________________________________________________________________________________________Revision 0.406Preliminary SiI100/101Subject to Change without Notice4.1 Panel Interface Logic.........................................................................................................................................364.1.1 Color TFT Interface....................................................................................................................................364.1.2 Color DSTN Interface.................................................................................................................................384.2 Impedance Matching Circuit..............................................................................................................................404.3 PLL Synchronization.........................................................................................................................................404.4 Signal Mapping..................................................................................................................................................414.4.1 1 Pixel/Clock Mode....................................................................................................................................414.4.2 2 Pixel/Clock Mode....................................................................................................................................425.0 Electrical Specifications.........................................................................................................................................435.1 Absolute Conditions...........................................................................................................................................435.2 Normal Operating Conditions............................................................................................................................435.3 DC Specifications..............................................................................................................................................435.3.1 Differential Transmitter DC Specifications................................................................................................445.3.2 Differential Receiver DC Specifications.....................................................................................................445.4 AC Specifications..............................................................................................................................................455.4.1 SiI100 AC Specifications............................................................................................................................465.4.2 SiI101 AC Specifications............................................................................................................................465.5 Timing Diagrams...............................................................................................................................................475.5.1 Input Timing...............................................................................................................................................485.5.2 Output Timing.............................................................................................................................................506.0 Package Dimensions..............................................................................................................................................536.1 SiI100 Package Dimensions...............................................................................................................................536.2 SiI101 Package Dimensions...............................................................................................................................54
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`NVIDIA Corp.
`Exhibit 1008
`Page 006
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`Silicon Image, Inc.Silicon Image, Inc.
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`List of Figures
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`Figure 1. PanelLink System Block Diagram..................................................................................................................9Figure 2. SiI100 Pin Out..............................................................................................................................................13Figure 3. SiI101 Pin Out..............................................................................................................................................21Figure 4. SiI100 Functional Block Diagram................................................................................................................29Figure 5. Horizontal Input Timing...............................................................................................................................30Figure 6. Vertical Input Timing...................................................................................................................................30Figure 7. Input Data Timing with Respect to IDCK....................................................................................................30Figure 8. Control Signal Timing with Respect to IDCK..............................................................................................31Figure 9. Control Signals with Respect to DE Timing.................................................................................................31Figure 10. SiI100 Transition Minimization Timing Diagram......................................................................................32Figure 11. VSYNC, HSYNC, and CLT[3:0] Sampling...............................................................................................32Figure 12. Low Voltage Differential Voltage Swing Adjust........................................................................................33Figure 13. Single Ended Low Voltage Differential Signal Adjustment.......................................................................34Figure 14. PLL_SYNC Timing with SYNC_CONT tied HIGH (Phase 1)..................................................................34Figure 15. PLL_SYNC Timing with SYNC_CONT tied LOW (Phase 2)...................................................................34Figure 16. SiI101 Functional Block Diagram..............................................................................................................35Figure 17. 1 Pixel/Clock Timing for Color TFT Panel with OCK_INV = Low..........................................................36Figure 18. 1 Pixel/Clock Timing for Color TFT Panels with OCK_INV = High........................................................37Figure 19. 2 Pixel/Clock Timing for Color TFT Panels with OCK_INV = Low.........................................................37Figure 20. 2 Pixel/Clock Timing for Color TFT Panels with OCK_INV = High........................................................37Figure 21. 1 Pixel/Clock ODCK Timing with DFO Low and OCK_INV Low for Color TFT Panels........................38Figure 22. 1 Pixel/Clock ODCK Timing with DFO Low and OCK_INV High for Color TFT Panels.......................38Figure 23. ODCK Timing with DFO High, PIXS Low, and OCK_INV Low for Color DSTN Panels.......................38Figure 24. ODCK Timing with DFO High, PIXS Low, and OCK_INV High.............................................................38Figure 25. ODCK Timing with DFO High, PIXS High, and OCK_INV Low for Color DSTN Panels......................39Figure 26. ODCK Timing with DFO High, PIXS High, and OCK_INV High for Color DSTN Panels......................39Figure 27. SiI101 Termination Resistance...................................................................................................................40Figure 28. Transmitter Small Signal Transition Times................................................................................................47Figure 29. Receiver Digital Output Transition Times..................................................................................................47Figure 30. Transmitter/Receiver Clock Cycle/High/Low Times..................................................................................47Figure 31. Channel-to-Channel Skew Timing..............................................................................................................47Figure 32. Input Data Setup/Hold Times to IDCK of SiI100......................................................................................48Figure 33. DE, VSYNC, HSYNC, and CLT[3:0] Setup/Hold Times to IDCK of SiI100...........................................48Figure 34. VSYNC, HSYNC, and CLT[3:0] Delay Times from DE of SiI100..........................................................48Figure 35. DE High/Low Times of SiI100...................................................................................................................48Figure 36. PLL_SYNC Timing of SiI100 with SYNC_CONT = 1.............................................................................48Figure 37. PLL_SYNC Timing of SiI100 with SYNC_CONT = 0.............................................................................48Figure 38. Output Signals Disabled/Enabled Timing from PD Active/Inactive from SiI100......................................49Figure 39. Differential Clock Delay from IDCK.........................................................................................................49Figure 40. Output Data Delay from ODCK of SiI101.................................................................................................50Figure 41. Output DE Delay from ODCK of SiI101...................................................................................................50Figure 42. Output VSYNC, HSYNC, and CLT[3:0] Delay from ODCK of SiI101....................................................50Figure 43. Output Signals Disabled/Enabled Timing from PD Active/Inactive of SiI101...........................................50Figure 44. Divide by 2 ODCK Delay Timing from Internal ODCK............................................................................51Figure 45. Divide by 4 ODCK Delay Timing from Internal ODCK............................................................................51Figure 46. ODCK Delay from Differential Clock Input..............................................................................................51Figure 47. 64 Pin TQFP Package Dimensions.............................................................................................................53Figure 48. 80 Pin TQFP Package Dimensions.............................................................................................................54
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`____________________________________________________________________________________________Revision 0.407Preliminary SiI100/101Subject to Change without Notice
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`NVIDIA Corp.
`Exhibit 1008
`Page 007
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`Silicon Image, Inc.Silicon Image, Inc.
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`List of Tables
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`Table 1. State of Output Pins in Power Down Mode of SiI100...................................................................................15Table 2. Transmitter Voltage Table.............................................................................................................................16Table 3. State of Output Pins in Power Down Mode of SiI101...................................................................................24Table 4. Color TFT or Color DSTN Panel Support Configuration..............................................................................24Table 5. Receiver Voltage Table.................................................................................................................................25Table 6. Theoretical Low Voltage Single Ended Differential Swing Level Relative to REXT_SWING............................33Table 7. Color TFT or Color DSTN Panel Support Configuration..............................................................................36Table 8. 1 Pixel/Clock Mode Data Mapping from SiI100 to SiI101...........................................................................41Table 9. SiI100 1 Pixel/Clock Input to SiI101 2 Pixel/Clock Output Data Mapping..................................................42Table 10. Absolute Conditions....................................................................................................................................43Table 11. Normal Operating Conditions......................................................................................................................43Table 12. DC Specifications........................................................................................................................................43Table 13. SiI100 Transmitter DC Specifications.........................................................................................................44Table 14. SiI101 Receiver DC Specifications.............................................................................................................44Table 15. AC Specifications........................................................................................................................................45Table 16. SiI100 AC Specifications.............................................................................................................................46Table 17. SiI101 AC Specifications.............................................................................................................................46
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`____________________________________________________________________________________________Revision 0.408Preliminary SiI100/101Subject to Change without Notice
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`NVIDIA Corp.
`Exhibit 1008
`Page 008
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`Silicon Image, Inc.Silicon Image, Inc.
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`Feature Review
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`• High Speed PLL
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`• High Speed Low EMI Operation
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`• Full Color High Resolution Display
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`Support up to XGA (up to 1024x768) color TFT and color DSTN panels at up to 65 MHz at 3.3V,therefore allowing 60 Hz refresh rate with VESA compatible timing.
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`• High Integration
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`Three low-voltage differential data links to transfer both data and embedded control signals and onededicated low-voltage differential clock link.
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`• Reliable Data Reception
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`• Flexible panel interface
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`• Low Power
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`• Low Pin-Count Packages
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`80-pin TQFP - SiI101Data (24)DEControls (6)Clock(max. 65MHzmin. 25MHz)Flat PanelGraphics/VideoControllerDataCapture,Encoder,SerializerPLLLow Voltage Differential SignalsData3 PairsClock1 PairData (24/36)DEControls (6)Clock(max. 65MHzmin. 25MHz)PanelControlASICDataRecovery,Sync,DecoderPLLImpedanceControl640x480 - 1024x768TFT or DSTNLCD PanelVoltageSwingSiI100SiI101Figure 1. PanelLink System Block Diagram
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`____________________________________________________________________________________________Revision 0.409Preliminary SiI100/101Subject to Change without Notice
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`NVIDIA Corp.
`Exhibit 1008
`Page 009
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`Filters inherent reference input clock jitter to the internal PLL clock jitter.
`Three low-swing differential data links capable of transferring up to 195MBytes/sec.
`Adjustable internal impedance matching to minimize cable reflections.
`Adjustable internal voltage swing on low voltage differential outputs.
`Proprietary transition minimization to reduce high frequency signal edge rates.
`Support up to 24-bit/pixel panels (up to 16.7M color) in 1-pixel/clock mode.
`Support up to 18-bit/pixel panels (up to two 18-bit/pixel 36-bit interface) in 2-pixel/clock mode.
`Direct interface to various Flat Panel Graphics/Video Controllers on the market.
`Integrated low power PLL with no external components required.
`DC-balanced encoder and decoder for reliable data transmission and fiber-optic ready.
`Integrated adjustable termination resistors for impedance matching.
`High speed data Oversampling to minimize effects of jitter and signal skew.
`Phase, Byte, and 1-cycle Inter-channel synchronization to minimize effects of signal and cable skew.
`Only frequency information of received clock is used, eliminating effect of clock to data skew.
`PLL synchronization signal used to synchronize both transmitter and receiver PLL clocks.
`SiI101 has up to 24-bit (1 pixel/clock) or up to 36-bit (2 pixels/clock) panel interface.
`Up to 6 control signals are supported in addition to the Display Enable signal.
`Free running output clock or clock low during “Blank Time” for TFT and DSTN panel support.
`Normal clock output or inverted clock output.
`Output clock can be divided by 1, 2, or 4 for low frequency DSTN panel clock support.
`3.3V +/-5% core, analog transmitter/receiver block, and PLL voltage operation.
`Low-voltage swing differential transmitter/receiver.
`Low power / low cost CMOS technology.
`Powerdown mode.
`64-pin TQFP - SiI100
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`Silicon Image, Inc.Silicon Image, Inc.
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`____________________________________________________________________________________________Revision 0.4010Preliminary SiI100/101Subject to Change without Notice
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`NVIDIA Corp.
`Exhibit 1008
`Page 010
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`Silicon Image, Inc.Silicon Image, Inc.
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`1.0 Product Summary
`Introduction
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`The SiI100 and SiI101 are High Speed Digital Video/Graphics Interconnect devices capable of supporting up to truecolor XGA TFT and DSTN LCD panels. The transmitter (SiI100) takes parallel video/graphics data from the hostLCD graphics controller and transmits it serially at high speed to the receiver (SiI101).
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`These devices are based onSilicon Image’s
`™ Technology that enables adjustable low voltage, high speed, serial, DC-balanced, transition minimized, differential data transmission. This in turn reduces system cost, minimizes boardspace requirements, reduces line count, allows driving cables of various types and lengths, and most importantly,lowers EMI.
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`Technologyaccomplishes this by operating at 3.3V and reducing capacitive load drive requirements from the graphics controllerto the LCD panel. In addition,
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`Technology provides several power reduction features:1. Transition minimization to reduce the number of high frequency edges transmitted.2. Low frequency PLL for low power requirements.3. Power down mode for deep sleep mode.4. Programmable Interface voltage levels (3.3V or 5V) to match voltage levels of the interface to thegraphics and flat panel ASIC controllers, while keeping the core at 3.3V.5. The SiI101 has the option to output 2 pixels per clock reducing clock speeds and power consumption.
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`Low EMI
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`fundamental
`Fundamental techniques
`Fundamental
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`Advanced techniques
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` techniques for lowering EMI include reduced voltage levels of transmitted data and highspeed serial digital differential data transmission. Unfortunately, since the data is serially transmitted athigh speeds without encoding, the EMI can actually increase since signal edge rates are not minimized.To prevent this from occurring, advanced techniques are required.
`Technology is adjustable to overcome noise limitations ofcable/connector systems. The lower the cable/connector noise level, the lower the voltage swingrequired, resulting in lower EMI. Therefore, the voltage swing can be user adjustable for the cablelength and noise of the system.2. To help suppress noisy reflections in the high speed cable/connector system,
`Technologyprovides on-chip termination resistors on the receiver to reduce transmission