VESA®
`
`Video Electronics Standards Association
`
`2150 North First Street, Suite 440
`San Jose, CA 95131-2029
`
`PLUG and DISPLAY STANDARD
`
`Phone : (408) 435-0333
`Fax : (408) 435-8225
`
`VESA PLUG and DISPLAY (P&D )
`STANDARD
`
`Version 1
`Revision 0
`Revision Date : June 11 th, 1997
`
`Purpose
`This standard is intended to provide an industry standard digital interface for display devices.
`
`Summary
`This standard defines a new video interface which provides both digital and analogue
`interfaces for video data, together with serial bus options.
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 1 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 001
`
`

`
` VESA - The Video Electronics Standards Association
`Plug and Display Standard
`
`Intellectual Property
`©Copyright 1997 - Video Electronics Standards Association. All rights reserved.
`
`While every precaution has been taken in the preparation of this standard, the Video Electronics Standards
`Association and its contributors assume no responsibility for errors or omissions, and make no warranties,
`expressed or implied, of functionality or suitability for any purpose.
`
`Trademarks
`All trademarks used within this document are the property of their respective owners.
`
`• VESA, DDC, EVC, EDID and P&D are trademarks of the Video Electronics Standards Association.
`• PanelLink and TMDS are trademarks of Silicon Image Inc.
`• MicroCross is a trademark of Molex Inc.
`• I2C is a trademark of Philips
`Patents
`VESA proposal and standards documents are adopted by the Video Electronics Standards Association without
`regard to whether their adoption may involve patents on articles, materials, or processes. Such adoption does
`not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
`the proposal or standards document.
`
`Support for this Standard
`Clarifications and application notes to support this standard may be written. To obtain the latest standard and
`any support documentation, contact VESA.
`
`If you have a product which incorporates P&D, you should ask the company that manufactured your product
`for assistance. If you are a manufacturer, VESA can assist you with any clarification you may require. All
`comments or error reports should be submitted in writing to VESA using one of following methods:
`
`• Fax
`
`+1 - 408 - 435 - 8225, direct this note to Technical support at VESA
`
` e-mail
`
` Mail to
`
`support@vesa.org
`
`Technical Support
`Video Electronics Standards Association,
`2150 North First Street, Suite 440,
`San Jose, CA 95131-2029
`
` •
`
` •
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 2 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 002
`
`

`
`Acknowledgments
`
`The many active participants on the VESA Plug and Display Committee all contributed to this
`standard through their experience and enthusiasm either in the initial stage or by participation in the
`committee meetings. Thanks to the following individuals and companies in particular:
`
`Name
`M Blashe
`B Burge
`D Chambers
`M Gardner
`C Grant
` R Heidick
`H Hernandez
`G Hewlett
`J Hosek
`S Kerigan
`L Kopp
`K Kwiat
`G Manchester
`M Marantic
`I Miller
`J Miseli
`B Myers
`E Myers
`J Roberts
`E Rodriguez-Crespo
`B Russell
`J Scheussler
`S Slinker
`O Tomita
`W Uenishi
`H van der Ven
`N Vidovich
`R Visser
`
`Company
`Toshiba
`Chips and Technologies
`JAE
`Molex
`Madison Cable
`3M
`3M
`Texas Instruments
`NEC Technologies
`IBM UK
`AMP
`Hirose Electric
`Molex
`Hitachi
`IBM UK
`Sun Microsystems
`Hewlett Packard
`AMP
`NIST
`Mitsubishi
`Canon
`National Semiconductor
`Silicon Image
`Toshiba
`Hosiden
`Panasonic
`Hitachi
`Philips MM Centre
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 3 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 003
`
`

`
`Terms and Abbreviations
`
`Term / Abbreviation
`ASIC
`CRT
`DDC
`DDC1
`DDC2
`
`DDC2B
`DDC2B+
`DDC2AB
`DPMS
`DSTN-LCD
`EDID
`EMI
`EVC
`TFT-LCD
`FPD
`FPDI
`HDTV
`IEEE 1394
`IC
`I2C™
`LCD
`LVDS
`Logical Layer
`MCS
`Microcross™
`
`P&D
`PanelLink™ Technology
`PLL
`Physical Layer
`RFI
`RGB2S
`Rxn
`TMDS™ 2
`
`TTL
`Txn
`USB
`VESA
`
`Description
`Application Specific Integrated Circuit
`Cathode Ray Tube
`(VESA) Display Data Channel
`The simplest mode defined in the VESA DDC standard
`The general term used to refer to any of the DDC2 modes (DDC2B,
`DDC2B+ and DDC2AB) defined in the VESA DDC standard
`Simplest of the DDC2 modes defined in VESA DDC standard
`Adds bi-directional communications to DDC2B
`An ACCESS.bus mode defined in VESA DDC standard
`(VESA) Display Power Management Standard
`Dual Scan Super Twisted Nematic LCD
`(VESA) Extended Display Identification Data
`Electromagnetic Interference
`(VESA) Enhanced Video Connector
`Thin Film Transistor LCD
`Flat Panel Display
`(VESA) Flat Panel display Interface
`High Definition Television
`Standard for High Performance Serial Bus
`Integrated Circuit
`Trademark of Philips used to refer to the Inter IC or I2C - Bus
`Liquid Crystal Display
`Low Voltage Differential Signaling1
`Used to indicate a section of code
`(VESA) Monitor Command Set
`Trademark of Molex Inc. for the quasi-coaxial section of the P&D
`connector system.
`Trademark of VESA for the Plug and Display standard
`Trademark of Silicon Image for their LVDS technology
`Phase Lock Loop
`Used to indicate a physical layer, either electrical or mechanical
`Radio Frequency Interference
`Red, Green & Blue Video, Hz. and Vt. Syncs.
`TMDS Receiver number ‘n’
`Trademark of Silicon Image used to refer to their PanelLink
`Technology2
`Transistor, Transistor Logic
`TMDS Transmitter number ‘n’
`Universal Serial Bus
`Video Electronics Standards Association
`
`1 The term LVDS is used in this document as a generic term and does not imply any particular LVDS
`technology.
`2 The term TMDS will generally be used in this document to denote PanelLink™ or compatible technologies.
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 4 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 004
`
`

`
`Referenced Standards and Documents
`
`Several Standards (listed in following table) are referenced by the P&D standard and compliance with the
`VESA P&D standard requires compliance with these standards.
`
`Standard Name
`
`Date
`
`Version /
` Reference
`C
`
`3.0
`
`1984-11
`
`Nov. ‘94
`
`Sep. ‘95
`Jan. ‘95
`Nov. ‘57
`
`Sep. ‘69
`
`ANSI/EIA-364--1994, Electrical Connector /Socket Test Procedures Including
`Environmental Classifications
`ACCESS.bus Specification
`ASME Y14.5M-1994
`EIA-170, Electrical Performance Standards - Monochrome Television Studio Facilities
`- (formerly RS-170)
`EIA-343-A, Electrical Performance Standard for High Resolution Monochrome
`Closed Circuit Television Camera
`IEC 801-1, Electromagnetic compatibility for industrial-process measurement and
`control equipment. Part 1 - General introduction
`Dec. ‘95
`1994
`IEEE-1394-1995
`Jan. ‘96
`1.0
`Universal Serial Bus Specification
`Nov. ‘96
`0.9g
`Universal Serial Bus Monitor Control Class Definition
`Apr. ‘96
`2.01
`VESA Display Data Channel Standard
`Aug. ‘93
`1.0
`VESA Display Power Management Signaling Standard
`Feb. '96
`1.0
`VESA Enhanced Video Connector Physical Connector Standard
`Nov. ‘95
`1.0
`VESA Enhanced Video Connector Standard
`Mar. '97
`1.2p
`VESA Enhanced Video Connector Standard : Proposed Revision
`Apr. ‘96
`2.0
`VESA Extended Display Identification Data Standard
`Jan. ‘97
`0.8
`VESA Flat Panel Display Interface 2 Standard Proposal
`Feb. ‘97
`0.2p
`VESA Monitor Command Set Proposal
`Aug. ‘96
`0.1p
`VESA Plug and Display Architecture Document 1
`1 Access to the VESA Plug and Display Architecture Document is restricted to VESA member companies.
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 5 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 005
`
`

`
`Index
`1. Introduction____________________________________________________________ 13
`1.1 P&D Overview ________________________________ ______________________________ 13
`1.2 P&D Interface ________________________________ ______________________________ 14
`1.2.1 Interface Elements_________________________________________________________________ 14
`1.2.2 Digital Interface: Capabilities ________________________________________________________ 14
`1.2.3 Analogue Interface: Capabilities ______________________________________________________ 14
`1.3 Compatibility with Other VESA Standards ________________________________ ______ 14
`1.3.1 Compatibility with VESA DDC Standard (see Section 2.1) _________________________________ 14
`1.3.2 Compatibility with VESA EDID Standard (see Section 2.1)_________________________________ 15
`1.3.3 Compatibility with VESA EVC Standard _______________________________________________ 15
`1.3.4 Compatibility with VESA DPMS Standard _____________________________________________ 16
`1.3.5 Compatibility with VESA FPDI-2 Standard _____________________________________________ 16
`1.4 Compatibility with Monitors Using Other Connectors _____________________________ 17
`1.4.1 Compatibility with Monitors Using 15-pin D-sub Connector________________________________ 17
`1.4.2 Compatibility with Monitors Using 13W3 Connector _____________________________________ 17
`1.4.3 Compatibility with Monitors Using BNC Connectors _____________________________________ 17
`1.5 Incompatible Display and System Interfaces ________________________________ _____ 17
`2. Plug and Display Architectural Overview ____________________________________ 18
`2.1 Plug and Display System Overview ________________________________ _____________ 18
`2.2 P&D Architecture ________________________________ ___________________________ 18
`2.2.1 Logical Layer Concepts_____________________________________________________________ 18
`2.2.2 Physical Layer Concepts ____________________________________________________________ 19
`2.2.3 Explanation of Remaining Elements of P&D Architecture Overview Drawing __________________ 20
`2.3 P&D-A/D Connector Overview ________________________________ ________________ 21
`3. Detection of Display Disconnect____________________________________________ 22
`3.1 Detection Mechanism - Host ________________________________ ___________________ 22
`3.2 Detection Mechanism - Display ________________________________ ________________ 22
`3.3 Power Up/Down and Hot Plugging : Flowchart ________________________________ ___ 23
`4. Electrical Layer Specification: Part 1 _______________________________________ 24
`4.1 Introduction ________________________________ ________________________________ 24
`4.2 DDC2 Sublayer, Type A ________________________________ ______________________ 24
`4.2.1 List of Signals ____________________________________________________________________ 24
`4.2.2 Signal Specification and Timing ______________________________________________________ 24
`4.2.3 Extended Display identification Data (EDID) ____________________________________________ 24
`4.3 IEEE 1394-1995 Sublayer, Type D1 ________________________________ _____________ 24
`4.4 USB Sublayer, Type D2 ________________________________ _______________________ 24
`4.5 Analogue Sublayer, Type E1 ________________________________ ___________________ 25
`4.5.1 Analogue Interface ________________________________________________________________ 25
`4.5.2 Analogue Video Signals ____________________________________________________________ 26
`4.5.3 Synchronisation Signals - VESA Video Signal Standard ___________________________________ 27
`4.5.4 Pixel Clock ______________________________________________________________________ 27
`4.6 Charging Power ________________________________ _____________________________ 29
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 6 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 006
`
`

`
`4.6.1 Hot Plugging _____________________________________________________________________ 29
`4.7 Stereo Syncronisation ________________________________ ________________________ 30
`5. Electrical Layer Specification: Digital (TMDS) Video Transmission Overview_______ 31
`5.1 Transition Minimised Differential Signaling Interface Overview _____________________ 31
`5.1.1 Introduction______________________________________________________________________ 31
`5.1.2 Logical Architecture _______________________________________________________________ 31
`5.1.3 Summary________________________________________________________________________ 34
`5.1.4 TMDS Transmitter ________________________________________________________________ 35
`5.1.5 TMDS Receiver Summary __________________________________________________________ 37
`5.1.6 Relationship Between Controller’s Output Data and Input Data Clock ________________________ 38
`5.2 TMDS Transition-Controlled Digital Encoding and Signal Transmission _____________ 40
`5.3 System Debug on Differential Data Pairs ________________________________ ________ 43
`5.4 Implementation ________________________________ _____________________________ 44
`5.4.1 Amplitude Modulated Signal mapping (e.g. TFT) ________________________________________ 44
`5.4.2 Temporal Modulated Signal Mapping (e.g. DSTN) - 16bpp_________________________________ 45
`5.4.3 Temporal-Modulated Signal Mapping (e.g. DSTN) - 24bpp ________________________________ 46
`5.5 Physical Layer ________________________________ ______________________________ 47
`5.5.1 Signal Bandwidth Characteristics _____________________________________________________ 47
`6. Electrical Layer Specification: TMDS Transmission Specification ________________ 48
`6.1 Electrical Characteristics ________________________________ _____________________ 48
`6.2 DC Electrical Specifications ________________________________ ___________________ 49
`6.2.1 Differential Transmitter DC Specifications ______________________________________________ 49
`6.2.2 Differential Receiver DC Specifications ________________________________________________ 49
`6.3 Driver Output Levels ________________________________ _________________________ 51
`6.4 Signal Integrity ________________________________ ______________________________ 53
`6.4.1 Jitter and Skew of Clock and Differential Data Pairs ______________________________________ 53
`6.5 Eye Diagram Template ________________________________ _______________________ 54
`6.6 AC Specifications ________________________________ ____________________________ 56
`6.6.1 Timing Diagrams _________________________________________________________________ 57
`6.7 Error Specification for Display Interface ________________________________ ________ 60
`6.8 Guidance for Display Controller Implementation ________________________________ _ 60
`7. Mechanical Physical Layer: Connector ______________________________________ 61
`7.1 Introduction ________________________________ ________________________________ 61
`7.1.1 P&D-A/D Connector_______________________________________________________________ 61
`7.1.2 P&D-D Connector_________________________________________________________________ 61
`7.2 Receptacle Connector ________________________________ ________________________ 62
`7.3 Positive Retention of Plug and Receptacle ________________________________ ________ 64
`7.4 Contact Finish On Plug And Receptacle Contacts ________________________________ _ 64
`7.5 Shell Finish On Plugs And Receptacles ________________________________ __________ 64
`7.6 Connector Durability ________________________________ _________________________ 65
`7.7 Plug Connector ________________________________ ______________________________ 65
`7.7.1 Plug Connector Termination _________________________________________________________ 65
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 7 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 007
`
`

`
`7.8 Pinouts________________________________ ________________________________ _____ 66
`7.8.1 Contact Sequencing________________________________________________________________ 66
`7.8.2 P&D-A/D Signal Pin Assignments - Main Pin Field ______________________________________ 67
`7.8.3 Signal Pin Assignments - MicroCross Section__________________________________________ 67
`7.8.4 P&D-D Signal Pin Assignments - Pin Field _____________________________________________ 68
`7.9 Connector Performance Characteristics ________________________________ _________ 68
`7.9.1 Environmental____________________________________________________________________ 68
`7.9.2 Electrical ________________________________________________________________________ 69
`7.9.3 Mechanical ______________________________________________________________________ 70
`7.10 Connector Performance Test Criteria ________________________________ __________ 71
`7.10.1 Connector Performance Test Groups__________________________________________________ 72
`8. Physical Layer: Cable Assembly Specifications________________________________ 82
`8.1 TMDS Video Sublayer, Type AT/AT’ ________________________________ ___________ 82
`8.2 Analogue Video Sublayer (Coax), Type A ________________________________ ________ 83
`8.3 Conductors for Vertical, Horizontal, Stereo Sync., Sync. Return and DDC, Type C _____ 83
`8.4 Conductors for Charge Power and +5VDC, Type D _______________________________ 83
`8.5 USB Sublayer, Type USB ________________________________ _____________________ 83
`8.6 IEEE 1394-1995 Sublayer, Type 1394 ________________________________ ___________ 83
`8.7 Cable Type Usage : P&D-A/D ________________________________ _________________ 84
`8.8 Cable Type Usage : P&D-D ________________________________ ___________________ 85
`9. Compliance with Plug and Display Standard _________________________________ 86
`9.1 A P&D-A/D Compliant Host System / Graphic Card / etc. __________________________ 86
`9.2 A P&D-D Compliant Host System / Graphic Card / etc. ____________________________ 86
`9.3 A P&D Compliant Display ________________________________ ____________________ 86
`9.4 P&D Symbol ________________________________ ________________________________ 87
`9.4.1 Upper Left Quadrant _______________________________________________________________ 87
`9.4.2 Upper Right Quadrant ______________________________________________________________ 87
`9.4.3 Lower Left Quadrant _______________________________________________________________ 87
`9.4.4 Lower Right Quadrant______________________________________________________________ 87
`9.4.5 Example ________________________________________________________________________ 87
`9.4.6 Additional Information _____________________________________________________________ 87
`10. Appendix A: Digital Monitor Cable Assembly ________________________________ 89
`10.1 Introduction ________________________________ _______________________________ 89
`10.2 P&D-D ⇔ P&D-D Plug Connectors ________________________________ ___________ 90
`10.2.1 Pin Definitions __________________________________________________________________ 90
`10.3 P&D-D ⇔ Microribbon Plug Connector ________________________________ ________ 91
`10.3.1 Assembly Drawing _______________________________________________________________ 91
`10.3.2 Pin Definitions, P&D-D ⇔ Microribbon ______________________________________________ 92
`11. Appendix B: Software Considerations at Start-Up ____________________________ 94
`11.1 Power on Sequences ________________________________ _________________________ 94
`11.1.1 System Unit Powers on after Monitor Power On ________________________________________ 94
`11.1.2 System Unit Powers on and Monitor Not Powered On ____________________________________ 95
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 8 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 008
`
`

`
`11.1.3 System Unit IPL after Monitor Power On______________________________________________ 96
`12. Appendix C: Guidance on Implementation __________________________________ 97
`12.1 P&D Family of Connectors ________________________________ ___________________ 97
`12.2 Plug - Receptacle Physical Compatibility Summary ______________________________ 97
`13. Appendix D: Power-Up and Hot-Plugging of P&D Hosts and Monitors ___________ 98
`13.1 Requirements of P&D Hosts ________________________________ __________________ 98
`13.2 Requirements of P&D Monitors ________________________________ _______________ 98
`13.3 Power-Up and Hot-Plugging Sequence of Events for P&D-A/D Host ________________ 99
`13.3.1 P&D-D Monitor Attached to P&D-A/D Host ___________________________________________ 99
`13.3.2 EVC Monitor Attached to P&D-A/D Host _____________________________________________ 99
`13.3.3 Non-P&D Monitor Attached to P&D-A/D Host ________________________________________ 100
`13.4 Power-Up and Hot-Plugging Sequence of Events for P&D-D Host _________________ 102
`13.4.1 P&D-D Monitor Attached to P&D-D Host ____________________________________________ 102
`13.4.2 Monitor with Analogue Interface Attached to P&D-D Host _______________________________ 102
`13.5 Power-Up and Hot-Plugging Sequence of Events for P&D-D Monitor ______________ 104
`14. Appendix E : Measurement Protocols_____________________________________ 106
`14.1 Bandwidth Measurements ________________________________ __________________ 106
`14.1.1 Scope and objective______________________________________________________________ 106
`14.1.2 Test Equipment _________________________________________________________________ 106
`14.1.3 Test Specimen __________________________________________________________________ 106
`14.1.4 Test Fixture ____________________________________________________________________ 106
`14.1.5 Test Method ___________________________________________________________________ 106
`14.2 Shell-to-Shell and Shell-to-Bulkhead Resistance ________________________________ 108
`14.2.1 Scope & Objectives______________________________________________________________ 108
`14.2.2 Measurement Equipment__________________________________________________________ 108
`14.2.3 Test Specimen __________________________________________________________________ 108
`14.2.4 Test Procedure__________________________________________________________________ 108
`14.2.5 Shell to Shell Resistance __________________________________________________________ 108
`14.2.6 Receptacle to Bulkhead Resistance __________________________________________________ 108
`14.2.7 Details to be Specified____________________________________________________________ 108
`14.2.8 Test Documentation _____________________________________________________________ 109
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 9 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 009
`
`

`
`Index of Tables
`TABLE 1-1 : P&D INTERFACE FEATURES
`TABLE 1-2 : P&D DIGITAL INTERFACE CAPABILITIES
`TABLE 1-3 : EVC VIDEO CAPABILITY
`TABLE 4-1 : ELECTRIC SUBLAYERS
`TABLE 4-2 : DDC2 SUBLAYER SIGNALS
`TABLE 5-1 : THEORETICAL LOW VOLTAGE SINGLE ENDED DIFFERENTIAL SWING LEVEL
`RELATIVE TO REXT_SWING
`TABLE 5-2 : ADDRESSABILITY TABLE
`TABLE 5-3 : ENCODER MAPPING FOR A SINGLE DIFFERENTIAL DATA PAIR
`TABLE 5-4 : SIGNAL NAME DESCRIPTIONS
`TABLE 5-5 : ENCODED DATA COMPONENTS FOR TX0 DIFFERENTIAL DATA PAIR
`TABLE 5-6 : ENCODED DATA COMPONENTS FOR TX1 DIFFERENTIAL DATA PAIR
`TABLE 5-7 : ENCODED DATA COMPONENTS FOR TX2 DIFFERENTIAL DATA PAIR
`TABLE 5-8 : SYSTEM DEBUG PATTERNS
`TABLE 5-9 : AMPLITUDE MODULATED COLOUR MAPPING
`TABLE 5-10 : TEMPORAL MODULATION COLOUR MAPPING - 16BPP
`TABLE 5-11 : TEMPORAL MAPPING, PIXEL LOCATION ON DISPLAY
`TABLE 5-12 : TEMPORAL MODULATION COLOUR MAPPING - 24BPP
`TABLE 5-13 : DISTRIBUTED TRANSMISSION PATH BANDWIDTH AND RISE-TIME
`TABLE 6-1 : TRANSMITTER DC SPECIFICATIONS FOR 25 - 65MHZ
`TABLE 6-2 : RECEIVER DC SPECIFICATIONS FOR 25 - 65MHZ
`TABLE 6-3 : DC SPECIFICATIONS
`TABLE 6-4 : COMPONENT VALUES, CAPACITOR COUPLING
`TABLE 6-5 : SIGNAL INTEGRITY PARAMETERS
`TABLE 6-6 : EYE DIAGRAM MASK AT POINT S1
`TABLE 6-7: EYE DIAGRAM MASK AT POINT R1
`TABLE 6-8 : AC SPECIFICATION (PART 1)
`TABLE 6-9 : AC SPECIFICATION (PART 2)
`TABLE 7-1 : P&D-A/D AND P&D-D SIGNALS
`TABLE 7-2 : CONTACT SEQUENCING
`TABLE 7-3 : P&D-A/D SIGNAL ASSIGNMENT - MAIN PIN FIELD
`TABLE 7-4 : SIGNAL ASSIGNMENT - MICROCROSS SECTION
`TABLE 7-5 : SIGNAL ASSIGNMENT - MAIN PIN FIELD
`TABLE 7-6 : PERFORMANCE GROUP A
`TABLE 7-7 : PERFORMANCE GROUP B
`TABLE 7-8 : PERFORMANCE GROUP C
`TABLE 7-9 : PERFORMANCE GROUP D
`TABLE 7-10 : PERFORMANCE GROUP E
`TABLE 7-11 : PERFORMANCE GROUP F
`TABLE 7-12 : PERFORMANCE GROUP FP - GENERAL PURPOSE, SINGLE ENDED
`TABLE 7-13 : PERFORMANCE GROUP FP - GENERAL PURPOSE, DIFFERENTIAL
`TABLE 7-14 : PERFORMANCE GROUP FP - QUASI-COAXIAL LINES
`TABLE 7-15 : PERFORMANCE GROUP G
`TABLE 8-1 : PHYSICAL SUBLAYER DESIGNATIONS
`TABLE 8-2 : TMDS VIDEO SUBLAYER ATTRIBUTES (PART 1)
`TABLE 8-3 : TMDS VIDEO SUBLAYER ATTRIBUTES (PART 2)
`TABLE 8-4 : ANALOGUE VIDEO SUBLAYER ATTRIBUTES # 1
`TABLE 8-5 : ANALOGUE VIDEO SUBLAYER ATTRIBUTES # 2
`TABLE 8-6 : CABLE TYPE USAGE - P&D-A/D
`TABLE 8-7 : CABLE TYPE USAGE - P&D-D
`
`14
`14
`16
`24
`24
`
`32
`34
`36
`39
`40
`41
`41
`43
`44
`45
`45
`46
`47
`49
`49
`49
`52
`53
`54
`55
`56
`57
`66
`66
`67
`67
`68
`72
`73
`74
`75
`76
`77
`78
`79
`80
`81
`82
`82
`82
`83
`83
`84
`85
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 10 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 010
`
`

`
`Index of Figures
`
`21
`FIGURE 2-1 : P&D-A/D CONNECTOR OVERVIEW
`23
`FIGURE 3-1 : POWER UP/DOWN AND HOT PLUGGING FLOWCHART
`25
`TABLE 4-1 : ANALOGUE SUBLAYER SIGNALS
`26
`TABLE 4-2 : VIDEO SIGNAL AMPLITUDE AND POLARITY
`27
`TABLE 4-3 : SYNCHRONISATION SIGNAL SPECIFICATION
`28
`FIGURE 4-4 : STEREO SYNC.
`31
`FIGURE 5-1 : SIMPLIFIED BLOCK DIAGRAM OF A TMDS INTERFACE WITH CLOCK + RGB
`33
`FIGURE 5-2 : TRANSITION MINIMISED DIFFERENTIAL VOLTAGE SWING ADJUST
`FIGURE 5-3 : SINGLE ENDED TRANSITION MINIMISED DIFFERENTIAL SIGNAL ADJUSTMENT 33
`FIGURE 5-4 : SYSTEM ENVIRONMENT BLOCK DIAGRAM EXAMPLE
`34
`FIGURE 5-5 : TMDS TRANSMITTER IC FUNCTIONAL BLOCK DIAGRAM
`35
`FIGURE 5-6 : TYPICAL CMOS CIRCUITS FOR TMDS DRIVER
`36
`FIGURE 5-7 : HORIZONTAL INPUT TIMING AT TYPE B INTERFACE
`38
`FIGURE 5-8 : VERTICAL INPUT TIMING AT TYPE B INTERFACE
`38
`FIGURE 5-9 : INPUT DATA TIMING WITH RESPECT TO IDCK AT TYPE B INTERFACE
`38
`FIGURE 5-10 : CONTROL SIGNAL TIMING WITH RESPECT TO IDCK AT TYPE B INTERFACE
`38
`FIGURE 5-11 : CONTROL SIGNALS WITH RESPECT TO DE TIMING
`39
`FIGURE 5-12 : TMDS INTERFACE TRANSITION MINIMISATION TIMING DIAGRAM
`40
`FIGURE 5-13 : ENCODED TIMING DIAGRAM FOR ALL DIFFERENTIAL DATA PAIRS
`41
`FIGURE 5-14 : HSYNC., VSYNC., AND CTL[3:1] SAMPLING RELATIVE TO CLOCK EDGE
`42
`FIGURE 6-1 : DIFFERENTIAL MODE IMPEDANCE
`48
`FIGURE 6-2 : SIGNAL LEVELS ON TRANSMISSION MEDIA
`48
`FIGURE 6-3 : TEST CIRCUIT FOR MEASURING IOH AND IOL
`50
`FIGURE 6-4 : DRIVER AND RECEIVER CIRCUIT MODEL FOR ONE DIFFERENTIAL DATA PAIR
`51
`FIGURE 6-5 : CAPACITOR COUPLED TMDS SYSTEM
`52
`FIGURE 6-6 : TIMING DIAGRAM FOR JITTER AND SKEW SPECIFICATION
`53
`FIGURE 6-7: TMDS CONNECTION
`54
`FIGURE 6-8: EYE DIAGRAM MASK AT POINT S
`54
`FIGURE 6-9: EYE DIAGRAM MASK AT POINT R
`55
`FIGURE 6-10 : TRANSMITTER SMALL SIGNAL TRANSITION TIMES
`57
`FIGURE 6-11 : RECEIVER DIGITAL OUTPUT TRANSITION TIMES
`57
`FIGURE 6-12 : TRANSMITTER / RECEIVER CLOCK CYCLE HIGH / LOW TIMES
`58
`FIGURE 6-13 : DIFFERENTIAL DATA PAIR TO DIFFERENTIAL DATA PAIR SKEW TIMING
`58
`FIGURE 6-14 : DE, VSYNC., HSYNC., AND CLT[3:1] SETUP / HOLD TIMES TO IDCK OF
`TRANSMITTER
`FIGURE 6-15 : VSYNC., HSYNC., AND CLT[3:1] DELAY TIMES FROM DE OF TRANSMITTER
`FIGURE 6-16 : DE HIGH / LOW TIMES OF TRANSMITTER
`FIGURE 6-17 : PLL_SYNC TIMING OF TRANSMITTER WITH SYNC_CONT = 1
`FIGURE 6-18 : PLL_SYNC TIMING OF TRANSMITTER WITH SYNC_CONT = 0
`FIGURE 6-19 : OUTPUT SIGNALS DISABLED / ENABLED TIMING FROM PD ACTIVE / INACTIVE
`59
`FROM TRANSMITTER
`59
`FIGURE 6-20 : DIFFERENTIAL CLOCK DELAY FROM IDCK
`60
`FIGURE 6-21 : LINE ERROR RATE
`60
`FIGURE 6-22 : FULL FRAME ERROR RATE
`FIGURE 7-1 : P&D-A/D RECEPTACLE CONNECTOR - BASIC MATING INTERFACE DIMENSIONS 62
`FIGURE 7-2 : P&D-D RECEPTACLE CONNECTOR - BASIC MATING INTERFACE DIMENSIONS
`62
`FIGURE 7-3 : P&D-A/D REFERENCE HOLE PATTERN (RECEPTACLE)
`63
`FIGURE 7-4 : P&D-D REFERENCE HOLE PATTERN (RECEPTACLE)
`63
`FIGURE 7-5 : RECOMMENDED PANEL CUT-OUT
`64
`FIGURE 7-6 : P&D-D PLUG CONNECTOR - BASIC MATING INTERFACE DIMENSIONS
`65
`FIGURE 9-1 : P&D SYMBOL
`87
`FIGURE 9-2 : P&D SYMBOL EXAMPLE
`87
`FIGURE 10-1 : PIN DEFINITIONS, P&D-D ⇔ P&D-D
`90
`FIGURE 10-2 : CABLE ASSEMBLY DRAWING, P&D-D ⇔ MICRORIBBON
`91
`
`58
`58
`58
`59
`59
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 11 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 011
`
`

`
`FIGURE 10-3 : PIN DEFINITIONS, P&D-D ⇔ MICRORIBBON
`FIGURE 12-1 : P&D CONNECTOR FAMILY
`FIGURE 12-2 : PLUG RECEPTACLE PHYSICAL COMPATIBILITY
`FIGURE 13-1 : POWER-UP AND HOT PLUGGING FLOWCHART FOR P&D-A/D HOST
`FIGURE 13-2 : POWER-UP AND HOT-PLUGGING FLOWCHART FOR P&D-D (TMDS) HOST
`FIGURE 13-3 : POWER-UP AND HOT-PLUGGING FLOWCHART FOR P&D-D (TMDS) MONITOR
`FIGURE 14-1 : BANDWIDTH MEASUREMENT SET-UP
`
`92
`97
`97
`101
`103
`105
`107
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 12 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 012
`
`

`
`1. Introduction
`
`1.1 P&D Overview
`The purpose of this standard is to provide a digital interface and, optionally, an analogue interface for video
`data allowing a wide range of display devices to be attached to a single video port on the host system which
`may be a personal computer (PC), workstation or other device. This standard only defines the interface at the
`connector on the host system and provides additional recommendations regarding system implementation.
`
`Monitors using a digital video interface generally have a fixed pixel format, typified by, but not restricted to, a
`Liquid Crystal Display (LCD) monitor. The objective is to retain data in a digital format thus eliminating the
`analogue conversion losses that cause screen artifacts. Retaining data in a digital format additionally provides
`opportunities for reducing system cost and simplifying the display setup.
`
`The digital interface defined in this standard is referred to as Transition Minimised Differential Signaling
`(TMDS).
`
`Analogue interface monitors are typified by, but not restricted to, CRT (cathode ray tube) based displays.
`
`Prior to the P&D standard, the attachment of digital interface displays to PC’s or workstations has required
`either:
`
`• Conversion of the analogue interface to digital at the display with cost and image quality problems
`• Provision of a separate graphics card with a digital interface with cost, space (slot for card), and the
`issues of a proprietary interface needing to be handled
`
`Key features and benefits of the VESA P&D interface are:
`• Single connector for any display device.
`• Industry standard, interoperability from multiple suppliers.
`• High quality display output.
`• Scaleable cost and performance.
`• Interoperable solution for analogue and digital monitors.
`• Independent software and hardware layers.
`• Operating System independent.
`• Plug and Play enabled.
`• Capable of using existing technology.
`• Capable of working over several metres of cable.
`• No DC component on interface.
`• Low electromagnetic emission.
`• Reduced pin count relative to parallel interface (typically 7:1 ratio).
`The host receptacle interface defined in this standard is referred to as the P&D-A/D (Plug and Display -
`Analogue / Digital) in Section 12 which explains the relationships between this and other receptacles in the
`same family together with the expected monitor plugs.
`The P&D-D receptacle shown in Section 12 is a logical extension of this standard for host applications not
`requiring an analogue option.
`
`VESA Plug and Display Standard
`Copyright 1997 Video Electronics Standards Association
`
`Page 13 of 109
`Version 1 Revision 0
`
`NVIDIA Corp.
`Exhibit 1005
`Page 013
`
`

`
`1.2 P&D Interface
`The term ‘logical layer’ is used in this section to indicate a section of code.
`
`1.2.1 Interface Elements
`Feature
`Digital Interface
`Analogue Interface1
`DDC2
`USB
`IEEE 1394-1995
`Initialisation Logical Layer
`Command Logical Layer
`Adapter Logical Layer
`
`Comment
`Mandatory
`Optional
`Mandatory
`Optional
`Optional
`Mandatory
`Optional
`Mandatory
`
`Table 1-1 : P&D Interface Features
`1 The analogue interface may be either:
`• Red, green and blue video with Vsync. and Hsync., or
`• Red, green and blue video with composite sync.
`1.2.2 Digital Interface: Capabilities
`See Section 6 for details of performance ranges, table 1.2 shows the maximum performance capability and the
`minimum set of features present.
`
`Maximum clock rate
`Maximum addressibility
`Maximum refresh rate
`Maximum colour capability
`DDC