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`ALTIVECPEM/D
`11/1998
`Rev. 0
`
`AltiVec Technology
`Programming Environments Manual
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`SAMSUNG-1009
`Page 1 of 350
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`AltiVec is a trademark of Motorola, Inc.
`DigitalDNA is a trademark of Motorola, Inc.
`The PowerPC name and the PowerPC logotype are trademarks of International Business Machines Corporation used by Motorola under license from
`International Business Machines Corporation.
`Mfax is a trademark of Motorola, Inc.
`
`This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
`Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or
`implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this
`document.
`Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
`regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
`or circuit, and speci(cid:222)cally disclaims any and all liability, including without limitation consequential or incidental damages. (cid:210)Typical(cid:211) parameters can and do
`vary in different applications. All operating parameters, including (cid:210)Typicals(cid:211) must be validated for each customer application by customer(cid:213)s technical
`experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized
`for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
`application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use
`Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its of(cid:222)cers, employees, subsidiaries,
`af(cid:222)liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
`any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
`regarding the design or manufacture of the part. Motorola and
` are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/
`Af(cid:222)rmative Action Employer.
`
`Motorola Literature Distribution Centers:
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`USA/EUROPE: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217; Tel.: 1-800-441-2447 or 1-303-675-2140/
`JAPAN
`: Nippon Motorola Ltd SPD, Strategic Planning Of(cid:222)ce 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan Tel.: 81-3-5487-8488
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`ASIA/PACIFC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong; Tel.: 852-26629298
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`Mfax“
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`World Wide Web Address: http://sps.motorola.com/mfax
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`INTERNET: http://motorola.com/sps
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`Technical Information: Motorola Inc. SPS Customer Support Center 1-800-521-6274; electronic mail address: crc@wmkmail.sps.mot.com.
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`Document Comments
`: FAX (512) 895-2638, Attn: RISC Applications Engineering.
`
`World Wide Web Addresses: http://www.mot.com/PowerPC
`http://www.mot.com/netcomm
`
`' Motorola Inc. 1998. All rights reserved.
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`1 2 3 4 5 6
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`Overview
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`AltiVec Register Set
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`Operand Conventions
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`Addressing Modes and Instruction Set Summary
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`Cache, Exceptions, and Memory Management
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`AltiVec Instructions
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`AltiVec Instruction Set Listings
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`A
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`Glossary of Terms and Abbreviations
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`GLO
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`Index
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`IND
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`Overview
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`AltiVec Register Set
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`Operand Conventions
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`Addressing Modes and Instruction Set Summary
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`Cache, Exceptions, and Memory Management
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`AltiVec Instructions
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`A
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`AltiVec Instruction Set Listings
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`1 2 3 4 5 6
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`GLO
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`Glossary of Terms and Abbreviations
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`IND
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`CONTENTS
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`Title
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`About This Book
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`Page
`Number
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`Audience ................................................................................................................xx
`Organization...........................................................................................................xx
`Suggested Reading............................................................................................... xxi
`General Information............................................................................................ xxi
`PowerPC Documentation................................................................................... xxii
`Conventions ....................................................................................................... xxiv
`Acronyms and Abbreviations ..............................................................................xxv
`Terminology Conventions ................................................................................ xxvii
`
`Chapter 1
`Overview
`
`1.1
`1.1.1
`1.1.2
`1.1.3
`1.2
`1.2.1
`1.2.2
`1.2.2.1
`1.2.2.2
`1.2.3
`1.2.4
`1.2.5
`1.2.6
`1.2.7
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`Overview.............................................................................................................. 1-2
`The 64-Bit AltiVec Technology and the 32-Bit Subset................................... 1-5
`The Levels of the AltiVec ISA ........................................................................ 1-5
`Features Not Defined by the AltiVec ISA ....................................................... 1-6
`The AltiVec Architectural Model ........................................................................ 1-6
`AltiVec Registers and Programming Model.................................................... 1-7
`Operand Conventions ...................................................................................... 1-7
`Byte Ordering .............................................................................................. 1-7
`Floating-Point Conventions ......................................................................... 1-8
`AltiVec Addressing Modes.............................................................................. 1-9
`AltiVec Instruction Set .................................................................................. 1-10
`AltiVec Cache Model ................................................................................... 1-11
`AltiVec Exception Model .............................................................................. 1-11
`Memory Management Model ........................................................................ 1-12
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`Chapter 2
`AltiVec Register Set
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`2.1
`2.1.1
`2.1.2
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`AltiVec Register File (VRF)................................................................................ 2-1
`The Vector Status and Control Register (VSCR) ............................................ 2-2
`VRSAVE Register (VRSAVE) ....................................................................... 2-4
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`MOTOROLA
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`2.1.3
`2.1.4
`2.1.5
`2.1.5.1
`2.1.5.2
`2.2
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`3.1
`3.1.1
`3.1.2
`3.1.2.1
`3.1.2.2
`3.1.3
`3.1.4
`3.1.5
`3.1.6
`3.1.6.1
`3.1.6.2
`3.1.6.3
`3.1.6.4
`3.1.7
`3.2
`3.2.1
`3.2.1.1
`3.2.1.2
`3.2.2
`3.2.3
`3.2.4
`3.2.4.1
`3.2.4.2
`3.2.4.3
`3.2.4.4
`3.2.4.5
`3.2.4.6
`3.2.5
`3.2.5.1
`3.2.5.2
`3.2.5.3
`3.2.5.4
`3.2.5.5
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`CONTENTS
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`Title
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`Page
`Number
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`PowerPC Condition Register ........................................................................... 2-5
`AltiVec Bit in the PowerPC Machine State Register (MSR) .......................... 2-5
`Machine Status Save/Restore Registers (SRR) ............................................... 2-7
`Machine Status Save/Restore Register 0 (SRR0)........................................ 2-7
`Machine Status Save/Restore Register 1 (SRR1)........................................ 2-8
`PowerPC Register Set .......................................................................................... 2-8
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`Chapter 3
`Operand Conventions
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`Data Organization in Memory ............................................................................. 3-1
`Aligned and Misaligned Accesses ................................................................... 3-1
`AltiVec Byte Ordering..................................................................................... 3-2
`Big-Endian Byte Ordering........................................................................... 3-3
`Little-Endian Byte Ordering ........................................................................ 3-3
`Quad Word Byte Ordering Example ............................................................... 3-3
`Aligned Scalars in Little-Endian Mode ........................................................... 3-4
`Vector Register and Memory Access Alignment ............................................ 3-6
`Quad-Word Data Alignment............................................................................ 3-7
`Accessing a Misaligned Quad Word in Big-Endian Mode ......................... 3-8
`Accessing a Misaligned Quad Word in Little-Endian Mode..................... 3-10
`Scalar Loads and Stores............................................................................. 3-11
`Misaligned Scalar Loads and Stores.......................................................... 3-11
`Mixed-Endian Systems .................................................................................. 3-11
`AltiVec Floating-Point Instructions(cid:209)UISA...................................................... 3-12
`Floating-Point Modes .................................................................................... 3-12
`Java Mode.................................................................................................. 3-13
`Non-Java Mode.......................................................................................... 3-13
`Floating-Point Infinities................................................................................. 3-14
`Floating-Point Rounding................................................................................ 3-14
`Floating-Point Exceptions.............................................................................. 3-14
`NaN Operand Exception............................................................................ 3-14
`Invalid Operation Exception...................................................................... 3-15
`Zero Divide Exception............................................................................... 3-15
`Log of Zero Exception............................................................................... 3-16
`Overflow Exception................................................................................... 3-16
`Underflow Exception................................................................................. 3-16
`Floating-Point NaNs ...................................................................................... 3-17
`NaN Precedence......................................................................................... 3-17
`SNaN Arithmetic ....................................................................................... 3-17
`QNaN Arithmetic....................................................................................... 3-17
`NaN Conversion to Integer........................................................................ 3-17
`NaN Production ......................................................................................... 3-17
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`vi
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`AltiVec Technology Programming Environments Manual
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`MOTOROLA
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`Chapter 4
`Addressing Modes and Instruction Set Summary
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`Conventions ......................................................................................................... 4-2
`Execution Model.............................................................................................. 4-2
`Computation Modes......................................................................................... 4-2
`Classes of Instructions ..................................................................................... 4-3
`Memory Addressing ........................................................................................ 4-3
`Memory Operands ....................................................................................... 4-3
`Effective Address Calculation ..................................................................... 4-3
`AltiVec UISA Instructions................................................................................... 4-4
`Vector Integer Instructions .............................................................................. 4-4
`Saturation Detection .................................................................................... 4-4
`Vector Integer Arithmetic Instructions........................................................ 4-5
`Vector Integer Compare Instructions......................................................... 4-13
`Vector Integer Logical Instructions ........................................................... 4-15
`Vector Integer Rotate and Shift Instructions ............................................. 4-16
`Vector Floating-Point Instructions................................................................. 4-17
`Floating-Point Division and Square-Root ................................................. 4-17
`Floating-Point Division ......................................................................... 4-18
`Floating-Point Square-Root................................................................... 4-18
`Floating-Point Arithmetic Instructions ...................................................... 4-19
`Floating-Point Multiply-Add Instructions ................................................. 4-19
`Floating-Point Rounding and Conversion Instructions ............................. 4-20
`Floating-Point Compare Instructions......................................................... 4-21
`Floating-Point Estimate Instructions ......................................................... 4-24
`Load and Store Instructions ........................................................................... 4-24
`Alignment .................................................................................................. 4-25
`Load and Store Address Generation .......................................................... 4-25
`Vector Load Instructions ........................................................................... 4-26
`Vector Store Instructions ........................................................................... 4-30
`Control Flow .................................................................................................. 4-30
`Vector Permutation and Formatting Instructions........................................... 4-30
`Vector Pack Instructions............................................................................ 4-31
`Vector Unpack Instructions ....................................................................... 4-32
`Vector Merge Instructions ......................................................................... 4-33
`Vector Splat Instructions ........................................................................... 4-34
`Vector Permute Instructions ...................................................................... 4-35
`Vector Select Instruction ........................................................................... 4-35
`Vector Shift Instructions............................................................................ 4-36
`Immediate Interelement Shifts/Rotates.................................................. 4-36
`Computed Interelement Shifts/Rotates.................................................. 4-37
`Variable Interelement Shifts .................................................................. 4-37
`
`4.1
`4.1.1
`4.1.2
`4.1.3
`4.1.4
`4.1.4.1
`4.1.4.2
`4.2
`4.2.1
`4.2.1.1
`4.2.1.2
`4.2.1.3
`4.2.1.4
`4.2.1.5
`4.2.2
`4.2.2.1
`4.2.2.1.1
`4.2.2.1.2
`4.2.2.2
`4.2.2.3
`4.2.2.4
`4.2.2.5
`4.2.2.6
`4.2.3
`4.2.3.1
`4.2.3.2
`4.2.3.3
`4.2.3.4
`4.2.4
`4.2.5
`4.2.5.1
`4.2.5.2
`4.2.5.3
`4.2.5.4
`4.2.5.5
`4.2.5.6
`4.2.5.7
`4.2.5.7.1
`4.2.5.7.2
`4.2.5.7.3
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`MOTOROLA
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`4.2.6
`4.2.6.1
`4.2.7
`4.3
`4.3.1
`4.3.2
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`5.1
`5.1.1
`5.2
`5.2.1
`5.2.1.1
`5.2.1.2
`5.2.1.3
`5.2.1.4
`5.2.1.5
`5.2.1.6
`5.2.1.7
`5.2.1.8
`5.2.1.9
`5.2.2
`5.2.3
`5.3
`5.4
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`6.1
`6.1.1
`6.1.2
`6.2
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`A.1
`A.2
`A.3
`A.4
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`viii
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`Processor Control Instructions(cid:209)UISA ......................................................... 4-38
`AltiVec Status and Control Register Instructions...................................... 4-38
`Recommended Simplified Mnemonics.......................................................... 4-39
`AltiVec VEA Instructions.................................................................................. 4-39
`Memory Control Instructions(cid:209)VEA ............................................................ 4-39
`User-Level Cache Instructions(cid:209)VEA .......................................................... 4-40
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`Chapter 5
`Cache, Exceptions, and Memory Management
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`PowerPC Shared Memory.................................................................................... 5-1
`PowerPC Memory Access Ordering................................................................ 5-1
`AltiVec Memory Bandwidth Management.......................................................... 5-3
`Software-Directed Prefetch.............................................................................. 5-3
`Data Stream Touch (dst).............................................................................. 5-3
`Transient Streams (dstt)............................................................................... 5-5
`Storing to Streams (dstst)............................................................................. 5-5
`Stopping Streams (dss) ................................................................................ 5-6
`Exception Behavior of Prefetch Streams..................................................... 5-7
`Synchronization Behavior of Streams ......................................................... 5-8
`Address Translation for Streams ................................................................. 5-8
`Stream Usage Notes..................................................................................... 5-8
`Stream Implementation Assumptions........................................................ 5-10
`Prioritizing Cache Block Replacement.......................................................... 5-10
`Partially Executed AltiVec Instructions ........................................................ 5-11
`DSI Exception(cid:209)Data Address Breakpoint ....................................................... 5-11
`AltiVec Unavailable Exception (0x00F20) ....................................................... 5-11
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`Chapter 6
`AltiVec Instructions
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`Instruction Formats .............................................................................................. 6-1
`Instruction Fields ............................................................................................. 6-2
`Notation and Conventions ............................................................................... 6-2
`AltiVec Instruction Set ........................................................................................ 6-8
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`Appendix A
`AltiVec Instruction Set Listings
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`Instructions Sorted by Mnemonic....................................................................... A-1
`Instructions Sorted by Opcode............................................................................ A-7
`Instructions Sorted by Form.............................................................................. A-12
`Instruction Set Legend ...................................................................................... A-18
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`AltiVec Technology Programming Environments Manual
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`MOTOROLA
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`Figure
`Number
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`Title
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` Page
` Number
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` 1-1
` 1-2
` 1-3
` 1-4
` 1-5
` 2-1
` 2-2
` 2-3
` 2-4
` 2-5
` 2-6
` 2-7
` 2-8
` 2-9
` 2-10
` 3-1
` 3-2
` 3-3
` 3-4
` 3-5
` 3-6
` 3-8
` 3-7
` 3-9
` 4-1
` 5-1
` 5-2
` 6-1
` 6-2
` 6-3
` 6-4
` 6-5
` 6-6
` 6-7
` 6-8
` 6-9
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`High Level Structural Overview of PowerPC with AltiVec Technology................... 1-3
`AltiVec Top-Level Diagram ....................................................................................... 1-7
`Big-Endian Byte Ordering for a Vector Register ....................................................... 1-8
`Intraelement Example, vaddsws ................................................................................. 1-9
`Interelement Example, vperm..................................................................................... 1-9
`AltiVec Register File .................................................................................................. 2-2
`Vector Status and Control Register (VSCR) .............................................................. 2-2
`VSCR Moved to a Vector Register............................................................................. 2-3
`Saving/Restoring the AltiVec Context Register (VRSAVE)...................................... 2-4
`Condition Register (CR) ............................................................................................. 2-5
`Machine State Register (MSR)(cid:209)64-Bit Implementation........................................... 2-6
`Machine State Register (MSR)(cid:209)32-Bit Implementation........................................... 2-6
`Machine Status Save/Restore Register 0 (SRR0) ....................................................... 2-8
`Machine Status Save/Restore Register 1 (SRR1) ....................................................... 2-8
`Programming Model(cid:209)All Registers .......................................................................... 2-9
`Big-Endian Mapping of a Quad Word........................................................................ 3-3
`Little-Endian Mapping of a Quad Word..................................................................... 3-4
`Little-Endian Mapping of Quad Word(cid:209)Alternate View ........................................... 3-4
`Quad Word Load with Munged Little-Endian Applied.............................................. 3-5
`AltiVec Little Endian Swap ........................................................................................ 3-6
`Misaligned Vector in Big-Endian Mode..................................................................... 3-7
`Big-Endian Quad Word Alignment ............................................................................ 3-8
`Misaligned Vector in Little-Endian Addressing Mode............................................... 3-8
`Little-Endian Alignment ........................................................................................... 3-10
`Register Indirect with Index Addressing for Loads/Stores....................................... 4-26
`Format of rB in dst Instruction.................................................................................... 5-3
`Data Stream Touch ..................................................................................................... 5-4
`Format of rB in dst instruction (32-bit)..................................................................... 6-11
`Format of rB in dst instruction (64-bit)..................................................................... 6-11
`Format of rB in dst instruction (32-Bit).................................................................... 6-13
`Format of rB in dst instruction (64-Bit).................................................................... 6-13
`Effects of Example Load/Store Instructions ............................................................. 6-15
`Load Vector for Shift Left ........................................................................................ 6-19
`Instruction vperm Used in Aligning Data................................................................. 6-19
`vaddcuw(cid:209)Determine Carries of Four Unsigned Integer Adds (32-Bit).................. 6-31
`vaddfp(cid:209)Add Four Floating-Point Elements (32-Bit) .............................................. 6-32
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`Figure
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` 6-11
` 6-12
` 6-13
` 6-14
` 6-15
` 6-16
` 6-17
` 6-18
` 6-19
` 6-20
` 6-21
` 6-22
` 6-23
` 6-24
` 6-25
` 6-26
` 6-27
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` 6-28
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` 6-29
` 6-30
` 6-31
` 6-32
` 6-33
` 6-34
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` 6-35
` 6-36
` 6-37
` 6-38
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` 6-40
` 6-41
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` 6-44
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`Title
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`vaddsbs(cid:209) Add Saturating Sixteen Signed Integer Elements (8-Bit) ....................... 6-33
`vaddshs(cid:209) Add Saturating Eight Signed Integer Elements (16-Bit) ........................ 6-34
`vaddsws(cid:209)Add Saturating Four Signed Integer Elements (32-Bit).......................... 6-35
`vaddubm(cid:209)Add Sixteen Integer Elements (8-Bit).................................................... 6-36
`vaddubs(cid:209)Add Saturating Sixteen Unsigned Integer Elements (8-Bit) ................... 6-37
`vadduhm(cid:209)Add Eight Integer Elements (16-Bit) ..................................................... 6-38
`vadduhs(cid:209)Add Saturating Eight Unsigned Integer Elements (16-Bit)..................... 6-39
`vadduwm(cid:209)Add Four Integer Elements (32-Bit) ..................................................... 6-40
`vadduws(cid:209)Add Saturating Four Unsigned Integer Elements (32-Bit) ..................... 6-41
`vand(cid:209)Logical Bitwise AND.................................................................................... 6-42
`vand(cid:209)Logical Bitwise AND with Complement...................................................... 6-43
`vavgsb(cid:209) Average Sixteen Signed Integer Elements (8-Bit) ................................... 6-44
`vavgsh(cid:209)Average Eight Signed Integer Elements (16-bits)..................................... 6-45
`vavgsw(cid:209) Average Four Signed Integer Elements (32-Bit) ..................................... 6-46
`vavgub(cid:209)Average Sixteen Unsigned Integer Elements (8-bits)............................... 6-47
`vavgsh(cid:209) Average Eight Signed Integer Elements (16-Bit)..................................... 6-48
`vavguw(cid:209)Average Four Unsigned Integer Elements (32-Bit) ................................. 6-49
`vcfsx(cid:209)Convert Four Signed Integer Elements to Four Floating-Point
`Elements (32-Bit)............................................................................................... 6-50
`vcfux(cid:209)Convert Four Unsigned Integer Elements to Four Floating-Point
`Elements (32-Bit)............................................................................................... 6-51
`vcmpbfp(cid:209)Compare Bounds of Four Floating-Point Elements (32-Bit).................. 6-53
`vcmpeqfp(cid:209)Compare Equal of Four Floating-Point Elements (32-Bit)................... 6-54
`vcmpequb(cid:209)Compare Equal of Sixteen Integer Elements (8-bits)........................... 6-55
`vcmpequh(cid:209)Compare Equal of Eight Integer Elements (16-Bit)............................. 6-56
`vcmpequw(cid:209)Compare Equal of Four Integer Elements (32-Bit) ............................. 6-57
`vcmpgefp(cid:209)Compare Greater-Than-or-Equal of Four Floating-Point
`Elements (32-Bit)............................................................................................... 6-58
`vcmpgtfp(cid:209)Compare Greater-Than of Four Floating-Point Elements (32-Bit) ....... 6-59
`vcmpgtsb(cid:209)Compare Greater-Than of Sixteen Signed Integer Elements (8-Bit) .... 6-60
`vcmpgtsh(cid:209)Compare Greater-Than of Eight Signed Integer Elements (16-Bit)...... 6-61
`vcmpgtsw(cid:209)Compare Greater-Than of Four Signed Integer Elements (32-Bit)...... 6-62
`vcmpgtub(cid:209)Compare Greater-Than of Sixteen Unsigned Integer Elements (8-Bit) 6-63
`vcmpgtuh(cid:209)Compare Greater-Than of Eight Unsigned Integer Elements (16-Bit) . 6-64
`vcmpgtuw(cid:209)Compare Greater-Than of Four Unsigned Integer Elements (32-Bit) . 6-65
`vctsxs(cid:209)Convert Four Floating-Point Elements to Four Signed Integer
`Elements (32-Bit)............................................................................................... 6-66
`vctuxs(cid:209)Convert Four Floating-Point Elements to Four Unsigned Integer
`Elements (32-Bit)............................................................................................... 6-67
`vexptefp(cid:209)2 Raised to the Exponent Estimate Floating-Point for Four
`Floating-Point Elements (32-Bit)....................................................................... 6-69
`vexptefp(cid:209)Log2 Estimate Floating-Point for Four Floating-Point
`Elements (32-Bit)............................................................................................... 6-71
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`AltiVec Technology Programming Environments Manual
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`MOTOROLA
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`SAMSUNG-1009
`Page 10 of 350
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`vmaddfp(cid:209)Multiply-Add Four Floating-Point Elements (32-Bit)............................ 6-72
`vmaxfp(cid:209)Maximum of Four Floating-Point Elements (32-Bit)............................... 6-73
`vmaxsb(cid:209)Maximum of Sixteen Signed Integer Elements (8-Bit)............................ 6-74
`vmaxsh(cid:209)Maximum of Eight Signed Integer Elements (16-Bit) ............................. 6-75
`vmaxsw(cid:209)Maximum of Four Signed Integer Elements (32-Bit) ............................. 6-76
`vmaxub(cid:209)Maximum of Sixteen Unsigned Integer Elements (8-Bit) ....................... 6-77
`vmaxuh(cid:209)Maximum of Eight Unsigned Integer Elements (16-Bit)......................... 6-78
`vmaxuw(cid:209)Maximum of Four Unsigned Integer Elements (32-Bit)......................... 6-79
`vmhaddshs(cid:209)Multiply-High and Add Eight Signed Integer Elements (16-Bit)....... 6-80
`vmhraddshs(cid:209)Multiply-High Round and Add Eight Signed Integer
`Elements (16-Bit)............................................................................................... 6-81
`vminfp(cid:209)Minimum of Four Floating-Point Elements (32-Bit) ................................ 6-82
`vminsb(cid:209)Minimum of Sixteen Signed Integer Elements (8-Bit) ............................. 6-83
`vminsh(cid:209)Minimum of Eight Signed Integer Elements (16-Bit)............................... 6-84
`vminsw(cid:209)Minimum of Four Signed Integer Elements (32-Bit)............................... 6-85
`vminub(cid:209)Minimum of Sixteen Unsigned Integer Elements (8-Bit)......................... 6-86
`vminuh(cid:209)Minimum of Eight Unsigned Integer Elements (16-Bit).......................... 6-87
`vminuw(cid:209)Minimum of Four Unsigned Integer Elements (32-Bit) .......................... 6-88
`vmladduhm(cid:209)Multiply-Add of Eight Integer Elements (16-Bit) ............................. 6-89
`vmrghb(cid:209)Merge Eight High-Order Elements (8-Bit)............................................... 6-90
`vmrghh(cid:209)Merge Four High-Order Elements (16-Bit).............................................. 6-91
`vmrghw(cid:209)Merge Four High-Order Elements (32-Bit)............................................. 6-92
`vmrglb(cid:209)Merge Eight Low-Order Elements (8-Bit) ................................................ 6-93
`vmrglh(cid:209)Merge Four Low-Order Elements (16-Bit) ............................................... 6-94
`vmrglw(cid:209)Merge Four Low-Order Elements (32-Bit) .............................................. 6-95
`vmsummbm(cid:209)Multiply-Sum of Integer Elements (8-Bit to 32-Bit) ........................ 6-96
`vmsumshm(cid:209)Multiply-Sum of Signed Integer Elements
`(16-Bit to 32-Bit) ............................................................................................... 6-97
`vmsumshs(cid:209)Multiply-Sum of Signed Integer Elements (16-Bit to 32-Bit) ............. 6-98
`vmsumubm(cid:209)Multiply-Sum of Unsigned Integer Elements
`(8-Bit to 32-Bit) .................................................................