SAMSUNG-1006
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`Page 1 of 340
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`SAMSUNG-1006
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`
`LITERATURE
`
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`TITLE
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`SAMSUNG-1006
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`

`
`i860™ MICROPROCESSOR FAMILY
`PROGRAMMER'S
`REFERENCE
`MANUAL
`
`1991
`
`SAMSUNG-1006
`Page 5 of 340
`
`

`
`Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
`appear in this document nor does it make a commitment to update the information contained herein.
`
`Intel retains the right to make changes to these specifications at any time, without notice.
`
`Contact your local sales office to obtain the latest specifications before placing your order.
`
`The following are trademarks of Intel Corporation and may only be used to identify Intel products:
`
`376, 4-SITE, Above, ACE51 , ACE96, ACE186, ACE196, ACE960, ActionMedia, BITBUS,
`Code Builder, COMMputer, CREDIT, Data Pipeline, DeskWare, DVI, ETOX, FaxBACK,
`Genius, i, t, i287, i386, i387, i486, i750, i860, i960, ICE, iCEL, ICEVIEW, iCS, iDBP, iDIS,
`12 1CE, iLBX, iMDDX, iMMX, Inboard, Insite, Intel, Inte1287, Inte1386, Inte1387, Inte1486,
`intelBOS, Intel Certified, Intelevision, inteligent Identifier, inteligent Programming, Intellec,
`Intellink, iOSP, iPAT, iPDS, iPSC, iRMK, iRMX, iSBC, iSBX, iSDM, iSXM, iWARP, Library
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`PR0750, PROMPT, Promware, QUEST, QueX, Quick-Erase, Quick-Pulse Programming,
`READY-LAN, RMXl80, RUPI, SatisFAXtion, Seamless, SLD, Snapln 386, SugarCube,
`SUPERCHARGER, The Computer Inside, ToolTalk, UNIPATH, UPI, VAPI, Visual Edge,
`VLSiCEL, WYPIWYF, and ZapCode.
`
`MDS is an ordering code only and is not used as a product name or trademark. MDS is a registered trademark of Mohawk
`Data Sciences Corporation.
`
`CHMOS and HMOS are patented processes of Intel Corp.
`
`Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trade(cid:173)
`mark or products.
`
`OS/2 is a trademark of IBM Corp.
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`©INTEL CORPORATION 1991
`
`SAMSUNG-1006
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`

`
`CUSTOMER SUPPORT
`
`INTEL'S COMPLETE SUPPORT SOLUTION WORLDWIDE
`Customer Support is Intel's complete support service that provides Intel customers with hardware support,
`software support, customer training, consulting services and network management services. For detailed infor(cid:173)
`mation contact your local sales offices.
`After a customer purchases any system hardware or software product, service and support become major
`factors in determining whether that product will continue to meet a customer's expectations. Such support
`requires an international support organization and a breadth of programs to meet a variety of customer needs.
`As you might expect, Intel's customer support is extensive. It can start with assistance during your development
`effort to network management. 100 Intel sales and service offices are located worldwide - in the U.S., Canada,
`Europe and the Far East. So wherever you're using Intel technology, our professional staff is within close
`reach.
`HARDWARE SUPPORT SERWCES
`Intel's hardware maintenance service, starting with complete on-site installation will boost your productivity
`from the start and keep you running at maximum efficiency. Support for system or board level products can be
`tailored to match your needs, from complete on-site repair and maintenance support to economical carry-in or
`mail-in factory service.
`Intel can provide support service for not only Intel systems and emulators, but also support for equipment in
`your development lab or provide service on your product to your end-user/customer.
`SOFfWARE SUPPORT SERWCES
`Software products are supported by our Technical Information Service (TIPS) that has a special toll free
`number to provide you with direct, ready information on known, documented problems and deficiencies, as
`well as work-arounds, patches and other solutions.
`Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Infor(cid:173)
`mation Phone Service), updates and subscription service (product-specific troubleshooting guides and
`;COMMENTS Magazine). Basic support consists of updates and the subscription service. Contracts are sold in
`environments which represent product groupings (e.g., iRMX® environment).
`NETWORK SERWCE AND SUPPORT
`Today's broad spectrum of powerful networking capabilities are only as good as the customer support provided
`by the vendor. Intel offers network services and support structured to meet a wide variety of end-user comput(cid:173)
`ing needs. From a ground up design of your network's physical and logical design to implementation, installa(cid:173)
`tion and network wide maintenance. From software products to turn-key system solutions; Intel offers the
`customer a complete networked solution. With over 10 years of network experience in both the commercial
`and Government arena; network products, services and support from Intel provide you the most optimized
`network offering in the industry.
`CONSULTING SERWCES
`Intel provides field system engineering consulting services for any phase of your development or application
`effort You can use our system engineers in a variety of ways ranging from assistance in using a new product,
`developing an application, personalizing training and customizing an Intel product to providing technical and
`management conSUlting. Systems Engineers are well versed in technical areas such as microcommunications,
`real-time applications, embedded microcontrollers, and network services. You know your application needs;
`we know our products. Working together we can help you get a successful product to market in the least
`possible time.
`CUSTOMER TRAINING
`Intel offers a wide range of instructional programs covering various aspects of system design and implementa(cid:173)
`tion. In just three to ten days a limited number of individuals learn more in a single workshop than in weeks of
`self-study. For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we
`can take our workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course
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`LAN applications.
`
`CG/CUSTSUPP/112890
`
`SAMSUNG-1006
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`SAMSUNG-1006
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`PREFACE
`
`The Intel i860™ microprocessor family delivers supercomputer performance in a single
`VLSI component. The 64-bit i860 architecture balances integer, floating point, and
`graphics performance for applications such as engineering workstations, scientific com(cid:173)
`puting, 3-D graphics, and multiuser systems. The architecture achieves high throughput
`with RISC design techniques, parallel and pipelined processing units, wide data paths,
`large on-chip caches, and fast, submicron CHMOS silicon technology. The i860 micro(cid:173)
`processor family includes:
`
`•
`
`•
`
`i860 XR Microprocessor (part number 80860XR)
`
`i860 XP Microprocessor (part number 80860XP)
`
`This book is the basic source of the detailed information that enables software designers
`and programmers to use i860 microprocessors. This book explains all programmer-visible
`features of the architecture.
`
`Even though the principal users of this Programmer's Reference Manual will be pro(cid:173)
`grammers, it contains information that is of value to systems designers and administra(cid:173)
`tors of software projects, as well. Readers of these latter categories may choose to read
`only the higher-level sections of the manual, skipping over much of the programmer(cid:173)
`oriented detail.
`
`HOW TO USE THIS MANUAL
`
`• Chapter 1, "Architectural Overview," describes the i860 microprocessors "in a nut(cid:173)
`shell" and presents for the first time the terms that will be used throughout the book.
`
`• Chapter 2, "Data Types," defines the basic units operated on by the instructions of
`the i860 microprocessor.
`
`• Chapter 3, "Registers," presents the processor's database. A detailed knowledge of
`the registers is important to programmers, but this chapter may be skimmed by
`administrators.
`
`• Chapter 4, "Addressing," presents the details of operand alignment, virtual memory,
`and on-chip caches. Systems designers and administrators may choose to read the
`introductory sections of each topic.
`
`• Chapter 5, "On-Chip Caches," explains cache operation in detail sufficient for appli(cid:173)
`cations programmers to optimize for the caches and for systems programmers to
`manage the caches correctly.
`
`• Chapter 6, "Concurrency Control," shows how the detached CCU of the i860 XP
`microprocessor supports programs designed for concurrent operations, even in a uni(cid:173)
`processor system.
`
`• Chapter 7, "Core Instructions," presents detailed information about those instruc(cid:173)
`tions that deal with memory addressing, integer arithmetic, and control flow.
`
`iii
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`PREFACE
`
`• Chapter 8, "Floating-Point Instructions," presents detailed information about those
`instructions that deal with floating-point arithmetic, long-integer arithmetic, and 3-D
`graphics support. It explains how extremely high performance can be achieved by
`utilizing the parallelism and pipelining of the i860 architecture.
`• Chapters 9 and 10, "Traps and Interrupts," deal with both systems- and applications(cid:173)
`oriented exceptions, external interrupts, writing exception handlers, saving the state
`of the processor (information that is also useful for task switching), and initialization.
`• Chapter 11, "Programming Model," defines standards for the use of many features of
`the i860 architecture. Software administrators should be aware of the need for stan(cid:173)
`dards and should ensure that they are implemented. Following the standards pre(cid:173)
`sented here guarantees that compilers, applications programs, and operating systems
`written by different people and organizations will all work together.
`• Chapter 12, "Programming Examples," illustrates the use of the i860 architecture by
`presenting short code sequences in assembly language.
`• The appendices present instruction formats and encodings, timing information, and
`summaries of instruction characteristics. These appendices are of most interest to
`assembly-language programmers and to writers of assemblers, compilers, and
`debuggers.
`
`RELATED DOCUMENTATION
`
`The following books contain additional material concerning the i860 microprocessor:
`i860™ 64-Bit Microprocessor (Data Sheet), order number 240296
`•
`i860™ XP Microprocessor (Data Sheet), order number 240874
`•
`i860™ 64-Bit Microprocessor Assembler and Linker Reference Manual, order number
`•
`240436
`i860™ 64-Bit Microprocessor Simulator and Debugger Reference Manual, order number
`240437
`i860™ Microprocessor Math Library Reference Manual, order number 464411
`
`•
`
`•
`
`NOTATION AND CONVENTIONS
`
`This manual uses special notation for symbolic representation of instructions and for
`hexadecimal numbers. A review of this notation makes the manual easier to read.
`
`Instruction Descriptions
`
`The instruction chapters contain an algorithmic description of each instruction that uses
`a notation similar to that of the Algol or Pascal languages. The metalanguage uses the
`following special symbols:
`• A ~ B indicates that the value of B is assigned to A.
`• Compound statements are enclosed between the keywords of the "if" statement (IF
`... , THEN ... , ELSE ... , FI) or of the "do" statement (DO ... , OD).
`
`iv
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`PREFACE
`
`• The operator + + indicates autoincrement addressing.
`• Register names and instruction mnemonics are printed in a contrasting typestyle to
`make them stand out from the text; for example, dirbase. Individual programming
`languages may require the use of lowercase letters.
`
`For register operands, the abbreviations that describe the operands are composed of two
`parts. The first part describes the type of register:
`
`c
`
`f
`
`One of the control registers fir, psr, epsr, dirbase, db, fsr, bear,
`ccr, pO, p1, p2, or p3
`
`One of the floating-point registers: fO through f31
`
`One of the integer registers: rO through r31
`
`The second part identifies the field of the machine instruction into which the operand is
`to be placed:
`
`srcl
`
`srclni
`
`srcls
`
`src2
`
`dest
`
`The first of the two source-register designators, which may be
`either a register or a 16-bit immediate constant or address offset.
`The immediate value is zero-extended for logical operations and is
`sign-extended for add and subtract operations (including addu and
`subu) and for all addressing calculations.
`
`Same as srcl except that no immediate constant or address offset
`vC;llue is permitted.
`
`Same as srcl except that the immediate constant is a 5-bit value
`that is zero-extended to 32 bits.
`
`The second of the two source-register designators.
`
`The destination register designator.
`
`Thus, the operand specifier isrc2, for example, means that an integer register is used and
`that the encoding of that register must be placed in the src2 field of the machine
`instruction.
`
`Other (nonregister) operands are specified by a one-part abbreviation that represents
`both the type of operand required and the instruction field into which the value of the
`operand is placed:
`
`#const
`
`const32
`
`A 16-bit immediate constant or address offset that the i860 micro(cid:173)
`processor sign-extends to 32 bits when computing the effective
`address.
`
`A 32-bit constant. Only 16 bits of the constant can be used at one
`time in any i860 microprocessor instruction. The operators 1% and
`h% select the low-order and high-order half, respectively.
`
`v
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`lbroff
`
`sbroff
`
`brx
`
`PREFACE
`
`A signed, 26-bit, immediate, relative branch offset. The offset has
`a resolution of four bytes; it does not address individual bytes.
`
`A signed, 16-bit, immediate, relative branch offset. The offset has
`a resolution of four bytes; it does not address individual bytes.
`
`A function that computes the target address by shifting the offset
`(either lbroff or sbroff) left by two bits, sign-extending it to 32 bits,
`and adding the result to the current instruction pointer plus four.
`The resulting target address may lie anywhere within the address
`space.
`
`Unless otherwise specified, floating-point operations accept single- or double-precision
`source operands and produce a result of equal or greater precision. Both input operands
`must have the same precision. The source and result precision are specified by a two(cid:173)
`letter suffix to the mnemonic of the operation, as shown in Table 0-1. In instruction
`descriptions, the following codes represent precision specifications:
`
`.p
`
`.r
`
`.V
`
`.W
`
`Precision specification .ss, .sd, or .dd (.ds not permitted). Refer
`to Table 0-1.
`
`Precision specification .ss, .sd, .ds, or .dd. Refer to Table 0-1.
`
`.sd or .dd. Refer to Table 0-1.
`
`.ss or .dd. Refer to Table 0-1.
`
`Other abbreviations include:
`
`.X
`
`.y
`
`.b (8 bits), .s (16 bits), or .I (32 bits)
`
`.I (32 bits), .d (64 bits), or .q (128 bits)
`
`mem.x( address)
`
`The contents of the memory location indicated by address with a
`size of x.
`
`PM
`
`The pixel mask, which is considered as an array of eight bits
`PM[7] .. PM[0], where PM[O] is the least-significant bit.
`
`Suffix
`
`.ss
`.sd
`.dd
`.ds
`
`Table 0-1. Precision Specification
`
`Source Precision
`
`Result Precision
`
`single
`single
`double
`double
`
`vi
`
`single
`double
`double
`single
`
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`
`PREFACE
`
`Hexadecimal Numbers
`
`Hexadecimal constants are written, according to the C language convention, with the
`prefix Ox. For example, OxOF is a hexadecimal number that is equivalent to decimal 15.
`
`RESERVED BITS AND SOFTWARE COMPATIBILITY
`
`In many register and memory layout descriptions, certain bits are marked as reserved or
`undefined. When bits are thus marked, it is essential for compatibility with future pro(cid:173)
`cessors that software not utilize these bits. Software should follow these guidelines in
`dealing with reserved or undefined bits:
`• Do not depend on the states of any reserved or undefined bits when testing the values
`of registers that contain such bits. Mask out the reserved and undefined bits before
`testing.
`• Do not depend on the states of any reserved or undefined bits when storing them in
`memory or in another register.
`• Do not depend on the ability to retain information written into any reserved or unde(cid:173)
`fined bits.
`• When updating a control register, always set the reserved and undefined bits to values
`previously retrieved from the same register.
`• When initializing memory layouts, set reserved bits to zero.
`
`NOTE
`Depending upon the values of reserved or undefined bits makes software depen(cid:173)
`dent upon the unspecified manner in which the i860 microprocessor handles
`these bits. Depending upon values of reserved or undefined bits risks making
`software incompatible with future processors that define usages for these bits.
`AVOID ANY SOFfWARE DEPENDENCE UPON THE STATE OF RESERVED
`OR UNDEFINED BITS.
`
`vii
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`
`Architectural Overview
`
`Data Types
`
`Registers
`
`Addressing
`
`On-Chip Caches
`
`Concurrency Control
`
`Core Instructions
`
`Floating-Point Instructions
`
`Traps and Interrupts (80860XR)
`
`Traps and Interrupts (80860XP)
`
`Programming Model
`
`Programming Examples
`
`II
`III
`III
`III
`II
`II
`III
`II
`II
`II
`III
`
`•
`
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`Appendix A
`Instruction Set Summary
`
`Appendix B
`Instruction Format and Encoding
`
`Appendix C
`Instruction Timings
`
`Appendix D
`Instruction Characteristics
`
`Appendix E
`Compatibility Between i860™ XR and i860™ XP
`~icroprocessors
`
`Index
`
`II
`II
`II
`II
`II
`II
`
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`TABLE OF CONTENTS
`
`CHAPTER 1
`ARCHITECTURAL OVERVIEW
`1.1 OVERVIEW ..................................................................................................................... 1-1
`1.2 INSTRUCTIONS ............................................................................................................. 1-2
`1.3 INTEGER CORE UNIT .................................................................................................... 1-5
`1.4 FLOATING-POINT UNIT
`................................................................................................ 1-5
`1.5 GRAPHICS UNIT ............................................................................................................ 1-B
`1.B MEMORY MANAGEMENT UNIT .................................................................................... 1-7
`1.7 CACHES
`.................................................................. :..................................................... 1-7
`........ .............. ..... ... ........................................... .... ...... ...... 1-8
`1.8 PARALLEL ARCHITECTURE
`1.9 SOFTWARE DEVELOPMENT ENVIRONMENT .. ....................................... ..... ......... ...... 1-9
`
`Page
`
`CHAPTER 2
`DATA TYPES
`2.1 INTE.GER ........................................................................................................................ 2-'1
`2.2 ORDINAL ........................................................................................................................ 2-1
`2.3 SINGLE-PRECISION REAL ............................................................................................ 2-1
`2.4 DOUBLE-PRECISION REAL
`........................................................................... ............... 2-2
`2.5 PIXEL
`.... ..................................... .......... ..................... ........... ........ .... ....... ........ .......... ..... 2-3
`2.B REAL-NUMBER ENCODING
`... ..... .... .......... ........ ........ ....... ...... ...................... .......... ...... 2-3
`
`CHAPTER 3
`REGISTERS
`.................................... ....... ............................. .............. ...... 3-2
`3.1 INTEGER REGISTER FILE
`3.2 FLOATING-POINT REGISTER FILE
`.............................................................................. 3-2
`3.3 PROCESSOR STATUS REGISTER
`............................................................................... 3-2
`3.4 EXTENDED PROCESSOR STATUS REGISTER ............................................................ 3-5
`3.5 DATA BREAKPOINT REGISTER .................................................................................... 3-7
`3.B DIRECTORY BASE REGISTER
`..................................................................................... 3-7
`3.7 FAULT INSTRUCTION REGISTER
`................................................................................ 3-9
`3.8 FLOATING-POINT STATUS REGISTER
`...................................................................... 3-10
`.......................................................................... 3-13
`3.9 KR, KI, T, AND MERGE REGISTERS
`3.10 BUS ERROR ADDRESS REGISTER ................. ....................................... .............. .... 3-13
`3.11 PRIVILEGED REGISTERS (808BOXP ONLy) .... ............... ............................. ......... .... 3-13
`... ............. ........ ............. 3-14
`3.12 CONCURRENCY CONTROL REGISTER (808BOXP ONLy)
`..... ... ....... .......... ........................... ......... .... 3-14
`3.13 NEWCURR REGISTER (808BOXP ONLy)
`3.14 STAT REGISTER (808BOXP ONLy) ..................... ....... ................................... ............. 3-15
`
`CHAPTER 4
`ADDRESSING
`4.1 ALIGNMENT . .................... ........ ..... ...................... ................. .......... .............. ... ......... ...... 4-2
`4.2 VIRTUAL ADDRESSING
`................................................................................................ 4-3
`4.2.1 Page Frame
`.................................. ,.......................................................... ..... ............... 4-3
`......................................................................................... ... ......... ...... 4-3
`4.2.2 Virtual Address
`4.2.3 Page Tables ........................................... ..................................... .............. ... .... ..... ...... 4-5
`4.2.4 Page-Table Entries
`..................................................................................................... 4-5
`4.2.4.1 PAGE FRAME ADDRESS
`......... ................... ...................................................... ...... 4-5
`.................................................. ........................ ...... ... ........ ............... 4':7
`4.2.4.2 PRESENT BIT
`4.2.4.3 WRITABLE AND USER BITS
`................................................................................... 4-7
`4.2.4.4 WRITE-THROUGH BIT ................... ....... ........ ....................................... .............. ...... 4-8
`4.2.4.5 CACHE DISABLE BIT ................................................. :............................................. 4-9
`
`ix
`
`SAMSUNG-1006
`Page 19 of 340
`
`

`
`TABLE OF CONTENTS
`
`Page
`4.2.4.6 ACCESSED AND DIRTY BITS .... ...... ......... ...... .................. ........... ........ ........ ..... ....... 4-9
`4.2.4.7 PAGE TABLES FOR TRAP HANDLERS ................................................................. 4-10
`4.2.4.S COMBINING PROTECTION OF BOTH LEVELS OF PAGE TABLES ..................... 4-10
`4.2.5 Address Translation Algorithm
`................................................................................. 4-10
`4.2.6 Address Translation Faults .................. ........ ....... ............... ........ ...... ....... ....... ........ ... 4-13
`
`CHAPTER 5
`ON-CHIP CACHES
`5.1 ADDRESS TRANSLATION CACHES .............................................................................. 5-1
`5.2 INTERNAL INSTRUCTION AND DATA CACHES
`.......................................................... 5-4
`5.2.1 Data Cache ........................................................................... ....... ................................ 5-6
`5.2.1.1 DATA CACHE UPDATE POLICIES .......................................................................... 5-S
`5.2.2 Instruction Cache .................................. :...................................................................... 5-9
`5.2.3 Cache Replacement Algorithm .................................................................................... 5-9
`5.2.4 Cache Consistency Protocol (SOS60XP Only)
`.......... ........ ....... ... ............... .............. 5-10
`5.2.4.1 DATA CACHE STATES (SOS60XP ONLY)
`............................................................. 5-10
`5.2.4.2 WRITE-ONCE POLICY (SOS60XP ONLy)
`.............................................................. 5-11
`5.2.4.3 LOCKED ACCESSES (SOS60XP ONLy)
`................... ............................................ 5-12
`5.3 INTERNAL CACHE CONSISTENCY ............................................................................. 5-13
`5.3.1 Bypassing Instruction and Data Caches .................................................................. 5-13
`5.3.2 Invalidating Cache Entries ......................................................................................... 5-14
`5.3.3 Flushing the Data Cache .......... ............. .............. .......... ... ....................... .................. 5-14
`5.3.4 Address Space Consistency ..................................................................................... 5-14
`5.3.5 Instruction Cache Consistency .................................................................................. 5-15
`5.3.6 Page Table Consistency
`.......................................................................................... 5-16
`5.3.7 Consistency of Cacheability ..................................................................................... 5-17
`5.3.S Protection Consistency .................................................................. .... ........................ 5-17
`5.3.9 Load Pipe Consistency.............................................................................................. 5-17
`5.3.10 Summary ............................................................................. .................................... 5-1S
`
`CHAPTER 6
`CONCURRENCY CONTROL
`6.1 DETACHED CCU ........................................................................................................... 6-1
`6.2 DCCU INITIALIZATION
`.................................................................................................. 6-1
`6.3 DCCU ADDRESSING . ... ............ ..... ....... ... ........................... ....................... .... ............ .... 6-2
`6.4 DCCU INTERNALS
`....... ............ .... ........... ... .................. ...... ....................... .... ................ 6-2
`6.5 DCCU PROGRAMMING
`................................................................................................ 6-3
`
`CHAPTER 7
`CORE INSTRUCTIONS
`7.1 LOAD INTEGER ............................................................................................................. 7-2
`7.2 STORE INTEGER
`.......................................................................................................... 7-3
`7.3 TRANSFER INTEGER TO F-P REGISTER
`.................................................................... 7-4
`7.4 LOAD FLOATING-POINT ............................................................................................... 7-5
`7.5 STORE FLOATING-POINT ............................................................................................. 7-7
`7.6 PIXEL STORE
`................................................................................................................ 7-S
`7.7 INTEGER ADD AND SUBTRACT ................................................................................... 7-9
`7.S SHIFT INSTRUCTIONS ................................................................................................ 7-11
`7.9 SOFTWARE TRAPS
`..................................................................................................... 7-12
`7.10 LOGICAL INSTRUCTIONS
`.............................................