(12) United States Patent
`D’Arrigo et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,218,820 B1
`Apr. 17, 2001
`
`US006218820B1
`
`(54) FREQUENCY TRANSLATOR USABLE IN A
`SWITCHING DC-DC CONVERTER OF THE
`TYPE OPERATING AS AVOLTAGE
`REGULATOR AND AS A BATTERY
`CHARGER, AND METHOD OF FREQUENCY
`TRANSLATION THEREFOR
`
`(75) Inventors: Angelo D’Arrigo, Catania; Salvatore
`Capici, Barrafranca; Filippo Marino,
`Tremestieri Etneo; Francesco
`Pulvirenti, Acireale, all of (IT)
`
`4/1995 Nonnenmacher .................... .. 363/21
`5,408,402
`5,465,201 * 11/1995 Cohen ....... ..
`363/56 X
`5,490,055 * 2/1996 Boylan et a1.
`. 323/285 X
`5,612,858
`3/1997 Weinmeier et a1. ................. .. 363/21
`
`* cited by examiner
`
`Primary Examiner—Jessica Han
`(74) Attorney, Agent, or Firm—Theodore E. Galanthay;
`Robert Iannucci; Seed IP LaW Group PLLC
`
`(73) Assignee: STMicroelectronics S.r.l., Agrate
`
`(57)
`
`ABSTRACT
`
`BrianZa (IT)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U_S,C, 154(b) by 0 days,
`
`(21) App1_ No; 09/568,609
`_
`May 10’ 2000
`(22) Flled:
`(30)
`Foreign Application Priority Data
`
`(EP) ............................................... .. 99830285
`May 10, 1999
`(51) Int. Cl.7 ............................. .. G05F 1/40; GOSF 1/573
`(52) US. Cl. ........................ .. 323/285; 323/284; 323/276;
`363/56
`(58) Field Of Search ................................ .. 363/50, 55, 56;
`323/276, 277, 280, 284, 285, 288
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`.
`.
`.
`.
`A frequency translator is usable in a switching DC-DC
`Converter of the type Operating as a Voltage regulator and as
`a battery charger. The frequency translator receives at inputs
`a division voltage (VFB) proportional to a present value of
`the output voltage (VOUT) of the DC-DC converter, a
`reference voltage (VREF) correlated to a nominal value of
`the output voltage (VOUT), and a limiting signal (VL)
`indicative of a normal operation or of current limitation
`operation of the DC-DC converter, and supplies at an output
`a bias current (IBIAS) Which is supplied to an input of an
`Oscillator Supplying at an Output a Comparison Signal (VC)
`Presenting a Periodic Pattern With a frequency Which is
`eerreleted to the bias eurreht (IBIAS) In particular, the
`frequency translator operates in a Way such as to regulate a
`frequehey translation of the eempariseh Signal (VC) as a
`function of the difference betWeen the division voltage
`(VFB) and the reference voltage (VREF) only When the
`DC-DC converter is operating in the current limitation
`condition.
`
`4,975,823
`
`12/1990 Rilly et a1. ........................... .. 363/56
`
`20 Claims, 6 Drawing Sheets
`
`v
`
`OSCILLATOR
`1
`
`IBIAS
`
`[1,40
`/ 28
`
`70
`
`/
`
`VH3
`
`VREF
`
`[BIAS
`
`720
`
`72 \
`
`\
`
`+
`
`._
`
`8O
`
`IREFI
`
`_
`
`76
`
`In‘
`
`72 c
`
`'7“
`
`Wm
`
`"T 78
`
`V,
`
`f /
`
`74
`
`72a
`
`\IFB
`
`x
`
`7D
`
`72b
`
`WAC-1022
`
`

`
`U.S. Patent
`
`Apr. 17, 2001
`
`Sheet 1 0f 6
`
`US 6,218,820 B1
`
`mm 1
`
`f9 MN . 2%
`
`3
`
`mm .0
`
`ww
`
`11
`
`or
`
`Jmm
`
`bbw 35a
`
`

`
`U.S. Patent
`
`Apr. 17, 2001
`
`Sheet 2 0f 6
`
`US 6,218,820 B1
`
`\E, Bi 1|;
`
`NE 2
`
`*1. A130
`
`N
`
`
`
`Illa z;
`
`E -
`
`1.1. .. E‘
`
`\ t>
`
`2w 0 9 W2 8\ w / @../.
`ON NW Q mmlmy
`
`in @N ... Om _|
`
`
`
`50> . - F
`
`+ IIHE>
`
`I ml;
`
`“mg +
`
`

`
`U.S. Patent
`
`Apr. 17, 2001
`
`Sheet 3 0f 6
`
`US 6,218,820 B1
`
`um”;
`
`nmw
`
`“mg mu; 2\
`mmw
`
`\S, Bi
`
`\ mm
`
`0mm
`
`

`
`U.S. Patent
`
`Apr. 17, 2001
`
`Sheet 4 0f 6
`
`US 6,218,820 B1
`
`on
`
`ml;
`
`on
`
`if
`
`nmw FR
`
`51> v \ 1;
`
`
`
`2 h TH:
`ow
`
`,
`
`mm
`
`mm 1W 5; 0.0 U mm
`
`F; mmw
`
`25.
`
`4
`
`Hz; *
`
`22
`
`:mK mw
`
`

`
`U.S. Patent
`
`Apr. 17, 2001
`
`Sheet 5 0f 6
`
`US 6,218,820 B1
`
`3.1 1 n? \g .1
`
`

`
`U.S. Patent
`
`Apr. 17, 2001
`
`Sheet 6 6f 6
`
`US 6,218,820 B1
`
`Fig.6
`
`we
`
`VA
`
`10 j
`
`+1
`
`F |g.7 W
`
`‘
`
`£6‘ '
`
`'
`
`'
`
`'
`
`'
`
`‘
`
`I
`
`IBIAS 1
`
`£10100 1
`
`4
`
`q
`
`4
`
`<
`
`M111
`
`Fig.8
`
`Fig.9
`
`Fig.1O
`
`Fig.“
`
`Fig.12
`
`1
`
`~
`
`-
`
`'
`
`T"
`
`1
`
`.
`
`H
`
`I
`
`1
`
`r
`
`1
`
`r
`
`T
`
`r 00
`
`I
`q
`
`..
`
`.
`
`r
`
`I
`
`1
`
`I
`
`r
`
`I
`
`U
`
`I
`
`I
`
`;
`
`1
`
`H
`
`>
`
`t
`
`.. -\/\//
`
`

`
`US 6,218,820 B1
`
`1
`FREQUENCY TRANSLATOR USABLE IN A
`SWITCHING DC-DC CONVERTER OF THE
`TYPE OPERATING AS A VOLTAGE
`REGULATOR AND AS A BATTERY
`CHARGER, AND METHOD OF FREQUENCY
`TRANSLATION THEREFOR
`
`TECHNICAL FIELD
`The present invention refers to a frequency translator
`usable in a switching DC-DC converter of the type operating
`as a voltage regulator and as a battery charger, and to a
`method of frequency translation therefor.
`
`10
`
`BACKGROUND OF THE INVENTION
`
`2
`function of the voltage supplied by the voltage error ampli
`?er 28, and the frequency Whereof depends upon the fre
`quency of the comparison voltage VC supplied by the
`oscillator 32.
`Finally, the DC-DC converter 1 comprises a ?Xed thresh
`old current limiting stage having the purpose of protecting
`the DC-DC converter 1 against current overloads and basi
`cally consisting of a differential comparator 34, hereinafter
`indicated as CURL comparator, presenting an inverting
`terminal and a non-inverting terminal connected across the
`sense resistor 14 and an output terminal issuing a limiting
`signal VL supplied to the driving stage 10; in particular, the
`CURL comparator 34 carries out the comparison betWeen
`the voltage present across the sense resistor 14 and a preset
`reference voltage programmed inside it: if the voltage
`present across the sense resistor 14 is less than or equal to
`the reference voltage programmed inside it, then the limiting
`signal VL sWitches to a loW logic level indicative of the
`absence of overloads, and the driving stage 10 continues to
`operate in a normal Way, controlling opening and closing of
`the sWitches 6 and 8 at a nominal sWitching frequency
`correlated to the frequency of the comparison voltage VC
`supplied by the oscillator 32, Whereas if the voltage present
`across the sense resistor 14 is greater than the reference
`voltage programmed inside it, then the limiting signal VL
`sWitches to a high logic level indicative of the presence of
`overloads, and, in response to the sWitching of the limiting
`signal VL from the loW logic level to the high logic level, the
`driving stage 10 controls opening of the sWitches 6 and 8, so
`as to interrupt the current supplied to the DC-DC converter
`1.
`
`The opening of the sWitch 8 causes the voltage across the
`sense resistor 14 to become Zero, and thus causes the
`limiting signal VL generated by the CURL comparator 34 to
`sWitch again to the loW logic level, and consequently the
`driving stage 10 to return to conditions of normal operating.
`As a result, as long as the overload persists, the limiting
`signal VL supplied by the CURL comparator 34 continues to
`sWitch betWeen the high and loW logic levels, thus gener
`ating a pulse train Which, When supplied to the driving stage
`10, causes sWitching of the operation of the DC-DC con
`verter 1 betWeen a normal operation, in Which opening and
`closing of the sWitches 6 and 8 is controlled at a preset
`frequency correlated to that of the saWtooth voltage supplied
`by the PWM comparator 30, and an current limitation
`operation, in Which opening of the sWitches 6 and 8 is
`controlled in order to interrupt the current supplied to the
`DC-DC converter 1.
`The operation of the DC-DC converter 1 is in itself knoWn
`and Will here be referred to solely as regards the aspects
`necessary for understanding the problems lying at the basis
`of the present invention. In particular, the DC-DC converter
`1 presents a single operating mode in Which the voltage error
`ampli?er 28 carries out regulation of the output voltage
`VOUT so that this remains constant as the current required
`by the load connected to the output terminal of the DC-DC
`converter 1 varies.
`In FIG. 2 there is illustrated and indicated by 40 a knoWn
`step-doWn DC-DC converter usable as a battery charger, in
`Which identical parts or parts equivalent to the ones of the
`DC-DC converter 1 are designated With the same reference
`numbers.
`In particular, the DC-DC converter 40 differs from the
`DC-DC converter 1 by further comprising a sense resistor 42
`connected in series to the inductor 16 and interposed
`betWeen the inductor 16 and the output terminal 4 of the
`
`15
`
`25
`
`FIG. 1 illustrates, and indicates as a Whole by the refer
`ence number 1, a knoWn step-doWn DC-DC converter
`usable as a voltage regulator. In particular, to provide an
`eXample, in FIG. 1 a DC-DC converter is illustrated having
`a Buck circuit con?guration; hoWever, this should not be
`deemed limiting, in that considerations altogether similar to
`the ones that are made in What folloWs for this type of circuit
`con?guration also apply to DC-DC converters having Boost
`and Flyback circuit con?gurations.
`According to What is illustrated in FIG. 1, the DC-DC
`converter comprises an input terminal 2, set, When in use, at
`an input voltage VIN, and an output terminal 4 supplying an
`output voltage VOUT loWer than the input voltage VIN.
`The DC-DC converter 1 comprises a ?rst and a second
`sWitch 6, 8, typically formed of bipolar transistors or
`p-channel or n-channel MOSFET transistors, the opening
`and closing Whereof are controlled in phase by a driving
`stage 10. In particular, the ?rst sWitch 6 presents a ?rst
`terminal connected to the input terminal 2 of the DC-DC
`converter 1, and a second terminal connected, via a diode 12,
`to ground, Whilst the second sWitch 8 presents a ?rst
`terminal also connected to the input terminal 2 of the
`DC-DC converter 1 via a sense resistor 14, and a second
`terminal connected, via the diode 12, to ground.
`The DC-DC converter 1 further comprises an inductor 16
`connected betWeen the second terminals of the sWitches 6
`and 8 and the output terminal 4; a capacitor 18 connected
`betWeen the output terminal 4 and ground; and a voltage
`divider 20 formed of tWo resistors 22, 24 connected betWeen
`the output terminal 4 and ground and presenting an inter
`mediate node 26 on Which a division voltage VFB is present,
`Which is proportional, through the division ratio, to the
`output voltage VOUT supplied by the DC-DC converter 1.
`The DC-DC converter 1 moreover comprises a differen
`tial voltage error ampli?er (VEA) 28 presenting an inverting
`terminal connected to the intermediate node 26 of the
`voltage divider 20 and receiving from the latter the division
`voltage VFB, a non-inverting terminal receiving a reference
`voltage VREF, and an output terminal supplying an inter
`mediate voltage VM and connected to a non-inverting
`55
`terminal of a differential comparator 30, knoWn as PWM
`(Pulse Width Modulator) comparator, and hereinafter indi
`cated by this name, Which in turn presents an inverting
`terminal connected to the output terminal of an oscillator 32
`supplying a comparison voltage VC presenting a saWtooth
`Waveform and having a preset frequency upon Which the
`sWitching frequency of the DC-DC converter 1 depends, and
`an output terminal connected to the input of the driving stage
`10 of the sWitches 6 and 8.
`In particular, the PWM comparator 30 basically acts as a
`pulse Width modulator and supplies at an output a voltage
`having a square Waveform, the duty cycle Whereof is a
`
`35
`
`45
`
`65
`
`

`
`US 6,218,820 B1
`
`10
`
`15
`
`25
`
`35
`
`3
`DC-DC converter 40; a ?ltering stage 44, made typically
`using an operational ampli?er and presenting a ?rst input
`terminal and a second input terminal connected across the
`sense resistor 42, and an output terminal supplying a voltage
`equal to the ?ltered voltage VFR present across the sense
`resistor 42; and a differential current error ampli?er (CEA)
`46 presenting an inverting terminal connected to the output
`terminal of the ?ltering stage 44, a non-inverting terminal
`receiving a reference voltage VR, and an output terminal
`connected to the inverting terminal of the PWM comparator
`30 through a decoupling diode 48, Which presents the anode
`terminal connected to the inverting terminal of the PWM
`comparator 30 and the cathode terminal connected to the
`output terminal of the current error ampli?er 46.
`In particular, the reference voltage VR is generated by
`causing a constant current, supplied by a current generator
`52 connected in series to a resistor 50, to How in the resistor
`50 itself; the reference voltage thus obtained is then taken
`across the resistor 50.
`The operation of the DC-DC converter 40 is in itself
`knoWn and Will here be referred to solely as regards the
`aspects necessary for understanding the problems lying at
`the basis of the present invention. In particular, it is pointed
`out that the DC-DC converter 40 presents tWo operating
`modes. A ?rst operating mode is that in Which the current
`error ampli?er prevails over the voltage error ampli?er and
`carries out regulation of the battery charging current, during
`Which the charging current is constant at the programmed
`value and the voltage present across the battery increases
`from the initial value, typically Zero, to its full charge value,
`Whereas the second operating mode is that in Which the
`voltage error ampli?er prevails over the current error ampli
`?er and carries out regulation of the voltage of the battery,
`during Which the charging current decreases until it goes to
`Zero and the battery voltage remains ?Xed at the full charge
`value.
`Both of the DC-DC converters described above present a
`draWback due to the fact that the time of intervention of the
`CURL comparator 34 for limiting the current supplied by the
`DC-DC converters When overloads are present at output (for
`eXample, upon sWitching-on of the DC-DC converters When
`the capacitor 18 must be charged) is not Zero and depends on
`the response time With Which the DC-DC converters react to
`such variations.
`Consequently, in the cases Where heavy overloads or short
`circuits at output, or else at sWitching-on, occur, the CURL
`45
`comparator 34 by itself does not suf?ce to limit the output
`current in that, in these conditions, the inductor 16 is charged
`With a current having a slope greater than the slope With
`Which it is discharged, thus leading to a divergence of the
`output current.
`In the literature there eXist various methods for creating a
`current limitation system that is effective against short
`circuits and overloads.
`A very Well knoWn method is based upon the so-called
`principle of frequency translation, i.e., based upon the
`reduction of the sWitching frequency of the DC-DC con
`verter in the presence of overloads or short circuits, that is
`upon the reduction of the sWitching frequencies of the
`sWitches 6 and 8.
`In FIG. 3 there is illustrated and designated by 60 a
`frequency translation DC-DC converter, usable as a voltage
`regulator.
`The DC-DC converter 60 presents a circuit topology very
`similar to that of the DC-DC converter 1; for this reason,
`identical parts or parts equivalent to those of the DC-DC
`converter 1 Will be identi?ed With the same reference
`numbers.
`
`55
`
`65
`
`4
`The DC-DC converter 60 differs from the DC-DC con
`verter 1 by further comprising a frequency translator 62
`presenting a pair of input terminals 62a, 62b connected to
`the inverting and non-inverting terminals of the voltage error
`ampli?er 28 and receiving, respectively, the division voltage
`VFB and the reference voltage VREF, and an output termi
`nal 62u issuing a translation regulating signal supplied to an
`input terminal of the oscillator 32 and consisting of a bias
`current IBIAS for the oscillator 32 itself, Which is designed
`so as to supply at an output a comparison voltage VC of a
`saWtooth or triangular Waveform, the frequency Whereof is
`proportional to the bias current IBIAS.
`The operation of the DC-DC converter 60 is in itself
`knoWn and Will here be referred to solely as regards the
`aspects necessary for understanding the problems lying at
`the basis of the present invention. In particular, in conditions
`of short circuit or sWitching-on of the DC-DC converter 60,
`the output voltage VOUT is initially Zero, in that the
`capacitor 18 is discharged, the bias current IBIAS supplied
`to the oscillator 32 assumes a minimum value, the compari
`son voltage VC supplied by the oscillator 32 consequently
`assumes a minimum value, and hence the sWitching fre
`quency of the sWitches 6 and 8, Which is controlled by the
`driving stage 10 and is in turn a function of the frequency of
`the comparison voltage VC, also assumes its minimum
`value.
`As the output voltage VOUT increases, the bias current
`IBIAS increases accordingly, and the sWitching frequency of
`the sWitches 6, 8 tends to go to its nominal value.
`A frequency translator 62 of the type described above is
`not, hoWever, usable in the DC-DC converter 40 operating
`as a battery charger on account of the presence of the dual
`operating mode, i.e., as a current regulator and as a voltage
`regulator, of the DC-DC converter 40.
`In fact, in both operating modes, under normal operating
`conditions, the DC-DC converter 40 should function at the
`nominal sWitching frequency; instead, With the frequency
`translation modality illustrated in FIG. 3 this is not possible
`in that, during the current regulation operating mode, since
`the output voltage VOUT varies from the Zero value to the
`nominal value, the frequency translator 62 Would control
`translation of the sWitching frequency of the DC-DC con
`verter 40 even though no overload is present at output.
`
`SUMMARY OF THE INVENTION
`An embodiment of the present invention provides a
`frequency translator usable in a sWitching DC-DC converter
`of the type operating as a voltage regulator and as a battery
`charger.
`Another embodiment of the present invention provides a
`frequency translation method that may be used in a sWitch
`ing DC-DC converter of the type operating as a voltage
`regulator and as a battery charger.
`Another embodiment of the present invention provides a
`sWitching DC-DC converter operating as a voltage regulator
`and as a battery charger.
`According to embodiments of the present invention dis
`closed herein, a limiting signal VL is supplied to the
`frequency translator in such a Way as it may control the
`translation of the frequency of a comparison signal VC as a
`function of the difference betWeen a reference voltage VREF
`and a division voltage VFB solely When the DC-DC con
`verter is operating in a current limiting condition. In this
`Way, the frequency translator may be used also in DC-DC
`converters operating as battery chargers, in that, during the
`current limiting condition, the limiting signal VL is Zero and
`inhibits frequency translation.
`
`

`
`US 6,218,820 B1
`
`5
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`For a better understanding of the present invention, a
`preferred embodiment thereof is noW described, simply With
`the purpose of providing a non-limiting example, With
`reference to the attached draWings, in Which:
`FIG. 1 shoWs a circuit diagram of a knoWn DC-DC
`converter usable as a voltage regulator.
`FIG. 2 shoWs a circuit diagram of a knoWn DC-DC
`converter usable as a battery charger.
`FIG. 3 shoWs a circuit diagram of a knoWn DC-DC
`converter usable as a voltage regulator and provided With a
`knoWn frequency translator.
`FIG. 4 shoWs a circuit diagram of a frequency translator
`usable in a DC-DC converter of the type operating as a
`voltage regulator and as a battery charger.
`FIG. 5 shoWs a more detailed circuit diagram of the
`frequency translator of FIG. 4.
`FIGS. 6—12 shoW patterns of electrical quantities of the
`frequency translator of FIG. 5.
`
`10
`
`15
`
`6
`second current generator 78 receiving at an input the current
`limiting signal VINT and supplying a limitation current IF
`Which is variable and correlated to the current limiting signal
`VINT; and a subtracting stage 79 receiving at an input the
`reference current IREF and the limitation current IF and
`supplying at an output the bias current IBIAS for the
`oscillator 32 equal to the difference betWeen the current
`IREF and the current IF.
`In particular, the reference current IREF supplied by the
`?rst current generator 76 presents an amplitude such that, if
`supplied to the oscillator 32 as bias current, it Would
`determine the generation of a comparison voltage VC hav
`ing nominal frequency, Whilst the limitation current IF
`supplied by the second current generator 78 is proportional
`to the amplitude of the current limiting signal VINT and
`ranges betWeen a minimum value of Zero to a maXimum
`value loWer than the value of the reference current IREF.
`The operation of the frequency translator 72 is as folloWs.
`In normal operating conditions, i.e., in the absence of
`overloads or short circuits, or folloWing upon sWitching-on
`of the DC-DC converter, the limiting signal VL is Zero, the
`current limiting signal VINT is Zero, the limitation current IF
`is Zero, and hence the bias current IBIAS is equal to the
`reference current IREF.
`In these conditions, therefore, the frequency of the com
`parison signal VC, and consequently the sWitching fre
`quency of the DC-DC converter, is the nominal one deter
`mined in the design phase.
`In conditions of overload, such as short circuits at output,
`or else upon sWitching-on, the DC-DC converter 70 enters
`the current limitation phase, and this condition is detected by
`the CURL comparator 34, Which supplies at an output a
`limiting signal VL on Which there is present a pulse train
`indicative of this condition.
`The integrating stage 74 carries out integration of the
`limiting signal VL Weighted With the term (1-VFB/V REF)
`and generates at an output the current limiting signal VINT
`Which is supplied to the current generator 78, Which gener
`ates at an output a limitation current IF proportional to the
`current limiting signal VINT.
`In the subtracting stage 79, the current IF is subtracted
`from the current IREF, thus generating a bias current IBIAS
`smaller than the reference current IREF, Which, When sup
`plied to the oscillator 32, determines a reduction in the
`frequency of the comparison voltage VC, and hence in the
`sWitching frequency of the DC-DC converter.
`The term (1-VFB/NVREF) eXpresses the dependence of
`the sWitching frequency of the DC-DC converter 70 upon
`the output voltage VOUT; since, in fact, the division voltage
`VFB ranges in use betWeen a Zero value and a value equal
`to that of the reference voltage VREF, the term (1-VFB/
`NVREF) accordingly varies betWeen a value of unity and a
`value of Zero. As the output voltage VOUT varies betWeen
`Zero and its steady state value, the division voltage VFB
`increases from the Zero value to a value equal to that of the
`reference voltage VREF, the term (1-VFB/V REF) decreases
`from 1 to 0, the current limiting signal VINT decreases until
`it Zeroes Whatever the value of the limiting signal VL, and
`hence the limitation current IF decreases until it Zeroes, thus
`determining the increase in the frequency of the comparison
`voltage VC, and consequently of the sWitching frequency of
`the DC-DC converter 70 from its minimum value to its
`nominal value.
`This prevents latch-up phenomena, i.e., phenomena in
`Which the output voltage VOUT gets blocked at a value
`loWer than the nominal value, Which may occur upon
`sWitching-on if the sWitching frequency is initially loWer
`than the nominal frequency.
`
`25
`
`35
`
`DETAILED DESCRIPTION
`In FIG. 4 there is illustrated, and indicated by 72, a
`frequency translator made according to an embodiment of
`the present invention and usable in a DC-DC converter,
`indicated by 70, of the type operating as a voltage regulator
`and as a battery charger. In particular, in FIG. 4 all the
`remaining circuit structure of the DC-DC converter 70 that
`may indifferently be either that of the DC-DC converter 1 or
`that of the DC-DC converter 40 previously described is
`shoWn schematically as a rectangle indicated by the refer
`ence numbers 1, 40, in Which only the components neces
`sary for the understanding of the present invention are
`shoWn.
`In particular, the frequency translator 72 presents, in
`addition to the input terminals, indicated in the ?gure by 72a
`and 72b, receiving the division voltage VFB and the refer
`ence voltage VREF, also a third input terminal, indicated by
`72c, receiving from the CURL comparator 34 the limiting
`signal VL indicative of normal operation or of current
`limitation operation of the DC-DC converter 70 and controls
`a translation of the frequency of the comparison voltage VC
`supplied by the oscillator 32 as a function of the difference
`betWeen the reference voltage VREF and the division volt
`45
`age VFB only When the DC-DC converter 70 is in current
`limitation operation, i.e., only if on the limiting signal VL
`there is present the pulse train that is indicative of this
`operating condition.
`In this Way, the frequency translator 72 can be used also
`in DC-DC converters operating as battery chargers. In fact,
`during the current regulation phase, in Which the output
`voltage VOUT increases from Zero to its steady state value,
`the limiting signal VL assumes a Zero value, and thus
`prevents carrying out of the frequency translation of the
`comparison voltage VC during this phase.
`As shoWn in FIG. 4, the frequency translator 72 comprises
`an integrating stage 74 receiving at the inputs the division
`frequency VFB, the reference voltage VREF and the limit
`ing signal VL, and supplying at an output a current limiting
`signal VINT obtained as folloWs:
`
`55
`
`VINT:fVm)'(1_ VREF
`
`VREF
`
`The frequency translator 72 further comprises a ?rst current
`generator 76 supplying a constant reference voltage IREF; a
`
`65
`
`

`
`US 6,218,820 B1
`
`7
`FIG. 5 shows in detail the circuit diagram of the frequency
`translator 72, in Which parts that are identical or equivalent
`to those of FIG. 4 are identi?ed by the same reference
`numbers.
`According to What is illustrated in this ?gure, the fre
`quency translator 72 comprises a supply line 80 set at the
`voltage VCC; an input differential stage 81 formed of a pair
`of PMOS transistors 82, 83 having the same dimensions and
`having gate terminals receiving, respectively, the reference
`voltage VREF and the division voltage VFB, drain terminals
`connected to respective internal nodes 84, 85, and source
`terminals connected, respectively, to one of tWo NMOS
`transistors 86, 87 forming a current mirror 88, and to ground.
`In particular, the transistors 86, 87 have source terminals
`connected to ground and gate terminals connected together
`via a resistor 89. In addition, the transistor 86 constitutes the
`load of the transistor 82 and is diode-connected, i.e., it has
`the drain terminal connected to its oWn gate terminal, Whilst
`the transistor 87 has the gate terminal connected to ground
`via a capacitor 90 and supplies on its oWn drain terminal the
`bias current IBIAS for the oscillator 32.
`BetWeen the supply line 80 and the node 84 is connected
`the current generator 76 supplying the reference voltage
`IREF, Whilst betWeen the supply line 80 and the node 85 is
`connected a current generator 91 supplying a constant
`current I0 equal to the reference current IREF. The current
`generators 76 and 91 are in practice made by means of a
`single current mirror provided With tWo repeating branches.
`BetWeen the nodes 84 and 85 there is moreover connected
`a netWork formed of a resistor 94, tWo capacitors 95, 96 and
`tWo sWitches, 97, 98, made, for eXample, using NMOS
`transistors. In particular, the resistor 94 is connected
`betWeen the node 84 and one node 99; the capacitor 95 is
`connected betWeen the node 99 and ground; the sWitch 97 is
`connected between the node 99 and one node 100; the
`capacitor 96 is connected betWeen the node 100 and ground;
`and ?nally the sWitch 98 is connected betWeen the node 100
`and the node 85.
`The sWitches 97 and 98 are controlled in counterphase,
`and in particular the sWitch 97 is controlled by the inverted
`limiting signal W obtained by inverting, via an inverter
`101, the limiting signal VL supplied on the input terminal
`72c, Whilst the sWitch 98 is controlled by the limiting signal
`VL obtained by inverting, via an inverter 102, the inverted
`limiting signal W supplied by the inverter 101.
`The resistor 94, the capacitors 95, 96, and the sWitches 97,
`98 form the integrating stage 74, Whilst the transistors 82, 83
`implement the relation VREF-VFB to be used in the inte
`gration.
`Operation is as folloWs. When the DC-DC converter is not
`in the current limitation phase, the limiting signal VL is at
`a loW logic level and the negated limiting signal W is at a
`high logic level; consequently, the sWitch 97 is closed and
`the sWitch 98 is open, the capacitors 95 and 96 are parallel
`connected and, via the resistor 94, are charged to the voltage
`present on the node 84.
`In this situation, the bias current IBIAS supplied to the
`oscillator 32 is equal to the reference current IREF, and the
`sWitching frequency of the DC-DC converter 70 is equal to
`its nominal value.
`When a condition of overload occurs, the DC-DC con
`verter 70 enters the current limitation phase, and hence the
`limiting signal VL sWitches to the high logic level, thus
`driving opening of the sWitch 97 and closing of the sWitch
`98. The capacitor 96 is thus discharged until the voltage
`across it is equal to the voltage on the node 85, Which is
`equal to VFB+VGS, Where VGS is the voltage present
`betWeen the gate terminal and the source terminal of the
`transistor 83.
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`8
`The voltage of the node 85 is loWer than the voltage of the
`node 84 in that, since the DC-DC converter 70 is in an
`overload condition, and hence out of regulation, the division
`voltage VFB is loWer than the reference voltage VREF.
`When the limiting signal VL sWitches again to the loW
`logic level, the sWitch 97 closes and the sWitch 98 opens, and
`thus the capacitor 95 is discharged on the capacitor 96, so
`causing the voltage of the node 99 and that of the node 84
`to decrease.
`If the capacitor 96 is designed so that its capacitance is
`suf?ciently small as compared to that of the capacitor 95,
`then as the successive pulses present on the limiting signal
`VL are sent to the sWitches 97 and 98, the consequent phases
`of charging and discharging of the capacitors 95 and 96 Will
`bring about integration of the pulses, causing the voltage of
`the node 84 to decrease continuously starting from its initial
`value doWn to a loWer value.
`The transistor 82 Will thus present a voltage VGS increas
`ingly smaller, and hence the current ?oWing in the transistor
`Will be IREF-IF, and this Will translate the sWitching fre
`quency to its minimum value.
`FIGS. 6 to 9 shoW the effects of an overload on the bias
`current IBIAS and on the sWitching frequency of the DC-DC
`converter.
`In particular, as may be noted, in the case of an overload
`that occurs at the instant of time indicated in the ?gure by to,
`the division voltage VFB decreases rapidly to a very small
`value folloWing a substantially step-like pattern, as shoWn in
`FIG. 6; the voltage VA present on the node 84 decreases
`folloWing the pattern shoWn in FIG. 7; and the bias current
`IBIAS decreases progressively folloWing the pattern shoWn
`in FIG. 8.
`FIG. 9, instead, illustrates the decrease in the clock
`frequency FCK With Which the oscillator 32 operates inter
`nally folloWing upon a condition of overload. The frequency
`of the saWtooth comparison voltage VC supplied as output
`from the oscillator 32 Will consequently undergo a reduction
`similar to that of the clock frequency illustrated in FIG. 9.
`FIGS. 10, 11 and 12 shoW, respectively, the pattern of the
`division voltage VFB, the bias current, and the clock fre
`quency of the oscillator 32 from the instant, indicated by t1,
`in Which the overload condition ceases.
`It should be noted that the minimum value of the clock
`frequency FCK of the oscillator 32, and hence of the
`comparison voltage VC supplied by the oscillator, and the
`degree of continuity With Which the said frequency and
`voltage go back to their nominal values depend upon the
`resistance of the resistor 94 and upon the capacitance of the
`capacitors 95 and 96. In particular, the smaller the capaci
`tance of the capacitor 96 as compared to the capacitance of
`the capacitor 95, the more gradual the transition.
`The resistor 89 and the capacitor 90 de?ne a ?lter having
`the purpose of avoiding an excessive ripple of the bias
`current IBIAS of the oscillator 32.
`From an examination of the characteristics of the fre
`quency translator 72 made according to the present
`invention, the advantages that the frequency translator
`makes possible are