`571-272-7822
`
`
`Paper No. 6
` Entered: December 3, 2015
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SONY CORPORATION,
`Petitioner,
`
`v.
`
`RAYTHEON COMPANY,
`Patent Owner.
`____________
`
`Case IPR2015-01201
`Patent 5,591,678
`____________
`
`
`
`Before JO-ANNE M. KOKOSKI, JENNIFER MEYER CHAGNON, and
`JEFFREY W. ABRAHAM Administrative Patent Judges.
`
`CHAGNON, Administrative Patent Judge.
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`I.
`
`INTRODUCTION
`
`Sony Corporation (“Petitioner”) filed a Petition for inter partes review
`
`of claims 1–18 (“the challenged claims”) of U.S. Patent No. 5,591,678
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`(Ex. 1001, “the ’678 patent”). Paper 2 (“Pet.”). Raytheon Company
`
`(“Patent Owner”) timely filed a Preliminary Response. Paper 5 (“Prelim.
`
`Resp.”).
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`Patent 5,591,678
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`We have authority to determine whether to institute inter partes
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`review. See 35 U.S.C. § 314(b); 37 C.F.R. § 42.4(a). Upon consideration of
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`the Petition and the Preliminary Response, and for the reasons explained
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`below, we determine that the information presented shows a reasonable
`
`likelihood that Petitioner would prevail with respect to all of the challenged
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`claims. See 35 U.S.C. § 314(a). Accordingly, we institute trial as to
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`claims 1–18 of the ’678 patent.
`
`A. Related Proceedings
`
`The ’678 patent has been asserted in Raytheon Co. v. Samsung
`
`Electronics Co., No. 2:15-cv-00341 (E.D. Tex.), and Raytheon Co. v. Sony
`
`Kabushiki Kaisha, No. 2:15-cv-00342 (E.D. Tex.). Pet. 1; Paper 3, 2.
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`B. The ’678 Patent
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`The ’678 patent, titled “Process of Manufacturing a Microelectric
`
`Device Using a Removable Support Substrate and Etch-Stop,” relates to a
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`method of fabricating a microelectronic device, in which the microelectronic
`
`device is moved from one support to another during fabrication. Ex. 1001,
`
`1:12–13. According to the ’678 patent, “[t]he invention permits
`
`microelectronic devices to be prepared using well-established, inexpensive
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`thin-film deposition, etching, and patterning techniques, and then to be
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`further processed singly or in combination with other such devices, into
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`more complex devices.” Id. at 2:9–14. Figure 1 of the’678 patent is
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`reproduced below.
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`Figure 1 is a process flow diagram of the method of the ’678 patent,
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`schematically illustrating each stage of fabrication of a microelectronic
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`device formed in accordance with the method. Id. at 3:48–50. As shown in
`
`box 20, first substrate 40 is provided, the first substrate including etchable
`
`layer 42, etch-stop layer 44, and wafer layer 46. Id. at 3:65–4:2. As noted in
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`the ’678 patent, “[s]uch substrates can be purchased commercially,” or
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`“prepared by applying well-known microelectronic techniques.” Id. at 4:2,
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`4:22–23. In a preferred embodiment, etchable layer 42 is a layer of bulk
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`silicon, etch-stop layer 44 is a layer of silicon dioxide, and wafer layer 46 is
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`a layer of single crystal silicon. Id. at 4:3–15.
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`Microelectronic circuit element 50 is formed in wafer layer 46, as
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`shown in box 22. Id. at 4:37–52. The ’678 patent notes that “the present
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`invention is not limited to any particular circuit element 50,” and, for
`
`example, “can include many active devices such as transistors,” or “may be
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`simply a patterned electrical conductor layer that is used as an interconnect
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`between other layers of structure in a stacked three-dimensional device.”
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`Id. at 4:55–56, 4:47–51.
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`Second substrate 58 is attached to the structure, as shown in box 24.
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`Id. at 5:14–44. Second substrate 58 may comprise, for example, silicon or
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`aluminum oxide, and optionally may include a microelectronic device
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`deposited therein. Id. at 5:18–25. Etchable layer 42 is removed by etching,
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`as shown in box 26. Id. at 5:45–6:9. The entire structure may be attached
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`temporarily to base 62, which may be a piece of aluminum oxide
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`(particularly, sapphire), to protect the structure against etch attack. Id. at
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`5:47–49. As described in the ’678 patent, the “etchant is chosen so that it
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`attacks the etchable layer 42 relatively rapidly, but the etch-stop layer 44
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`relatively slowly or not at all.” Id. at 5:52–54.
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`“Back-side electrical connections are formed through the [exposed]
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`etch-stop layer 44 (for direct back-side interconnects 56’) and through the
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`etch stop layer 44 and the wafer layer [46] to the microelectronic circuit
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`element 50 (for indirect front-side interconnects [56]),” as shown in box 28.
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`Id. at 6:10–14. The connections are formed by patterning etch-stop layer 44
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`using well-known patterning techniques. Id. at 6:14–17. Electrical
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`conductor layer 70 may be deposited over etch-stop layer 44 and back side
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`electrical connections 56, 56’. Id. at 6:44–49.
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`As shown in box 30 of Figure 1, final structure 71 may be joined with
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`another microelectronic device 72, to form a three-dimensional structure
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`comprising structures 71, 72. Id. at 6:50–58, Fig. 2.
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`C. Illustrative Claim
`
`Of the challenged claims, claims 1, 11, and 13 are independent.
`
`Claims 2–10 depend, directly or indirectly, from claim 1; claim 12 depends
`
`from claim 11; and claims 14–18 depend, directly or indirectly, from
`
`claim 13. Claim 1 of the ’678 patent, reproduced below, is illustrative of the
`
`challenged claims:
`
`1. A method of fabricating a microelectronic device,
`comprising the steps of:
`
`furnishing a first substrate having an etchable layer, an
`etch-stop layer overlying the etchable layer, and a wafer
`overlying the etch-stop layer;
`
`forming a microelectronic circuit element in the exposed
`side of the wafer of the first substrate opposite to the side
`overlying the etch-stop layer;
`
`attaching the wafer of the first substrate to a second
`substrate; and
`
`etching away the etchable layer of the first substrate
`down to the etch-stop layer.
`
`Ex. 1001, 8:5–16.
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`5
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`D. The Applied References and Evidence
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`Petitioner relies on the following evidence. Pet. 2.
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`Reference
`
`Tsuneo Hamaguchi & Nobuhiro Endo,
`Novel SOI Technology Using Preferential
`Polishing, NEC Research Notes 1480 (70)
`(1987) (“Hamaguchi”)
`JP App. Pub. No. 64-18248 (“Morimoto”)
`U.S. Patent No. 5,244,534 (“Yu”)
`U.S. Patent No. 4,910,155 (“Cote”)
`U.S. Patent No. 5,064,683 (“Poon”)
`U.S. Patent No. 5,069,002 (“Sandhu”)
`U.S. Patent No. 5,189,500 (“Kusunoki”)
`U.S. Patent No. 5,066,993 (“Miura”)
`U.S. Patent No. 4,681,718 (“Oldham”)
`U.S. Patent No. 3,864,819 (“Ying”)
`U.S. Patent No. 5,202,754 (“Bertin”)
`
`Date
`
`1987
`
`Exhibit
`No.
`Ex. 10041
`
`Jan. 23, 1989 Ex. 10062
`Sept. 14, 1993 Ex. 1007
`Mar. 20, 1990 Ex. 1008
`Nov. 12, 1991 Ex. 1009
`Dec. 3, 1991
`Ex. 1010
`Feb. 23, 1993 Ex. 1011
`Nov. 19, 1991 Ex. 1012
`July 21, 1987 Ex. 1014
`Feb. 11, 1975 Ex. 1016
`Apr. 13, 1993 Ex. 1017
`
`Petitioner further relies on the Declaration of Dr. Richard A.
`
`Blanchard (Ex. 1002, “Blanchard Declaration”).
`
`E. The Asserted Grounds
`
`Petitioner sets forth its challenges to claims 1–18 as follows. Pet. 2,
`
`18–60.
`
`References
`Bertin
`Bertin and Morimoto
`Bertin and Ying
`
`Basis Claims Challenged
`§ 102
`1, 6, 7, 10, 11
`§ 103
`5, 12, 13
`§ 103
`9
`
`
`1 Hamaguchi is a Japanese-language reference (Ex. 1003). Citations to
`Hamaguchi herein are to the certified English translation submitted by
`Petitioner (Ex. 1004).
`2 Morimoto is a Japanese-language reference (Ex. 1005). Citations to
`Morimoto herein are to the certified English translation submitted by
`Petitioner (Ex. 1006).
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`References
`Morimoto and CMP/Etching
`references3
`Morimoto, CMP/Etching
`references, and Oldham
`Morimoto, CMP/Etching
`references, and Bertin
`
`II. ANALYSIS
`
`A. Claim Construction
`
`Basis Claims Challenged
`§ 103
`1, 2, 4, 5, 10, 13, 14, 16, 17
`
`§ 103
`
`8, 18
`
`§ 103
`
`3, 15
`
`The ’678 patent is expired. When interpreting claims of an expired
`
`patent, our analysis is similar to that of a district court. In re Rambus, Inc.,
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`694 F.3d 42, 46 (Fed. Cir. 2012). Specifically, claim terms are given their
`
`ordinary and customary meaning, as would be understood by a person of
`
`ordinary skill in the art, at the time of the invention, in light of the language
`
`of the claims, the specification, and the prosecution history of record.
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`Phillips v. AWH Corp., 415 F.3d 1303, 1313–17 (Fed. Cir. 2005) (en banc).
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`However, there is no presumption of validity, and we do not apply a rule of
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`construction with an aim to preserve the validity of claims.
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`Petitioner proposes constructions for three terms:
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`(1) “microelectronic circuit element”; (2) “etching,” “etchable layer,” “etch
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`stop layer” (grouped together); and (3) “wafer.” Pet. 16–18. Patent Owner
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`disagrees with Petitioner’s proposed constructions for each of these terms,
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`and additionally proposes a construction for the term “second substrate.”
`
`Prelim. Resp. 3–9. For purposes of this Decision, we need only discuss the
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`meaning of “second substrate,” recited in each of the independent claims.
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`No other terms require express construction. See, e.g., Wellman, Inc. v.
`
`
`3 Petitioner refers to Exhibits 1004 and 1007–1012, collectively, as the
`“CMP/Etching references.” Pet. 36–37.
`
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`Eastman Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011) (“[C]laim terms
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`need only be construed ‘to the extent necessary to resolve the
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`controversy.’”) (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
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`200 F.3d 795, 803 (Fed. Cir. 1999)).
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`Patent Owner argues that “second substrate” should be construed as
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`“a substrate that is part of the complete device.” Prelim. Resp. 6–7. Thus,
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`according to Patent Owner, a layer that is attached temporarily and
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`subsequently removed cannot disclose the claimed second substrate. Id.
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`at 11–12. We do not adopt Patent Owner’s proposed construction.
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`The plain meaning of “second substrate” is merely another substrate
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`(i.e., in addition to the claimed “first substrate”). Nothing in the claims
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`themselves, or in the Specification, narrows this plain meaning. We find no
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`persuasive evidence for limiting the term in the manner asserted by Patent
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`Owner.
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`Patent Owner argues that “[t]he language of the specification makes
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`clear that the circuit is transferred to the second substrate to form a final
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`device,” pointing to the ’678 patent’s Title and the Background section,
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`which states the invention relates “to a microelectronic device that is moved
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`from one support to another support during fabrication.” Prelim. Resp. 6
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`(citing Ex. 1001, 1:11–12). Patent Owner further points to the discussion of
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`a disclosed embodiment, in which “‘[t]he second substrate 58 may be any
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`suitable material, such as silicon or aluminum oxide (specifically sapphire).
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`The second substrate may optionally include a microelectronic device
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`deposited therein.’” Id. at 7 (quoting Ex. 1001, 5:18–21).
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`Each of the independent claims, however, includes the open-ended
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`“comprising” in its preamble, and nothing in the claims themselves
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`precludes an additional step of later removing the second substrate or limits
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`the claims to a device in which the second substrate necessarily is retained as
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`part of the final device. See Georgia-Pacific Corp. v. U.S. Gypsum Co.,
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`195 F.3d 1322, 1327 (Fed. Cir. 1999) (“The transitional term
`
`‘comprising’ . . . is inclusive or open-ended and does not exclude additional,
`
`unrecited elements or method steps” (quoting M.P.E.P. § 2111.03 (6th
`
`ed.1997)); see also Vehicular Techs. Corp. v. Titan Wheel Int’l, Inc.,
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`212 F.3d 1377, 1383 (Fed. Cir. 2000) (“A drafter uses the term ‘comprising’
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`to mean ‘I claim at least what follows and potentially more.’”).
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`Accordingly, we decline to adopt Patent Owner’s proposed
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`construction requiring the “second substrate” remain as “part of the
`
`complete device.” No further express construction of the claim term is
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`necessary for purposes of this Decision.
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`B. Principles of Law
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`To establish anticipation, each and every element in a claim, arranged
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`as recited in the claim, must be found in a single prior art reference.
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`See Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1369 (Fed. Cir.
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`2008); Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed.
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`Cir. 2001). Although the elements must be arranged or combined in the
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`same way as in the claim, “the reference need not satisfy an ipsissimis verbis
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`test,” i.e., identity of terminology is not required. In re Gleave, 560 F.3d
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`1331, 1334 (Fed. Cir. 2009); accord In re Bond, 910 F.2d 831, 832 (Fed.
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`Cir. 1990).
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`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
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`between the subject matter sought to be patented and the prior art are such
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`that the subject matter as a whole would have been obvious at the time the
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`invention was made to a person having ordinary skill in the art to which said
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`subject matter pertains. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
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`(2007). The question of obviousness is resolved on the basis of underlying
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`factual determinations including: (1) the scope and content of the prior art;
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`(2) any differences between the claimed subject matter and the prior art;
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`(3) the level of ordinary skill in the art; and (4) objective evidence of
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`nonobviousness. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
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`In that regard, an obviousness analysis “need not seek out precise
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`teachings directed to the specific subject matter of the challenged claim, for
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`a court can take account of the inferences and creative steps that a person of
`
`ordinary skill in the art would employ.” KSR, 550 U.S. at 418; accord
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`In re Translogic Tech., Inc., 504 F.3d 1249, 1259 (Fed. Cir. 2007). A prima
`
`facie case of obviousness is established when the prior art, itself, would
`
`appear to have suggested the claimed subject matter to a person of ordinary
`
`skill in the art. See In re Rinehart, 531 F.2d 1048, 1051 (CCPA 1976).
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`The level of ordinary skill in the art may be reflected by the prior art of
`
`record. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001);
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`In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In re Oelrich,
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`579 F.2d 86, 91 (CCPA 1978).
`
`We analyze the asserted grounds of unpatentability in accordance with
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`those principles.
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`C. Asserted Grounds Based on Bertin
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`Petitioner asserts that claims 1, 6, 7, 10, and 11 are unpatentable under
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`35 U.S.C. § 102 as being anticipated by Bertin. Pet. 2, 18–29. Petitioner
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`further asserts that claims 5, 12, and 13 are unpatentable under 35 U.S.C.
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`§ 103 as obvious over Bertin and Morimoto, and that claim 9 is unpatentable
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`10
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`under 35 U.S.C. § 103 as obvious over Bertin and Ying. Id. at 2, 29–35.
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`Patent Owner argues that Petitioner fails to show Bertin discloses the
`
`claimed invention. Prelim. Resp. 10–11. We have reviewed the parties’
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`contentions and supporting evidence. Given the evidence on this record, and
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`for the reasons explained below, we determine that the information
`
`presented shows a reasonable likelihood that Petitioner would prevail on
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`each of these asserted grounds.
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`1. Anticipation of Claims 1, 6, 7, 10, and 11 by Bertin
`
`Petitioner argues that Bertin discloses all limitations of claims 1, 6, 7,
`
`10, and 11. Pet. 18–29. We discuss independent claim 1 as exemplary.
`
`Claim 1 recites a “method of fabricating a microelectronic device.”
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`Ex. 1001, 8:5–6. Bertin relates to such a “fabrication method and resultant
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`three-dimensional multichip package.” Ex. 1017, Abstract; see Pet. 18
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`(citing Ex. 1017, Abstract, 1:10–14, 1:55–2:31, 3:4–27).
`
`Petitioner relies on substrate 52, etch-stop 53, and the portion above
`
`etch-stop 53 (including active layer 54) of Bertin as disclosing the claimed
`
`etchable layer, etch-stop layer, and wafer, respectively. Pet. 18–19.
`
`Petitioner provides an annotated version of Figure 3a of Bertin, reproduced
`
`below (id. at 19).
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`11
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`Petitioner’s annotated figure illustrates the portions of semiconductor
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`device 50 of Bertin that Petitioner points to as corresponding to the claimed
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`etchable layer (highlighted in blue), etch-stop layer (highlighted in green),
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`and wafer (partially highlighted in yellow). Id. at 18–19 (citing Ex. 1017,
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`1:55–2:17, 3:25–46, 3:50–4:10, Figs. 3a–3i; Ex. 1002 ¶¶ 72–73, 81–82).
`
`Petitioner further relies on active layer 54 (that includes various
`
`transistors therein), layer 63 (that contains active circuits and wiring), and/or
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`metallized trenches 66 (Fig. 3e) with connection pads 68 as disclosing the
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`claimed “microelectronic circuit element” being “form[ed] . . . in the
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`exposed side of the wafer of the first substrate opposite to the side overlying
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`the etch-stop layer.” Pet. 19–22 (citing Ex. 1017, 3:4–4:62, 5:22–38,
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`Figs. 3d–e; Ex. 1002 ¶¶ 83–88; Ex. 1001, 4:37–43).
`
`Petitioner relies on carrier 70 of Bertin as disclosing the claimed
`
`“second substrate.” Pet. 22. Petitioner provides an annotated version of
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`Figure 3f of Bertin, reproduced below (id.).
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`Petitioner’s annotated figure illustrates a second substrate (highlighted in
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`orange) attached to the wafer (partially highlighted in yellow). Id. (citing
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`Ex. 1017, 4:63–5:44, 8:51–10:34, Figs. 3f–3i; Ex. 1002 ¶ 89).
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`Finally, Petitioner relies on Bertin’s disclosure of chemically etching
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`layer 58 (highlighted in blue) using an etchant selected to cease when etch
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`stop layer 53 (highlighted in green) is reached (Ex. 1017, Fig. 3g) for the
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`claimed step of “etching away the etchable layer of the first substrate down
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`to the etch-stop layer.” Id. at 22–23 (citing Ex. 1017, 3:4–46, 4:4–10, 4:47–
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`52, 5:10–22, 5:39–44, 6:18–24, Figs. 3f–3g; Ex. 1002 ¶¶ 90–91).
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`Patent Owner argues that Bertin’s teachings are ambiguous, pointing
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`to allegedly confusing portions of Bertin. Prelim. Resp. 10–11. For
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`example, Patent Owner asserts that the discussion of dielectric layer 60 and
`
`layer 63 is confusing. Id. Patent Owner, however, does not provide
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`persuasive evidence that Petitioner’s mapping of Bertin on the claims is
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`missing any claimed element. We, thus, are persuaded, on the current
`
`record, that Petitioner has shown sufficiently that Bertin discloses all the
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`steps of claim 1.
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`We also have reviewed the parties’ contentions and supporting
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`evidence regarding claims 6, 7, 10, and 11, and similarly are persuaded,
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`based on the record now before us, that Petitioner has shown sufficiently that
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`Bertin discloses all steps of claims 6, 7, 10, and 11. See Pet. 23–29 (citing
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`Ex. 1017, Abstract, 1:10–14, 1:55–2:31, 3:4–4:10, 4:26–40, 4:47–53, 4:62–
`
`5:44, 6:6–9, 6:18–24, 8:51–10:34, Figs. 3a–3i; Ex. 1002 ¶¶ 92–104);
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`Prelim. Resp. 10–11 (arguing generally regarding the allegedly deficient
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`disclosure of Bertin).
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`2. Obviousness of Claims 5, 12, and 13 in View of Bertin and
`Morimoto
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`Claims 5 and 12 depend from claims 1 and 11, respectively, and
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`further recite that “the etchable layer is silicon, the etch-stop layer is silicon
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`dioxide, and the wafer is single-crystal silicon.” Ex. 1001, 8:29–31,
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`9:10–12. Independent claim 13 recites limitations similar to claim 1, and
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`additionally includes the same specific materials recited in claims 5 and 12
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`for the etchable layer, the etch-stop layer, and the wafer, respectively.
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`Id. at 9:13–26.
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`As discussed by Petitioner, “Bertin discloses a three-layer silicon
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`substrate . . . but does not expressly disclose an etch-stop layer made of
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`SiO2.” Pet. 29; see id. at 30–31 (citing Ex. 1017, 5:21–22; Ex. 1002 ¶ 125).
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`Petitioner relies on Morimoto as disclosing an SiO2 etch-stop layer. Id. at 30
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`(citing Ex. 1006, 2). According to Petitioner, “it would have been obvious
`
`to use Morimoto’s SiO2 etch-stop layer in Bertin’s structure” because
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`“[u]sing an SiO2 etch-stop layer would have had no unpredictable
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`results. . . . and qualifies as the use of a known equivalent for a known
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`function (as an etch-stop layer).” Id. at 29–30 (citing Ex. 1002 ¶ 130).
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`Petitioner further asserts that “both Morimoto and Bertin disclose the
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`use of single-crystal silicon for integrated circuit manufacturing in a way
`
`that renders a single-crystal silicon wafer obvious, particularly in view of the
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`typical use of single-crystal silicon in the art.” Id. at 29, 31 (citing Ex. 1017,
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`3:42–46, 4:30–32, 5:21–22, 5:50–51; Ex. 1006, 1; Ex. 1001, 3:64–4:11).
`
`Petitioner further cites to the Blanchard Declaration in support of this
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`assertion. Id. at 31 (citing Ex. 1002 ¶¶ 126–128).
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`Patent Owner, at this stage of the proceeding, has not presented
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`separate arguments regarding the limitations of claims 5, 12, and 13, or the
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`combination of references. We are persuaded, on the record now before us,
`
`that Petitioner has shown sufficiently that the combination of Bertin and
`
`Morimoto teaches or suggests all of the limitations of claims 5, 12, and 13,
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`and has articulated sufficient reasoning why it would have been obvious to
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`combine these references in the proposed manner.
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`3. Obviousness of Claim 9 in View of Bertin and Ying
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`Claim 9 depends from claim 1, and recites a further step of, “after the
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`step of attaching and before the step of etching, fixing the second substrate
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`to an etching support that is resistant to attack by an etchant.” Ex. 1001,
`
`8:46–49. Petitioner relies on Ying as teaching this claim feature. Pet. 34–
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`35. Ying relates to the fabrication of small semiconductor devices, and
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`teaches, prior to etching a semiconductor wafer, attaching the wafer to a
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`substrate, such as sapphire, which is not capable of being attacked by an
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`etching solution, before etching. Ex. 1016, 1:8–11, 3:12–4:28. Petitioner
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`asserts that “a person of skill in the art would have needed to hold the
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`semiconductor [of Bertin] while performing etching, and would not have
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`wanted the structure holding the semiconductor itself to be dissolved, as
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`taught by Ying.” Pet. 35. Petitioner further cites to the Blanchard
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`Declaration in support of its assertion that claim 9 would have been obvious
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`in view of Bertin and Yang. Id. at 34–35 (citing Ex. 1002 ¶¶ 246, 248–251).
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`Patent Owner, at this stage of the proceeding, has not presented
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`separate arguments regarding the limitations of claim 9, or the combination
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`of references. We are persuaded, on the record now before us, that
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`Petitioner has shown sufficiently that the combination of Bertin and Ying
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`teaches or suggests all of the limitations of claim 9, and has articulated
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`sufficient reasoning why it would have been obvious to combine these
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`references in the proposed manner.
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`4. Conclusion
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`For the foregoing reasons, we authorize institution of inter partes
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`review on the following asserted grounds: claims 1, 6, 7, 10, and 11 under
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`35 U.S.C. § 102 as anticipated by Bertin; claims 5, 12, and 13 under
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`35 U.S.C. § 103 as obvious over Bertin and Morimoto; and claim 9 under
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`35 U.S.C. § 103 as obvious over Bertin and Ying.
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`D. Asserted Grounds Based on Morimoto
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`Petitioner asserts that claims 1, 2, 4, 5, 10, 13, 14, 16, and 17 are
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`unpatentable under 35 U.S.C. § 103 as obvious over Morimoto and the
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`CMP/Etching references. Pet. 2, 35–57. Petitioner further asserts that
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`claims 8 and 18 are unpatentable under 35 U.S.C. § 103 as obvious over
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`Morimoto, the CMP/Etching references, and Oldham, and that claims 3
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`and 15 are unpatentable under 35 U.S.C. § 103 as obvious over Morimoto,
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`the CMP/Etching references, and Bertin. Id. at 2, 57–60. Patent Owner
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`argues Morimoto does not teach or suggest several claim features. Prelim.
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`Resp. 11–18. We have reviewed the parties’ contentions and supporting
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`evidence. Given the evidence on this record, and for the reasons explained
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`below, we determine that the information presented shows a reasonable
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`likelihood that Petitioner would prevail on each of these asserted grounds.
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`1. Obviousness of Claims 1, 2, 4, 5, 10, 13, 14, 16, and 17 in View
`of Morimoto and the CMP/Etching References
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`Petitioner argues that the combination of Morimoto and the
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`CMP/Etching references renders obvious each of claims 1, 2, 4, 5, 10, 13,
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`14, 16, and 17. Pet. 35–57. We discuss claim 1 as exemplary. Claim 1
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`recites a “method of fabricating a microelectronic device.” Ex. 1001, 8:5–6.
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`Morimoto relates to a “method for producing a semiconductor device.”
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`Ex. 1006, 2; see Pet. 37 (citing Ex. 1006, 1, 2; Ex. 1002 ¶ 156).
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`Petitioner relies on silicon substrate 11, buried oxide layer 12, and a
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`portion above buried oxide layer 12 of Morimoto as disclosing the claimed
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`etchable layer, etch-stop layer, and wafer, respectively. Pet. 13–14, 37–39.
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`Petitioner provides a revised, annotated version of Figure 1(a) of Morimoto,
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`reproduced below (id. at 13).
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`The figure above shows Morimoto’s substrate, after ion implantation and
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`heating, but before inclusion of the circuitry shown in Morimoto’s
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`Figure 1(a). Id. at 13–14. Petitioner’s annotated figure illustrates the
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`portions of Morimoto that Petitioner points to as corresponding to the
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`claimed etchable layer (highlighted in blue), etch-stop layer (highlighted in
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`green), and wafer (highlighted in yellow). Id. at 37–39 (citing Ex. 1006, 2;
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`Ex. 1002 ¶¶ 157–171).
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`Petitioner further relies on MOS transistor 13, wiring 14, and
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`insulating file 15 as teaching the claimed “microelectronic circuit element”
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`being “form[ed] . . . in the exposed side of the wafer of the first substrate
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`opposite to the side overlying the etch-stop layer.” Id. at 39–40 (citing
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`Ex. 1006, 2; Ex. 1002 ¶¶ 173–174). This is illustrated in annotated
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`Figure 1(a) of Morimoto provided by Petitioner, and reproduced below (id.
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`at 40).
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`Figure 1(a) of Morimoto illustrates transistor 13 and wiring 14 formed in the
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`semiconductor device.
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`Petitioner further relies on supporting silicon substrate 16 of
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`Morimoto as teaching the claimed “second substrate.” Pet. 40–41.
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`Petitioner provides an annotated version of Figure 1(b) of Morimoto,
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`reproduced below (id. at 40).
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`Petitioner’s annotated figure illustrates a second substrate (highlighted in
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`orange) attached to the wafer including the microelectronic devices formed
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`therein (highlighted in yellow). Id. (citing Ex. 1006, 2; Ex. 1002 ¶¶ 175–
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`176).
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`Figure 1(b), above, also shows that silicon substrate 11 (highlighted in
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`blue in previous figures) has been removed. Petitioner asserts that
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`“Morimoto teaches that the etchable layer 11 is removed down to layer 12,
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`which is an etch-stop layer.” Pet. 41. According to Petitioner, although
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`Morimoto explicitly discloses “chemical-mechanical polishing (‘CMP’)” as
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`the removal method, it would have been obvious to use an etching process,
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`as claimed. Id. at 41–49. As noted by Petitioner, the chemical mechanical
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`polishing disclosed in Morimoto “stops at the lower surface of the buried
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`oxide film” (i.e., layer 12, highlighted green in the figures above). Id. at 41
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`(citing Ex. 1006, 2; Ex. 1002 ¶ 177).
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`With its Petition, Petitioner includes seven references it describes as
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`the “CMP/Etching references,” as evidence of the level of skill in the art,
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`supporting the conclusion that Morimoto renders obvious using etching. Id.
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`at 36. According to Petitioner, “[t]he seven CMP/Etching references each
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`(redundantly) show that the etching step was at least obvious,” and the
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`“[s]even references are cited to show the strength of the evidence, although
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`one alone would suffice.” Id. at 36–37. Petitioner asserts (i) that it would
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`have been obvious to use etching within a CMP process, and (ii) that it
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`would have been obvious to use etching as a known alternative to a CMP
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`process. Id. at 41–49. Petitioner and Dr. Blanchard cite to the CMP/Etching
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`references as evidence of the level of one of ordinary skill in the art at the
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`time of the invention, and particularly as evidence that one of such skill
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`would have known these assertions to be true. Id.; Ex. 1002 ¶¶ 151–155,
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`177–194. We similarly rely on these references as evidence of the
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`knowledge of one of ordinary skill in the art. Based on the evidence
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`presented by Petitioner, we are persuaded that one of ordinary skill in the art
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`would have recognized that Morimoto (in view of the knowledge of one of
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`ordinary skill) teaches or suggests the use of etching for removal of silicon
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`substrate 11.
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`We, thus, are persuaded, on the current record, that Petitioner has
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`shown sufficiently that Morimoto renders obvious all steps of claim 1.
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`Independent claim 13 differs from independent claim 1 in that it recites
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`specific materials for each layer of the microelectronic device. We are
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`persuaded by Petitioner’s assertion that the device of Morimoto discloses a
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`silicon etchable layer and an SiO2 etch-stop layer (Pet. 53–54 (citing
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`Ex. 1006, 1–2; Ex. 1002 ¶ 209); see id. at 37–39 (citing Ex. 1006, 2; Ex.
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`1002 ¶¶ 158–159)), and renders obvious the use of a single-crystal silicon
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`wafer layer (id. at 50–51 (citing Ex. 1002 ¶¶ 200–201), 53–54)).
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`Patent Owner argues, first, that Morimoto fails to disclose “attaching”
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`a “second substrate,” because substrate 16 of Morimoto is used only
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`temporarily and does not form part of the final device. Prelim. Resp. 11–15.
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`This argument is based on a construction of “second substrate” that we do
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`not adopt, for the reasons discussed above, and, thus, is not persuasive.
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`Patent Owner also argues that Morimoto does not disclose or render obvious
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`“etching.” Id. at 15–18. Based on the record currently before us at this
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`stage of the proceeding, we do not find Patent Owner’s arguments
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`persuasive. As discussed above, Petitioner provides evidence and
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`declaration testimony that one of ordinary skill in the art at the time of the
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`invention would have recognized that CMP includes etching as a part of the
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`process, and that, alternatively, etching could be used in place of a CMP
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`process.
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`We also have reviewed the parties’ contentions and supporting
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`evidence regarding claims 2, 4, 5, 10, 14, 16, and 17, and similarly are
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`persuaded, based on the record now before us, that Petitioner has shown
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`sufficiently that Morimoto renders obvious all the additional steps of these
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`claims. See Pet. 49–57 (citing Ex. 1006, 2–3; Ex. 1002 ¶¶ 140, 152, 155,
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`195–201, 203–206, 213–225); Prelim. Resp. 11–18 (arguing generally
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`regarding the allegedly deficient disclosure of Morimoto with respect to
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`claims 1 and 13).
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`2. Obviousness of Claims 8 and 18 in View of Morimoto, the
`CMP/Etching References, and Oldham
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`Claims 8 and 18 depend from claims 1 and 13, respectively, and
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`further recite “placing a layer of epoxy between the second substrate and the
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`wafer portion of the first substrate, and degassing and curing the epoxy.”
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`Ex. 1001, 8:41–45, 10:20–24. Petitioner points to disclosure in Morimoto
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`that silicon substrate 16 (i.e., the claimed second substrate) is bonded to
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`insulating film 15 (i.e., the claimed wafer portion) “with an epoxy resin or
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`the like.” Pet. 57 (citing Ex. 1006, 2; Ex. 1002 ¶ 130). Petitioner relies on
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`Oldham as teaching that “the use of epoxy molding compound with both
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`degassing and curing” was a common practice at the time of the invention.
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`Id. at 58 (citing Ex. 1014, 3:30–43; Ex. 1002 ¶¶ 228–229). Petitioner further
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`asserts “[i]t would have been obvious to apply steps known to be useful for
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`epoxies . . . to the adhesive of Morimoto, and there would not have been any
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`unpredictable results.” Id.
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`Patent Owner, at this s