Raytheon2027R-0001
`
`Sony Corp. v. Raytheon Co.
`IPR2015-01201
`
`

`
`SILICON PROCESSING
`
`A symposium
`sponsored by ASTM
`Committee F-1 on Electronics,
`National Bureau of Standards,
`and Stanford University
`San Jose, Calif., 19-22 Jan. 1982
`
`ASTIVI SPECIAL TECHNICAL PUBLICATION 804
`D. C. Gupta, Siliconix Incorporated, editor
`
`ASTM Publication Code Number (PCN)
`04-804000-46
`
`1916 Race Street, Philadelphia, Pa. 191G3
`
`Raytheon2027R-0002
`
`

`
`Copyright © by AMERICAN SOCIETY FOR TESTING AND MATERIALS
`Library of Congress Catalog Card Number: 82-83529
`
`1983
`
`NOTE
`The Society is not responsible, as a body,
`for the statements and opinions
`advanced in this publication.
`
`Printed in Baltimore, Md. (b)
`June 1983
`
`Raytheon2027R-0003
`
`

`
`Foreword
`
`The Symposium on Silicon Processing was held in San Jose, California, on
`19-22 January 1982. ASTM Committee F-1 on Electronics, the National Bu(cid:173)
`reau of Standards, and Stanford University sponsored the symposium, and
`Dinesh C. Gupta, Siliconix Incorporated, presided as chairman. The Advi(cid:173)
`sory Board consisted of Kenneth E. Benson, Bell Laboratories; W. Murray
`Bullis, Fairchild Advanced R&D Laboratory; Robert E. Lorenzini, Siltec
`Corporation; Samuel L. Marshall, Solid State Technology; and James D.
`Meindl, Stanford University. The Technical Committee consisted of Theo(cid:173)
`dore L Kamins, Hewlett-Packard Laboratories; Eric Mendel, International
`Business Machines; Krishna C. Saraswat, Stanford University; Joseph Stach,
`Penn State University; and Fritz G. Vieweg-Gutberlet, Wacker Chemitronic;
`and was headed by Paul H. Langer, Bell Laboratories. The Arrangements
`and Publicity Committee consisted of Austin R. Blew, Lehighton Electronics
`Incorporated; Edward E. Gardner, IBM-GTD; Gilbert A. Gruber, Siliconix
`Incorporated; Charles Koehler, Fairchild Advanced R&D Laboratory; Don(cid:173)
`ald J. Levinthal, Semiconductor International; Philip L. Lively, ASTM;
`David G. Mead, Nicolet Instrument Corporation; J. Timothy Raab,
`Rockwell International Recticon; Donald G. Schimmel, Bell Laboratories;
`and William R. Wheeler, Tencor Instruments; and was headed by Carl A.
`Germano, Motorola Incorporated. The Spouse Committee, consisting of
`Lou Ann Gruber, Vijay Gupta, and Carol Koehler, was headed by Kathleen
`Bullis; and the Registration Committee, consisting of Elaine Cohen, Na(cid:173)
`tional Bureau of Standards, and Jan Meighan, San Jose Convention Bureau,
`was headed by Mr. Lively. We appreciate their efforts.
`Appreciation is also extended to the following session and workshop
`chairmen: James T. Clemens, Bell Laboratories; James R. Ehrstein, Na(cid:173)
`tional Bureau of Standards; Carl A. Germano, Motorola Incorporated; Gil(cid:173)
`bert A. Gruber, Siliconix Incorporated; Theodore I. Kamins, Hewlett-Pack(cid:173)
`ard Laboratories; William H. Kroeck, Western Electric Company; John W.
`Lampe, Martin Marietta Aerospace; Paul H. Langer, Bell Laboratories; Eric
`Mendel, International Business Machines; C. W. Pearce, Western Electric
`Company; R. Fabian W. Pease, Stanford University; Mike Powell, Motorola
`Limited; Sy Prussin, TRW Systems; Krishna C. Saraswat, Stanford Univer(cid:173)
`sity; Joseph Stach, Penn State University; and Fritz G. Vieweg-Gutberlet,
`Wacker Chemitronic.
`
`Raytheon2027R-0004
`
`

`
`Related
`ASTM Publications
`
`Laser-Induced Damage
`04-726000-46
`
`in Optical Materials: 1979, STP 726 (1980),
`
`Lifetime Factors in Silicon, STP 712 (1980), 04-712000-46
`
`Laser-Induced Damage
`04-689000-46
`
`in Optical Materials: 1978, STP 689 (1979),
`
`Optical Interferograms—Reduction and Interpretation, STP 666 (1979),
`04-666000-46
`
`Annual Book of ASTM Standards, Volume 10.04: Electronics (I),
`01-100483-46
`
`Annual Book of ASTM Standards, Volume 10.05: Electronics (II),
`01-100583-46
`
`Raytheon2027R-0005
`
`

`
`A Note of Appreciation
`to Reviewers
`
`The quality of the papers that appear in this publication reflects not only
`the obvious efforts of the authors but also the unheralded, though essential,
`work of the reviewers. On behalf of ASTM we acknowledge with apprecia(cid:173)
`tion their dedication to high professional standards and their sacrifice of
`time and effort.
`
`ASTM Committee on Publications
`
`Raytheon2027R-0006
`
`

`
`ASTM Editorial Staff
`
`Janet R. Schroeder
`Kathleen A. Greene
`Rosemary Horstman
`Helen M. Hoersch
`Helen P. Mahy
`Allan S. Kleinberg
`Virginia M. Barishek
`
`Raytheon2027R-0007
`
`

`
`Preface
`
`The papers in this volume were presented at the Symposium on SiHcon
`Processing held in San Jose, California, on 19-22 January 1982. The sympo(cid:173)
`sium was sponsored by ASTM Committee F-1 on Electronics, the National
`Bureau of Standards, and Stanford University. In addition to the technical
`presentations, the symposium included well-attended workshops on each
`technical topic; impressions of these workshops are provided in Appendix II.
`The trend towards very-large-scale integration (VLSI) is usually described
`as increasing device count on an integrated circuit chip. The associated
`trends towards smaller feature size, larger chip size, and larger wafer diame(cid:173)
`ter present new problems in processing technology and control to the semi(cid:173)
`conductor device manufacturer. The symposium was designed to identify the
`future directions in materials and processing technology required for VLSI
`and areas where additional measurement development and standardization
`are required to accelerate the efficient implementation and control of these
`technologies.
`The symposium opened with a series of brief talks on the role of standards
`and on the work performed by the Stanford Center for Integrated Systems,
`the National Bureau of Standards, and the National Science Foundation in
`relation to the semiconductor industry. These talks were followed by an
`overview projection of future VLSI technology which emphasized the need
`for rigorous and disciplined control of processes to achieve the potential of
`VLSI. These talks are presented in Appendix I.
`The opening general session included a discussion on semiconductor busi(cid:173)
`ness and education requirements in the Eighties by a panel of prominent in(cid:173)
`dividuals in industry, academia, and government. Brief summaries of the
`panel responses to key questions are provided in Appendix II.
`The response to the symposium was extremely favorable, suggesting a con(cid:173)
`tinuing need for a regular forum to discuss technology topics in the context
`of measurement and control. Accordingly, the symposium sponsors have ini(cid:173)
`tiated plans both to repeat the symposium at two-year intervals and to
`broaden industry involvement in the organization and conduct of future
`symposia. The present symposium has established a consistent theme for
`these symposia as they evolve: understanding and control of the complex
`process technologies required for VLSI and other advanced device concepts.
`The problem areas and standardization needs identified in this and subse-
`
`Raytheon2027R-0008
`
`

`
`quent symposia will provide the feedback to the research community and vol(cid:173)
`untary standards system essential for the future growth of the industry.
`We appreciate the cooperation and support of the ASTM staff in the for(cid:173)
`mulation of these proceedings. The assistance of W. Murray Bullis is ac(cid:173)
`knowledged. Finally, we are indebted to our industrial, government and uni(cid:173)
`versity colleagues who contributed to the content of the symposium and the
`proceedings.
`
`Raytheon2027R-0009
`
`

`
`Contents
`
`Introduction
`
`CRYSTAL GROWTH AND MATERIAL SHAPING
`
`Silicon Crystal Growth and Processing Technology: A Review—
`A. C. BONORA
`
`5
`
`Large-Diameter Czochralski Silicon Crystal Growth—w. LIN AND
`D. W. HILL
`
`24
`
`Impurity Incorporation in Czochralski Silicon Grown for VLSI—
`A. MURGAI
`
`39
`
`Dependence of Silicon Float-Zone Refining Parameters on Frequency—
`K. P. GUPTA AND R, O. GREGORY
`
`50
`
`Influence of Laser Marking on Silicon Wafer Properties—M. H. CHRIST
`AND B. S, MAURANTONIO
`
`62
`
`MICROELECTRONICS IMAGING AND PATTERNING
`
`A Review of Optical Lithographic Techniques for VLSI—D. A. DOANE
`
`85
`
`Resist Profile Quality and Linewidth Control—A. R. NEUREUTHER
`
`108
`
`Considerations of Resist Processing—M. J. BOWDEN AND J. FRACKOVIAK
`
`125
`
`SILICON C VD TECHNIQUES
`
`Epitaxy: An Introspective Review—J. H. WILLIAMS
`
`Modeling and Applications of Silicon Epitaxy—G. R. SRINIVASAN
`
`Effects of Processing Parameters on Shallow Surface Depressions Dur(cid:173)
`ing Epitaxial Deposition—M. R. BOYDSTON, G, A. GRUBER, AND
`D. C. GUPTA
`
`147
`
`151
`
`174
`
`Raytheon2027R-0010
`
`

`
`Improvement in MOS VLSI Device Characteristics Built on Epitaxial
`Silicon—L. s. WHITE, G. R. M O H AN RAO, P. U N D E R, A ND
`M. ZIVITZ
`
`Reduced-Pressure Chemical Vapor Deposition of Polycrystalline
`Silicon—M. L. HAMMOND
`
`Plasma-Enhanced Chemical Vapor Deposition
`Silicon-Containing Films—D. w. HESS
`
`of Silicon
`
`and
`
`190
`
`206
`
`218
`
`DIELECTRICS A ND JUNCTION FORMATION
`
`Process Technology Requirements for VLSIC Fabrication—R. KUMAR,
`M. M. NOWAK, E. H. TYLER, AND M. A, VINSON
`
`229
`
`Defects and High-Pressure Steam Oxidation of Silicon—L. E. KATZ
`
`238
`
`Hydrogen/Chlorine Distributions in Silicon Dioxide: Detection and
`Model—J. R. MONKOWSKI, M. D. MONKOWSKI, I. S. T. TSONG,
`AND J. STACH
`
`245
`
`Dependence of Thin-Gate Oxide Properties on Processing—s. K. LAI
`
`260
`
`Polyimide-Substrate Effects During Wet Chemical Processing of
`Polyimide Films in VLSI—D. J. BELTON, P. VAN PELT, A ND A. E.
`MORGAN
`
`Modeling Anomalous Junction Formation in Silicon by the Codiffusion
`of Implanted Arsenic with Phosphorus—R. B. FAIR A ND W. G.
`MEYER
`
`273
`
`290
`
`D E F E C T S, O X Y G EN PRECIPITATION, A ND CARRIER LIFETIME
`
`Silicon Crystals for VLSI Technologies—L. JASTRZEBSKI
`
`309
`
`Material Defect Factors Affecting MOS Device Performance—
`J. H. MATLOCK
`
`332
`
`Oxygen Precipitation Studies at Various Impurity Levels Using Thermal
`Donor Activation—j. c. ALLISON, O. F. MAXWELL, R. SCHINDLER,
`AND M. DOMENICI
`
`362
`
`Raytheon2027R-0011
`
`

`
`Effects of Oxygen Precipitation on Minority Carrier Lifetime in Silicon
`Crystals—c. J, VARKER, J. D. WHITFIELD, AND P. L. FEJES
`
`369
`
`Defects and Carrier Lifetime
`p. RAI-CHOUDHURY
`
`in Silicon—A. ROHATGI AND
`
`389
`
`MEASUREMENTS FOR PROCESS CONTROL
`
`Computer-Aided Process Modeling for Design and Process Control—
`R. W. DUTTON, P FAHEY, K. DOGANIS, L. MEI, AND H. G. LEE
`
`407
`
`Characterizing Process Nonuniformities on Large-Diameter Wafers:
`An Overview—D. s. PERLOFF
`
`422
`
`Temperature-Dependent Infrared Characterization of Silicon Wafers—
`D. G. MEAD, R. M. GUMMER, AND C. R. ANDERSON
`
`445
`
`Analysis of Infrared Spectra for Oxygen Measurements in Silicon—
`R. K. GRAUPNER
`
`459
`
`Determination of Oxygen Concentration in Silicon by Infrared Absorp(cid:173)
`tion—T. ABE, S. GOTOH, N. OZAWA, AND T, MASUI
`
`469
`
`Thickness Measurement of Thin (1.0-^m) Epitaxial Silicon Layers by
`Infrared Reflectance—s. p. WEEKS
`
`477
`
`Automated Detection of Wafer Surface Defects by Laser Scanning—
`L. K. GALBRAITH
`
`492
`
`Computerized Electron-Beam Linewidth Measuring and Inspection:
`A New Tool—T. F. POMPOSO AND V. J. COATES
`
`501
`
`Measurement of Ion Implantation Doses in Silicon by EUipsometry and
`Spectral Reflectance—A. K. HOCHBERG
`
`509
`
`Appendix I
`
`APPENDIXES
`
`The Role of Standards in the Electronics Industry—K. E. BENSON 537
`
`Raytheon2027R-0012
`
`

`
`NBS Work for the Semiconductor Industry—R. i. SCACE
`
`NSF Role in Microelectronics—R. J. GUTMANN
`
`Future VLSI Technology: A Review—J. M. EARLY
`
`Appendix II—Panel and Workshop Discussions: A Synopsis—
`D. C. GUPTA
`
`Index
`
`538
`
`540
`
`541
`
`547
`
`553
`
`Raytheon2027R-0013
`
`

`
`Anthony C. Bottom’
`
`Silicon Crystal Growth and
`Processing Technology: A Review
`
`IlFl2I£NCl3:lonora.A.C..“$caaCryad(ioI\a-dPtaeg"le&iog:A
`Iain.“ Silleoa banning. A.S'l'MSl?8N. D. C. Gupta. lEd..AtaeritaIt Society for
`Tuning and Materials. lfl3. pp. 5-23.
`
`AISIIACI’: Crystal growing and shaping technologies are being itllautced by a
`eonhinationofnewdiaeoverisin inlet-ialsprooertiesandttea-eeljuiteatetttsfrunt the
`marketplace. Key elements olchanp in crysaalgrovnh ittdtttlecotltul ofarbonand
`oayaemooupled wltlu Illnsilioll to eornpulerizad largo-eltargegroavers. and inani-
`aatiun at magnetic field influence.
`Matefnlsshapiagishciegdriven by stringent uaity reqairetaeatsooapledvith
`newly available processing teehnolagis incladin; laser nan-king. getter-in¢. and edge
`putting. New instruments for inspection 0! particles. aaatenal
`and
`were names: are contributing to an overall and ton-ans automation ol critical pro-
`cesses. Planuity of the polished slice oominas to be a signiliant concern. since some
`ooatplnitltogtaplty prose-ssesthovarpalornaneegainsuihultnllat wafers.
`
`IIIY WORDS: dlicon. crystal ptwatlt. materials pmoasing. shpitg. law matting.
`inspection imtrtnnruls. Ialer quality
`
`Crystal Growing
`
`Virtually all semiconductor-device technology employs a crystalline mate
`rial as its starting point. The term crystal refers to a material that is highly
`ordered on a long-range atomic basis. The process of convening a random-
`ordered or polycrystalline material into one of long-range order is known as
`com! slowing-
`Tlte physics of semiconductohcrystal growth generally is based on estab-
`lishing thermal and geometrical condition such that a liquid is solidified in a
`controlled interface. Most electronic crystal production is currently centered
`on silicon and utilizes the technique invented by Czochralski (oz? and ae-
`velopcd by Teal and Little’.
`In the C2 pmoess. crystal growth begins with the ineltingof a charge of
`
`Mealo latlt. (hlif. 9&3.
`‘Vic President and General lhhager. filter lastnnneut
`‘Gum. ll. C. in oymlcm-is.-A Ihlovialdnnuh. W. lutlsleyeul. lids..P~o:«i-rsof
`Third llaterntiooal fiunltter School on Crystal (ho'at.lt—l977. NOIII-HOIIIIIII. ‘lie Nether-
`hnds. I979.
`‘Teal. G. K.. IEEE Tianrtlaln Vol. ED-23. No. 7. July I976. pp. 62!-J9.
`
`Raytheon2027R-0014
`
`

`
`ttm: gradients in the melt.
`shown schetnatially in Fig.1. A seed crystal with the desited crystallo-
`graphic orientation is dipped into the melt at a temperature near the solidifi-
`cation point. If conditi
`'
`seed ctystal in such 1
`
`Its and tilled with an inert gas. usually
`at-yon. With applied power tanyn; front 50 to IN RVA. meltdown of the
`duty: proceeds. When the melt nacltes “dip-in” tempentune (approxi-
`mately l42o'C). the seed is dipped. and the necking and sltouldeting proce-
`dnm follow. Operatorskill remains a crucial factor throughout these opera-
`
`Raytheon2027R-0015
`
`

`
`BONORA ON QVSTAL GROWTH AND PIIOQSSING TECIIIOLOOY
`
`7
`
`tions. Once the crystal reaches the diameter dsirctl. the autormtic-diameter»
`control (ADC) system is turned on and closed-loop controls regulate the
`diameter.
`
`The process continues through body growth. As the crystal is pulled. the
`melt level in the cnttible drops relative to other hot-zone components. Be-
`cause this changing melt level creates undesirable changs in thermal profiles
`at the growth interface, an electromechanical crutible-lih system is normally
`provided to elevate the crucible continuously during the growth procs. The
`rate of lifl. in turn. affects other growth parameters. so the furnace operator
`must monitor visual indications of structure on the growing crystal to assure
`that crystal pull speed and crucible lifl rate are appropriate.
`Body growth proceeds at pull speeds ranging from 50 to I00 tum/h. until
`only a small volume of melt remains in the crucible; at this point the mound-
`oll' procedure begins. Structure must be maintained meticulously during
`round-olf. because crystal defxts such as "slip" can propagate up through
`the still-plastic crystal body. After round-oil’. power to the furnace is turned
`on‘and the crystal is allowed to cool. The crystal may later be heat treated to
`stabilize electrially active oxygut.
`
`Oystal Evaluttrlort
`
`he completed crystal is immersed in an etchant designed to highlight de-
`fects such as slip. When the shoulder and round-off portions have been
`cropped with a diamond saw. resistivity and type measurements are made
`and recordcdforthecrystal ends. Thecropperlingotisgrottndtothedcsirettl
`diameter. and may be rechecked for axial profile by taking resistivity read-
`ings along the length of its cylindrical surface.
`At a location determined by atomic orientation. a flat is pound along the
`length of the ingot: this will serve as a reference plane for later operations.
`Thccrystal may notvbesliced intowalersorcropped into scgmcntsforspc-
`cific end users.
`
`CZ Material Chnmctrrrtrticr
`
`Mnchofthecurrent resarchonsiliconisfoctsedontheexcceclingy
`complex relationships among certain impnritis and defects in silicon crys-
`tals. because point defects in wafer-substrates exert an increasingly strong in-
`fluence on final die yieids. This surge of interest in crystal defect formation
`arises from the shrinkingdie and circuit-element size used in very-large-scalp
`integration (VISI) technology. The complexities lie partially in the fact that
`impurity concentration alone does not constitute defect l'orrnation:otherde~
`terrninin; factors include thermal gradients at the time of solidification. lo-
`calized melt convection. instantaneous growth rates. melt-rernelt pl»
`nornena. and thermal conditions after solidification.
`
`Raytheon2027R-0016
`
`

`
`8
`
`SIUOONPIIOCQSINB
`
`Current technical literature on the subject of crystal defects is plentiful.
`but its utilization in production practices presents many challenges. To de-
`termine accurately the influence of process changes in crystal growth upon
`device yields in a particular fabrication line may involve an elapsed time of
`three to six months. and requires detailed communication between water
`supplier and user.
`
`Oxygen and Carbon
`
`Control of oxygen and carbon in the growing crystal is an active area of
`research. Oxygen is present in C2 silicon as a result of dissolution of the sil-
`ia crucible wall.and genertllyis higher in concentration at the topend ofan
`ingot. Reported concentrations-range from <10 to >40 ppm. Oxygen influ-
`ences wafer strength. resistance to thermal warping. ntinor-ity<:arrier life-
`time. and intrinsic impurity gettering. There is evidence that the level of oxy-
`gen content influences die yields. and that appropriate levels for maximum
`yield depend upon the particular device production technology.
`Carbon is present in C2 silicon as a result ofcontributions from the origi-
`nal polycrystalline material and from graphite components of the hot zone.
`Reported concentrations range from 0.1 to 7 ppm. with levels usually rising
`throughout the length of the ingot. Carbon is strongly implicated in the gen-
`eration of point defects: its role appears to be interrelated to the presence of
`oxygen.
`
`Carbon and Oxygen rlleasurenteur/Control
`
`Control ofarbon and oxygen must be achieved primarily by the materials
`producer. and substantial etfort is being expended in related applied re-
`searemoxygencanbepartiaflycontrolledbymeansofgrowthtechniques
`that minimize the rate of crucible-wall dissolution and reduce the incorpora-
`tion of dissolved oxygen into the growing crystal. Control of carbon is re-
`lated to gas now patterns. hot zone materials. furnace leak integrity. and
`starting material.
`The primary technique for measuring oxygen and arbon concentrations
`employs a transmission/absorption-type infrared spectrophotometer.
`Lengthyandeareful sample processing isnecessary toobtain usableresults.
`although the recent introduction of Fourier transform infrared equipment
`facilitates rapid measurement of oxygen and carbon on polished slices.
`A subjective indication ofthe influence ofearbon and oxygen on C2 mate-
`rial is provided by a variety of
`tests. This technique employs high-
`temperature oxidation of a polished sample. followed by decoration etching
`and visual examination. Swirl is evidenced as a cloudy appearance. oflen
`havingastvirled form. that iscaused by the high-densityI’orrnationofrni-
`croseopic etch pits at sits where concentrated microdefects occur. Because
`
`Raytheon2027R-0017
`
`

`
`BONORA ON CRYSTAL GROWTH AND PFlOCE%ING TECFNOLOGY
`
`9
`
`swirl has been correlated to areas of high device-yield loss. CZ growth tech-
`nologies that provide low or zero swirl may improve die yields.
`
`New Developments in Crystal Growirg
`
`‘me field of (‘Z growth is experiencing the emergence of several new tech-
`nologies in such diverse areas as control of oxygen by magnetic fields. liquid-
`silicon recharging. high resistivity. and furnace automation. An overview of
`these areas will provide a general idea of work currently under way.
`
`Magnetic CZ
`
`In ordinary CZ growth. thermal gradients set up convection currents that.
`when combined with crucible and crystal rotation. give rise to a general flow
`pattern such as that in Fig. 2. This convection-induced now transports oxy-
`gen through the melt into the liquid-crystal interface via dissolution of the
`quartz crucible.
`The convection currents also give rise to regularly occurring temperature
`transients at the melt-crystal interface. creating what is termed the melt-
`rctnclt phenomenon. This repetition of incremental solidification and melt-
`ing is implicated in the development of mierodefccts.
`Standard (‘Z pullers afford limited capability for oxygen control through
`such processes as changing rotation and pull speeds and hot-zone geometry.
`Recently it has been found that oxygen content and crystal striations may be
`reduced significantly by applying a transverse magnetic field to the silicon
`melt area in order to damp the liquid convection currents.‘ Several silicon
`
`FIG. 2—.\'rbrnum‘e repreraumon ofnrrll/low perm-ar irufloed by thermal comer-lion enlar-
`nhlr rotation.
`
`'Suruki. T.. lsawa. N.. Otubo. Y..and Haihi. K. in Seaarmnbrnw Siflwar I931. ll. R. Hull
`et al. Eds . Proceoditlgs cl Fourth International Symposium on Slicon Materials Science and
`Technology. The Electrochemical Society. Pennington. N. J.. l9Il.
`
`Raytheon2027R-0018
`
`

`
`10
`
`stucou PROCESSING
`
`FIG. 3—Dio:rm-v afmnamtr flu mm
`
`rkmud mawrrbm.
`
`producers are investigating the effects of this technique. known as magnetic
`CZ (MCZ).
`
`The MCZ effect offers a direct means of regulating oxygen transport and
`temperature transients. In principle. any motion of the highly conductive
`molten silicon is impeded when it crosses the magnetic flux field (Fig. 3).
`This provides a thick. stable boundary layer betwun the crucible wall and
`the bulk silicon melt. so that oxygen transport is limited to dilfusion through
`a stable liquid medium. At the same time. the temperature transients at the
`growth interface are suppressed: the result is a relatively steady instantane-
`ous growth rate.
`
`Continuous liquid-filicon Feed
`
`‘me concept of continuous liquid-silicon feed (CLF) has been under de-
`velopment for several yam. CLF employs a heated quartz tube to transfer
`liquid silicon from a meltdown chamber to a growth chamber. allowing for
`control ofdopant concentration in the feed material. and for semioontinuous
`replenishment of polycrystalline material and crystal solidification. Advan-
`tages include axially uniform crystal properties. improved productivity. and
`decreased crucible and power costs. Individual crystal sizes up to 65 kg have
`been achieved. and the process has shown capability for growing zero-defect-
`quality material. Operation of the CLF system is technically complex. how-
`ever. and additional furnace automation is required for production feasibil-
`ity. A schematic representation of a CLF system is shown in Fig. 4.
`
`High-R:sisrr'vr’ry CZ
`
`Historically. most requirements for resistivities greater than 25 ()-cm
`have been filled with material grown by the float-zone process. which uses no
`cntcible. Increasing demands for resistivities as high as 70 0-em have re-
`
`Raytheon2027R-0019
`
`

`
`FIG. 4—(‘rnu arenas offurnaee incorporating ecutrunmvs Iiqnidfrrd ofstficon aiming grin--rk.
`
`oently been satisfied with C2 material. Production experience to date indi-
`cates that extra care in doping and charge preparation can keep yields close
`to levels expected for standard product. provided that high-purity polycrys-
`talline material is used. General availability of the product may afford addi-
`tional flexibility in the design of high-speed memory devices.
`
`Furnace Automation
`
`To free the crystal growth process from operator judgment. it is desirable
`to have a computer monitor the process status and effect necessary changes.
`lmproved furnace mechanical design. coupled with the uniform consistency
`of digital control and new process transducers. will lead to substantial auto-
`mation. and preprogrammed process changes will give better run-to-run
`uniformity.
`Present activities emphasize effective use of linked automation and devel-
`opment of “recipe" loading systems that will facilitate end-user process de-
`velopment without the need for software and computer system skills. Figure
`5 shows a state-of-the-art computer-controlled furnace.
`
`Crystal Processing
`
`Slicing
`
`Conversion of ground ingots into slices (wafers) is accomplished primarily
`by inside-diameter (lD) diamond sawing. Machine technology has changed
`to accommodate larger ingots as well as new accuracy requirements. Typical
`
`Raytheon2027R-0020
`
`

`
`r12
`
`stuoou PflOO£S$lNG
`
`FIG. $—Genr-nil view of a oplavl evnrpurer-auurulld /imam: ml: 60%: (huge .tt':r
`capability.
`
`new machines incorporate hydraulically or mechanically tensioned blade
`heads in the 6816- to 762-mm-diameter range. using blades with l2- and I5-
`mil lterf widths and 2012- to 254-mm bores. Machine types currently avail-
`able include horizontal and vertical spindles with rolling-element and air-
`bearing construction. All types are successfully in use by leading silicon
`producers. and automatic control-feedback features are becoming available.
`All saws allow adjustment of the ingot axis to permit cutting on the daired
`crystal orientation. Typical productivity figures for I00-mm wafers are 150
`to 220 wafers per 8-h shift. and blade life is in the range of 3500 to 7000 cuts.
`Control of planarity during the slicing process has become critical in the
`last three years. since repeated thermal processing of wafers has been found
`to exaggerate the distortions of wafer bow. Flatness of the polished wafer
`product also is influenced by how. because the subsequent grinding/lapping
`
`Raytheon2027R-0021
`
`

`
`aouomt on cavsm. GROWTH mo mocessme tecunotoev
`
`13
`
`F1G.6—(7au~wpviewa/lDuw..ritaviagaannurieNnled'es:tqfrunve.
`
`processes remove material from bowed wafers in an unpredictable manner.
`Most saws incorporate a means to facilitate bow control by measuring the
`dellcction of the blade during each wafer cut.
`Generally. a blade that cuts without lateral dcflection will deliver slices
`with minimal “cut-in“ bow. but how induced by nonsymrnetrical surface
`stresses on opposing faces may still exist. The saw operator nomtally moni-
`tors both blade deflcction and general wafer bow trends. and will correct the
`cutting action by a combination of blade-dressing techniques and blade
`tensioning.
`Figure 6 shows a prototype saw that allows the cut ingot face to be auto-
`matically raised during slicing. This semiautomatic device also allows the
`measurement for cut-in bow. and for initiation of a programmed blade-
`dressing sequence indicated by the direction and magnitude of the bow.
`Another feature that is becoming prevalent is “single-slice recovery".
`wherein a retrieval mechanism recovers each water and loads it into a con-
`ventional cassette. This feature eliminates drag of the blade on the return
`stroke. with improved safety and ease of operation.
`Wafer slicing and cleaning remain critical first fabrication steps. and a
`wafer with excmfi/e bow. lack of planarity. or worlt damage erutu prob-
`lems in further processing,
`
`L°PP5'l8
`
`Typically. the as-cut slice from an ID saw is not flat enough to meet pol-
`ished slice requirements. and a 1'ree-abrasive double-sided machining proces
`(lapping) is used to planar-ire both slice surfaces and provide uniform finish.
`
`Raytheon2027R-0022
`
`

`
`1. Loss ofdiametral accuracy.
`2. Rounding of the flat cusps.
`3. Angttlusltittingofthe wafer flat.
`4. Random sullopingoflhewaferedge.
`5. lnsulrtciettt control or top and bottom comouls.
`
`and high-speedgrinding with: preformed wheeL Aootmnon meth-
`'
`'
`odusesagrooved wheel rotztingatltt'glIspeed.whidtisheldauinstthepe-
`ripltery on slowly rotating water by a constant-force medunism. An aller-
`nativemethod(Fi¢.T)usesamultimpseqncnc:to9'indthcoutside
`diameter. top edge. and bottom edge on a am-controlled profile grinder.
`Advantage: include (I) accurate final diameter. independent or wa.fcI'-slarl-
`in; dimensions; (2) accurate primaty-flat and secondary-flat generation: and
`(3) independent selection of lop and bottom edge contours.
`
`Raytheon2027R-0023
`
`

`
`FIG. 7-Wqfen-edge pm/Ila-I that dbnauiou
`flan. anlcwu up allbornn ahanycn.
`
`cracks lend to prop:
`really in use (acid a
`
`xious oxides of nitrogen evolved. operator hazards.
`and a tendency towards nonuniform etch removal which leads to a non-
`planar wafer surface.
`For these and other reasons. caustic etching in high-tempemun: (70 lo
`
`Raytheon2027R-0024
`
`

`
`.16
`
`stuoort mocesstua
`
`l30’C) potassium or sodium hydroxide has become commonplace in the last
`two years. Although time cycles are considerably longer than with acid.
`material removal tends to be more uniform. and the etched wafer flatter.
`Process characteristics are more uniform throughout bath life. and both et-
`chant costs and air pollution are reduced.
`Rinsing is particularly important alter caustic etching. and several stages
`of deionized (DI) water rinse may be necessary. The wafer surface tends to
`be grainicr or rougher after caustic etch. which leads to occasional problems
`with backside
`Residual sodium-potassium contamination
`has not presented problems.
`
`Gerrering
`
`Controlled residual wort damage on the backside or at strain sites in the
`silicon lattice acts to “getter-“ various ipurities during thermal processing.
`preventing their migration upward into active device regions. Common meth-
`ods of introducing controlled backside residual damage include:
`
`I. Abrasive bln.sn’ng—Controllcd-diameter particles of alumina or other
`hard material are directed at high velocity apinst the wafer backside in a
`process similar to sandblasting.
`2. laser beanr—A small-diameter focused laser pulse of appropriate
`wavelenflh and energy strikes the surface and creates localized melting or
`material removal. A matrix of damage sites in thedesircd pattern is achieved
`by repeated pulsing.
`3. Direct 3In_'f0(‘( obra.rr'on—'l'he wafer is rotated on a vacuum chuclt and
`an abrasive-coated cloth or paper is moved radially in point or line contact
`with the wafer. leaving a series of concentric damage sites.
`4. Liquid llonlug—A high-velocity stream of liquid containing abrasive
`particles is traversed acres the wafer backside.
`
`In all systems of this type. major considerations are uniformity of damage
`depth and freedom from residual contamination. In addition. certain dam-
`age processes leave deep fasures which tend to pick up contaminants that
`cannot be easily detected or cleaned. and which diffuse through the wafer at
`subsequent steps. These processes all have different characteristics in terms
`of damage intensity and ease with which damage sites anneal out and lose
`effectiveness.
`
`A variety of thermal and chemical means are also available to improve
`gettering. One technique involves processing a wafer in a manner so as to
`achieve a sharp gradient of oxygen concentration at the polished surface.
`thus creating a “denuded zone“ which contrasts with relatively high oxygen
`content in the bulk of the wafer. Other techniques to achieve oxygen gra-
`dients are being explored experimentally. The concept of the silicon wafer
`
`Raytheon2027R-0025
`
`

`
`BONOHA ON CRYSTAL GROWTH AND PROCESSWG TECHNOLOGY
`
`17
`
`substrate as a homogeneous entity. polished on one side. is rapidly giving
`way to the recognition that many dtsirable properties can be deliberately
`and methodically created.
`Introduction of bacltsurfaee gettering is norrnally done following the etch-
`ing operation. and rigorous cleaning is neccsary prior to polishing.
`
`lnrernrediate Wafer Inspection
`
`After the slice/lap/etch operations. integrated automatic equipment (Fig.
`8) is used to inspect and sort the wafers for resistivity. thickness. bow. flat-
`nes. and surface appearance. Visual inspection of asrctched wafer surfaces is
`performed to check for etch stains. residual saw marlts. flakes and chips.
`edge contour. and uniformity of appearance. Although this operation relies
`heavily on human visual skill and