Raytheon2025R-0001
`
`Sony Corp. v. Raytheon Co.
`IPR2015-01201
`
`

`
`Published by
`Pan Stanford Publishing Pte. Ltd.
`Penthouse Level, Suntec Tower 3
`8 Tclnasck Boulevard
`
`Singapore (338988
`E—mz1i|: editurial@panstz|nfortl.z:nm
`Web: www.pa11stanforti.com
`
`British Library [2ataloguing-in-Publication Data
`A catalogue record for this book is available from the British Library.
`
`3D integration for VLSI Syste ms
`
`Copyright © 2012 by Pan Stanford Publishing Pte. Ltd.
`AH‘ rights reserved.
`
`/-iii rights reserved. This book. Or parts thereof may not be reproduced in any form
`or by (my means electronic or‘ mechanical, inciuding photocopying, recording or any
`information storage and retrievai system now known or to be inven ted, without written
`permission from the Pubiisherz
`
`copying fee
`in this volume, please pay 2:
`For photocopying of material
`through the Copyright Clearance Center,
`inc, 222 Rosewood Drive, Danvers.
`MA 01923, USA.
`In this case permission to photocopy is not required from
`the publisher.
`
`ISBN: 9 78-981- 4303-81-1 [Hardcover]
`ISBN: 978-981-4303-82-3 [eB00k}
`
`Printed in Singapore by Markono Print Media Pte Ltd
`
`Raytheon2025R-0002
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`

`
`Contents
`
`Preface
`
`Contents
`
`Chapter 1
`
`3D Integration Technology — Introduction
`and Overview
`
`Chuan Seng Tan, Kuan-Neng Chen and
`Steven]. Koester
`
`Chapter 2
`
`A Systems Perspective on 3D Integration:
`What is 3D? And What is 3D Good For?
`
`Phil Emma and Eren Kursun
`
`Chapter 3
`
`Wafer Bonding Techniques
`
`Bioh Kim, Thorsten Matthias, Vfarel Dragof,
`Markus Wimplinger and Paul Lindner
`
`Chapter 4
`
`TSV Etching
`Paul Werbaneth
`
`Chapter 5
`
`TSV Filling
`
`Arthur Keigler
`
`Chapter 6
`
`3D Technology Platform: Temporary Bonding
`and Release
`
`Chapter 7
`
`Chapter 8
`
`Mark Privett
`
`3D Technology Platform: Wafer Thinning,
`Stress Relief, and Thin Wafer Handling
`Scott Sullivan
`
`Advanced Die-to-Wafer 3D Integration
`Platform: Self-Assembly Technology
`
`Takafumi Fukushima, Kang-Wook Lee,
`Tetsu Tanaka and Mitsamasa Koyanagi
`
`Chapter 9
`
`Advanced Direct Bond Technology
`
`Paul Enquist
`
`Chapter 10
`
`Surface Modification Bonding at Low
`Temperature for Three-Dimensional
`
`Hetero-Integration
`
`Akitsa Shigetoa
`
`vii
`
`27
`
`43
`
`71
`
`91
`
`121
`
`139
`
`153
`
`175
`
`205
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`
`vlll Contents
`
`Chapter 11
`
`Through Silicon Via Implementation in CMOS
`Image Sensor Product
`
`231
`
`Xavier Gognard and Nicolas Hotellier
`
`Chapter 12
`
`A 300-mm Wafer-Level Three—Dimensional
`
`263
`
`Integration Scheme Using Tungsten Through-
`Silicon Via and Hybrid Cu-Adhesive Bonding
`Fei Lin‘
`
`Chapter 13
`
`Power Delivery in 3D IC Technology with a
`Stratum Having an Array of Monolithic
`DC-DC Point-of-Load [PoL] Converter Cells
`
`Ron Rutman andjfan Sun
`
`Chapter 14
`
`Thermal-Aware 3D IC Designs
`
`Xiaoxia Wu, Yuan Xie and V:]'aykirshnan
`Narayanan
`
`Chapter 15
`
`3D IC Design Automation Considering
`Dynamic Power and Thermal Integrity
`
`Hao Yu and Xfwei Huang
`
`Chapter 16
`
`Outlook
`
`Ya Lon Yang
`
`index
`
`297
`
`313
`
`335
`
`351
`
`367
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`Chapter 1
`
`3D INTEGRATION TECHNOLOGY -
`
`INTRODUCTION AND OVERVIEW
`
`Chuan Seng Tan
`Naryong Thzllnolqylcal Uniwrstty
`
`Steven ]. Koester
`University oiMmn:-mta
`
`Kuan-Neng Chen
`National (‘Auto Tung Umsvrstry
`
`1.1 INTRODUCTION
`
`The past decade has seen thnee-dimensional [3D) integration technology
`mature rapidly from a hypothetical concept to a technology that is on the
`cusp widespread commercial implementation. This rapid trend towards
`acceptance of 3D integration has been both a result or key demonstrations
`of the technical feasibility of the process, as well as a growing consensus that
`30 integration will be necessary to continue current computational system
`performance trends. 3D technology also ofiers an abundance of opportunities
`for new applications and functionality.
`In this introduction, we provide an
`overview of the system needs that are driving 3D integration development,
`the recent advances in the underlying technology that have been key to its
`recent acceptance, and new opportunities for additional functionality that
`30 has the potential to provide.
`
`30 Intcavotion for VLSI Systems
`(died In Chum Sena Tin, Kuan-Mme Chat and Steven L Koester
`Copyright 0 2012 by Dan Slanlovd Publishig Pto. ud.
`wuw.pansunlordAom
`
`
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`2
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`JD integration Teehrroiboy mrmdur rioo and Overview
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`1.2 DRIVERS AND APPLICATIONS
`
`The driving fume for microprocessors in the last several decades has been the
`scaling of Si metal-oxide semiconductor field-effect transistors (MOS!-‘E'l's),'
`which has allowed transistordimcnsions to shrink from fractions ofmillimeters
`in the l960's. to the 10's ofnanometcrs in present-day technologies. As Gordon
`Moore predicted in his seminal paper.‘ reducing the feature size also allows
`chip area to be decreased. improving production thereby reduong cost per
`function. The saling laws original put in place by Dennard‘ also showed that
`improved device and ultimately processor speed could be achieved through
`dimensional scaling. The impact of these trends on society has been nothing
`short of remarkable, as computational systems have become an indispensible
`aspect of nearly every facet of society. llowever, all trends ultimately have
`limits, and Moore's Law is no exception The limits to Moore's Law scaling
`have come simultaneously from many directions Lithographic limits have
`made it extremely difficult to pack more features onto a semiconductor chip.
`and the most advanced lithographic techniques needed to scale are becoming
`prohibitively expensive for most labs.’ Furthermore, short-channel effects
`and random fluctuations are making conventional planar device geometries
`obsolete‘ Finally, the fact that scaling has proceeded without appreciable
`voltage reduction over the past decade has increased power densities to
`the precipice of cooling and reliability limits’ This latter fact has essentially
`ended dock frequency enhancement as the primary driver of rnicro-processor
`performance improvement
`Amidst this landscape. multi-core architectures have become the new
`engine driving system-level pcrfomiance enhancement“ In multi-core
`architectures. computation proceeds in parallel. thereby lesscningthe frequency
`requirements for the individual cores. Instead of increasing clock frequency,
`performance enhancements can be achieved by adding cores. Reducing the
`frequency of individual cores is particularly beneficial from a power point of
`view, since it allows the supply voltage to be redumd, which in turn improves
`computational efficicncy.
`llowever, multi-wre architectures place new
`requirements on the technology. and as we will show, these requirements are
`ideally met by utilizing 3D integration. The main requirement for multi-core
`architectures 15 increased memory bandwidth (either main memory or cache).
`This condition derives from the well-known law’ that states that the cache
`miss rate goes as the inverse square root of the niche size for .1 single core,
`and as the number of cores is increased. the cache capacity must be increased
`geometrically for each additional core added
`30 offers the opportunity to inaease the amount of available memory
`to multi-core processors by stacking additional primary or ache memory
`on the chip. as opposed to relying upon oil’-chip access 30 integration can
`also increase the aggregate bandwidth to this memory since it provides
`much greater density of interconnects than traditional C45. Finally. the
`power required to access memory through 3D interconnects is reduced
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`-
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`Drivers and apllicvtions
`
`3
`
`compared to off-chip memory since smaller. less power-hungry interconnect
`drive circuits are needed due to the reduced interconnect capacitance. A
`conceptual diagram showing the benefits of 3D integration for multi-core
`memory design is shown in Fig. 1.1.‘
`
`.__g
`
`innor’ ,-.-:'V'
`
`(3)
`
`(bl
`
`Fig. 1.! Conceptual diagram showing core and memory partitioning for (a) 2D and
`(in) 3D chip designs (adapted from Ref. 8).
`
`if memory expansion for multi-cone architectures were the only
`application of 3D technology, enthusiasm for 3D technology development
`might have been substantially more muted. However. 3D technology has
`potential to benefit computational systems in a vast number of new ways.
`For instance. voltage regulation is another aspect of multi-core architectures
`where 3D could provide tremendous benefits."° The advantages ofa 3D chip
`with a dedicated voltage regulation layer compared to a 20 system with off-
`chip regulation aresubstantial.‘ First.3D reducestheresistancebetween the
`
`voltage source and chip, minimizing supply voltage droop 3D also allows the
`use of multiple voltage planes. potentially one of every core. This would allow
`the supply voltage of the cores to be precisely tuned for optimal performance,
`and even allow cores to be turned on’ if needed.
`it has also been proposed
`that if switching converters are utilized, PR losses through the package could
`be reduced since the power would enter the package at a higher voltage than
`the chip supply voltage.“
`3Dtechnologylsalso useful fora varietyofadvanced memoryapplications.
`For flash technology, fonn factor is the overriding concern. and therefore
`3D integration can provide increased density within a given footprint On
`the other hand. the benefits of 3D stacking for SRAM and DRAM technology
`result both from inaeased areal density and inaeased performance." With
`suflicient interconnect density. a 3D DRAM an partitioned with the memory
`controller on one layer. and the arrays on the remaining layers, resulting in
`significant improvement in access time.“
`
`'
`I
`‘
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`|
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`1
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`4 30 mtegrooon recnncdoay - Introduction and 0w~r\a'ew
`
`Perhaps some ofthe most intriguing aspects of 3D integration technology
`are the new capabilities that could be brought to bear by bringing very
`dissimilar technologies into intimate contact. One interesting possibility
`is the integration of 3D photonic interconnects with multiscore processors,
`which have the potential to dramatically reduce the power of interconnects
`particularly in the reginie where the interconnect distance is long, and the
`data rates are high. A conceptual 3D optical interconnect scheme is shown
`in Fig, 1.3." Here a complete network-on-a-chip is shown, which utilizes 2)
`bottom multi-oone processor layer, an intermediate memory layer, and an
`optical interconnect layer on top. In such a system. local interconnects could
`be provided by standard met.-il wiring. wheneas global connections would be
`made mziiig a photonic interconnect fabric consisting of silicon waveguides.
`The interconnect power has been calculated for such .1 schcmeand Ls found to
`be nearly 2 orders ulmagnitude lower compared to electrical interconnects."
`The photonlt‘. network provides the additional advantage that off-chip I/0 is
`achieved at the same bandwidth with little additional power.
`
`On chip optical routing
`
`Processor layer
`
`Photonic layer network
`Memory layer
`
`Fig. 1-2 Conceptual diagraiii of a ‘JD integrated pliotonic iiitemonnect network
`(adapted from Ref. I2)
`
`Co-integration of lll-V components with CMOS is another possible
`application of 3D iiitegrattoii that could have a profound impact on high-
`performance systems The optical properties oflll-V are the most compelling
`
`detectors" could provide additional performance enhancement and
`design flexibility for photonic interconnects." The work in" is par1ic-ularly
`intriguing as the heterogeneous integration is performed at the device level,
`creating an entirely new device, in this case by integrating a Ill-V optical gain
`or absorbing region with a Si wavegiiide.
`Integration of high-speed Ill-V
`electronic devices has also be proposed to improve performance of mixed-
`signal chips by integrating either high-speed or high-power Ill-V FETs or
`H813 with CMOS digital cirruitry.“' Future challenges for heterogeneous 3D
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`Classification
`
`5
`
`integration will certainly tndude yield, reliability and cost. However, in the
`end, if basic manulacturability issues can be addressed, heterogeneous 3D
`technology could allow new applications for Si-based systems by allowing
`each sub-component to be optimized according to its specific lunction
`without the trade-offs assodated with monolithic integration.
`
`1.3 CIASSIFICATION
`
`System Integration Landscape
`
`FormFactor
`
`-—omelet
`
`ctmun-to-ctn:uIt hteroonnoct ooncsiy
`
`L"3"'2-
`
`Fig. 1.3 Comparison of various system integration technologies in terms ol form fac-
`tor and circuit-to-circuit interconnect dcrtsity."'9 IEEE 2007.
`
`System integration, that is, the integrating together of circuits or intellectual
`property (IP) blodts, is one of the mayor applications of 3D integration.
`As such. 30 integration must compete against a number of established
`technologies. Figure 1.8 compares the relative capability of several system
`integration methods (board. 2D multi-chip module - ZD-MCM, package-om
`package - Pol’, wstaem-in-package - SiP, and 20 system-on-chip — 20-800
`in terms of form factor and interconnects density between circuit blocks“
`3D integration offers more compact form factor and higher drip-to-chip
`interconnects density. Comparing with 2D-Soc, 3D integration shortens time-
`to-market and lowers the system cost. By using larger number of smaller
`and shorter through silicon via ('l’SV] as compared to wire bonding in Sil’,
`performance is enhancement via 30 integration due to smaller latency and
`higher bandwidth. as well as smaller power consumption
`
`
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`6 JD Integration Tedtnology - lhtroducttonandovervleiv
`
`Classification
`
`There are a number of technology options to arrange integrated circuits in a
`vertical stack It is possible to stack lCs in a vertical fashion at various stages
`of processing: [1] post-singulation 3D packaging (e.g. chip-to-chip). and (2)
`pne-singulation waferlevel 3-D integration [e,g. chip-to-wafer, wafer-to-wafer,
`and monolithic approaches). Active layers can be vertically interconnected
`using physical contact such as bond wine or interlayer vertical via (including
`'l'SV). It is also possible to establish chip to chip connection via non-contact
`[or wireless) links such as mpacitive and inductive couplings I 17]. Capacitive
`coupling utilizes a pair of electrodes that are formed using conventional IC
`fabrication. The inductive-coupling l/0 is formed by placing two planar coils
`(planar inductors) above each other and is also made using conventional IC
`fabrication. The advantages of these approachw are fewer processing steps
`hence lower cost. no requirement for BSD protection. low power. and smaller
`area l/0 cell.
`Since there is substantial overlap between various options and lack of
`standardization in terms of definition, classification of 3D IC technology is
`olten not straight forward. This chapter makes an attempt to classify 3D IC
`based on the processing stage when stacking takes place.
`
`Monolithic Approaches
`
`in these approaches. devices in each active layer are processed sequentially
`starting from the bottom-most layer: Devices are built on a substrate wafer by
`mainstream process technology. After proper isolation. a second device layer
`is formed and devices are processed by conventional means on the second
`layer: This sequence of isolation, layer formation, and device processing can
`be repeated to build a multi-layer structure.
`The key technology in this approach is forming a high quality active
`layer isolated from the bottom substrate. This bottom-up approach has the
`advantage that precision alignment between layers can be accomplished.
`However: it suffers from a number of drawbacks The crystallinlty of upper
`layers is usually low and imperfect. As a result. high performance devices
`cannot be built in the upper layers. Thermal cycling during upper layer
`crystallization and device processing can degrade underlying devices and
`therefore a tight thermal budget must be imposed. Due to the sequential
`nature of this method, manufacturing throughput is low. A simpler FEOL
`process flow is feasible if polycrystalline silicon can be used for active devices;
`however; a major difficulty is to obtain hiyi-quality electrical devices and
`interconnects. While obtaining single-crystal device layers in a generic IC
`technology remains in the research stage. polycrystalline devices suitable for
`non-volatile memory (NVM) have not only been demonstrated but have been
`commercialized (for example by SanDislt). A key advantage of FEOL-based
`3-D integration is that IC BEOL and packaging technologies are unchanged:
`all the innovation occurs in 3-D stacking ofactive layers.
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`Oassifirvtion
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`7
`
`A number of FEOL techniques include: laser beam recrystallization.“ "’
`seeding-assisted recrystallization?‘ “' selective epitaxy and over-growth.“
`and grapho-exitaxy.‘-‘
`
`Assembly Approaches
`
`This is a parallel integration scheme in which fully processed or partially
`processed integrated circuits are assembled in a vertical fashion. Stacking
`can be achieved with one of these methods: (1) chip-to-chip, (2) chip-to-
`wafer. and (3) wafer-to-wafer. Vertical connection in chip-to-chip stacking
`can be achieved using wine bond or through silicon via (TSV).
`Wafer level 3D integration. such as chip-to-wafer and wafer-to-wafer
`stacking, use TSV as the vertical interconnect. This integration approach
`often involves a sequence of wafer thinning and handling. alignment. TSV
`formation, and bonding. The key diflerentiators are:
`
`0
`
`0
`
`-
`-
`
`Bonding medium — metal-to-metal. dielectric-to-dielectric (oxide.
`adhesive. etc) or hybrid bonding;
`TSV fonnation — via first. via middle or via last;
`
`Stacking orientation — face-to-face or back-to-face stacking;
`Singulation level — chip-to-diip. chip-to-wafer or wafer-to-wafer.
`
`
`
`Ioduuinland
`finlritallondt
`
`Vb Dudqlndlng
`
` Dunne-aqua
`
`Ilfiridlorultug
`‘
`’ Hfiédnd
`(lots-wallet
`
`‘
`
`lb 031* Ij;
`
`Fig. 1.4 Wafer bonding techniques for wafer-level 3-D integration: [3] dielectric-cm
`dielectric (b) metal-to-metal; and (c] dielectric/metal hybrid.
`
`The types of wafer bonding potentially suitable for wafer-level 3D
`integration are depicted in Fig. 1.4. Dielectric-to-dielectric bonding is most
`commonly accomplished using silicon oxide or BCB polymer as the bonding
`medium. These types of bonding provide primary function as a mechanical
`bond and the inter-wafer via is formed after wafer-to-wafer alignment and
`bonding [l-‘ig. I.4(a)). when metallic copper-to-copper bonding is used
`(Fig. l.4(b)). the inter-wafer via is completed during the bonding process;
`note that appropriate interconnect processing within each wafer is required
`to enable 3D interoonnectivity. Besides providing electrical connections
`
`
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`8 Jolntegrouon lechnology-mtroductlooandorervrav
`
`between IC layers. dummy pads can also be inserted at the bonding interface
`at the same time to enhance the overall mechanical bond strength This
`bonding scheme inherently leaves behind isolation gap between Cu pads and
`this could be a source ofconcern for moisture corrosion and compromise the
`structuml integrity especially when 1c layers above the substrate is thinned
`down further. Figure 1.4(c] shows a bonding scheme utilizing a hybrid
`medium of dielectric and Cu. This scheme in principle provides a seam-
`less bonding interface consists of dielectric bond (primarily a mechanical
`bond) and Cu bond (primarily an electrical bond]. However. very stringent
`requirements with regards to surface planarity [dielectric and Cu] and Cu
`contamination in the dielectric layer due to misalignment are needed.
`
`"" "“ FE>2ee3>E->
`"" “°"'° LEEZSDZE
`
`Fig. 1.5 TS! can be formed at various stages of IC processing.
`
`to
`The selection of the optimum technology platfonn is subject
`ongoing development and applications. Cu-to-Cu bonding has significant
`advantages for highest
`inter-wafer interoonnectivity. As a result.
`this
`approach is desirable for microprocessors and digitally~based system-on-
`a-chip (Soc) technologies. Polymer-to-polymer bonding is attractive when
`heterogeneous integration of diverse technologies is the driver and the
`inter-wafer interconnect density is more relaxed: benzocyclobute (BCB) is
`the polymer most widely investigated. Taking advantage of the viscosity of
`the polymer, this method is more forgiving in temis of surface planarity and
`particle contamination. Oxide-to-oxide bonding of fully processed IC wafers
`requires atomic-scale smoothness of the oxide surface. in addition. wafer
`distortions introduced by FEOL and Bl’.-ZOL processing introduces sufficient
`wafer bowing and warping that prevents suilicient contact area to achieve
`the required bonding strength. While oxide-to-oxide bonding alter FEOL and
`local interconnect processing has been shown to be promising (particularly
`with S0! wafers that allows for extreme thinning down to the buried oxide
`layer) the increased wafer distortion and oxide roughness alter multilevel
`interconnect processing require exua attention during processing.
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`CIOwfiwD'arI9
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`Fig. 1.6 (Top) Face-to-lace or face-down stadung (Bottom) Back-to-face or
`bce~up stacking,
`
`TSV can be formed at various stages during the 3D IC process as shown
`in Fig. 1.5. When TSV is formed before any CMOS processes. the process
`sequence is known as ‘via first". It is also possible to form the TSV when
`the front end processes are completed. In this ‘via middle‘ process, back
`end processes will continue alter the T51! process is completed. when
`‘PS1! is formed after the CMOS processes are completed. it is known as ‘via
`last" process. TSV can be formed from the front side or the back side of the
`wafer. The above schemes have different nequiremcnts in terms of process
`parameters and materials selection. The choice depends on final application
`requirements and infrastructures in the supply chain.
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`
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`10 Jblnteorodon ledmolooy-mtruductionondonerview
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`Another key differentiator in 3D IC integration is related to the stacking
`orientation. One option is to perform face-to-face [F2i-‘] alignment and
`bonding with all required i/Os brought to the thinned backside of the top
`wafer [which becomes the face of the two-wafer stack). Another approach is
`to temporarily bond the top wafer to a handling wafer. after which the device
`wafer is thinned from the back side and permanently bonded to the full-
`thicltness bottom wafer: after this permanent bonding the handling wafer is
`removed. This is also called a back-to-face (B2F] stacking. These two stacking
`orientations are shown in Fig, 1.6.
`
`‘liable 1.1 Comparison between wafer-trrwafer and chip-to-wafer stacking
`
`Wafer-to-Wafer
`
`Chip-to-wafer
`
`Wafer/die
`Size
`
`Wafer/die of oommon Disimilar wafer/die size is
`size in order to avoid
`acceptable
`silicon area wastage
`
`Throughput
`
`Wafer scale
`
`Die scale
`
`Yield
`
`Lower than lowest
`yield wafer, therefore
`high yield wafer must
`be used
`
`Known good die can be used if
`pre-stacking testing is available
`
`Alignment
`accuracy
`
`<2 um global
`alignment
`
`~10 um for M000 dph
`<2 pm for <l00 dph
`
`FZF stacking allows a high density layer to layer interconnection which is
`limited by the align ment accuracy. Handle waferis not required in l~‘2Fstacking
`and this imposes more stringent requirement on the mechanical strength of
`the bonding interface in order to sustain shear force during wafer thinning
`which is often achieved by mechanical grinding or polishing. Since one of the
`IC layer is facing down in the final assembly. I-‘2i-‘ stacking also complicates
`the layout design as opposed to more conventional layout design whereby IC
`layers are facing up. Another potential disadvantage of i'-‘2F stacking relates
`to the thickening of the ILD layer at the bonding interface which presents
`higher barrier for effective heat dissipation. 82F stacking requires the use
`of a temporary handle and the layer to layer interconnection density is
`limited by the TSV pitch. Since the device layer is bonded to a temporary
`handle, the final permanent bond does not sustain damage resulting from
`wafer thinning, It requires the use ofa temporary bonding medium that can
`provide sufficient strength during wafer handling and can be readily released
`after successful device layer permanent transfer on the substrate.
`in wafer level 3D innegration, pennancnt bonding an be done either
`in chip-to-wafer (CZW) or wafer-to-wafer (WZW) stacking, A comparison
`of these two methods is summarized in Table 1.1. As shown in Fig. 1.7. the
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`CIOSSIIVUONVI
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`1]
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`option of CZW or WZW depends on two key requirements on chip size and
`alignment accuracy. When high precision alignment is desired in order to
`achieve high density layer to layer interconnections, WZW is a preferred
`choice to maintain acceptable throughput by performing a wafer level
`alignment. W2W is also preferred when chip size gets smaller:
`
`Alignment
`
`Fig. 1.7 The choice between CZW and WZW depends on the chip size and the
`required alignment accumcyt
`
`3D Interconnect Technology Definitions by ITRS
`
`Since 3D technology is actively pursued by almost all payers (such as lC
`foundry, semiconductor assembly and test. printed circuit board, and
`assembly] in the electronic manufacturing supply chain, a broad variety of
`technology is being proposed. As a result, the u-aditional interfaces between
`all these players are blurring, In order to come to a clear vision on roadmaps
`for 30 technologies. it is important to come to a clear definition of what is
`understood by 3D interconnect technology. The International Technology
`Roadmap for Semiconductor [l‘l'RS), in the 2009 report on interconnect, has
`proposed a classification of the wide variety of 3D technologies" that capture
`the functional requirements of 3D technolog at the dilferent hierarchical
`levels of the system and correspond to the supply chain manufacturing
`capabilities The following is summary of 30 definitions and naming
`conventions proposed by ITRS.
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`Jomtearotron kchnology-snrrodixuon rmaowmitw
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`technology which allows for the vertial
`30 Interconnect Technology -
`stacking of layers of "basic electronic components" that are connected using
`a 2D-interconnect fabric are listed below. ‘Basic electronic components‘ are
`elementary circuit devices such as transistors. diodes, nesLstors. capacitors
`and inductors. A special case of 3D interconnect tedinoloy is the Si
`interposer structures that may only contain interconnect layers. although
`in many cases other basic electronic components [in particular decoupling
`capacitors) may be embedded.
`
`3D Bonding - operation that joins two die or wafer surfaces together.
`
`30 Stacking - operation that also realizes electrical interconnects between
`the two device levels.
`
`- 3D integration using “traditional” packaging
`3D-Packaging (30-P)
`technologies. such as wire bonding, padcage-on-package stacking or
`embedding in printed circuit boards.
`
`3D-Wafer-Level-Packaging (30-WLP) - 3D integration using wafer level
`packaging technologies. performed after wafer fabrication. such as flip-chip
`redistribution. redistribution interconnect. fan-in chip-size packaging. and
`fan-out reconstructed wafer chip-scale packaging
`
`3D-System-on-chip {3D-SOC ) - Circuit designed as a system-on-chip, SOC, but
`realized using multiple stacked die. 3D-interconnects directly connect circuit
`tiles in different die levels. These interconnects are at the level of global on-
`chip interconnects This allows for extensive use/reuse of IP-blocks.
`
`3D approach using direct
`-
`(30-SIC)
`3D-Stacked-Integmted-Circuit
`interconnects between circuit blocks in different layers of the 3D die stack
`Interconnects are on the global or intennediate on-chip interconnect levels.
`The 3D stack is characterized bya sequence of alternating front-end [devices]
`and back-end (interconnect) layers.
`
`30-fntegmted-Circuit (3D~IC) - 3D approach using direct stacking of active
`devices lnteroonneds are on the local on-chip interconnect levels The
`30 stack is diaracterlzed by a stack of front-end devices. combined with a
`common back-end interoonned stack.
`
`Table 1.2 (reproduced from ITRS) presents a structured definition of
`3D interconnect technologies based on the interconnect hierarchy. This
`structune also refers to the industrial semiconductor supply chain and
`allows definition of meaningful roadmaps and targets for each layer of the
`interconnect hierardiy.
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`Table 1.2 3D Interconnect Technologies Based on Interconnect Hicrarchyt“
`
`Clauifiacoanls
`
`JD-warn-level Water-level
`
`u Traditional packaging cl um.-rmnnecl
`Iedmologhs. cg. vnn:- bonded die
`SIJGS. patina-on-padage slacks.
`- Also ildudes die in PCB integration.
`- No untough-Si~vias ['I‘SVs].
`
`0 WLP infnstxuctun. sum as
`mdisu-ibution layer (RDLJ and bumping.
`0 3D inteunnnccls an pmrcssed allzr the
`[C hhriution. 'post IC-poss‘Nab’on' (via
`last process). Cooncmnm on bond-pad
`Iv.-v:L
`o T51! densly mqum.-Inents lollow bond-
`pad density rnadmaps.
`
`0 Sudan; of Iamecimnit blocks (tiles.
`IP«hIoc|s. memory -hanks), simiar no
`an Soc appmach but Inning cilulils
`physnralty on different laytn.
`0 Un-buficnd I/0 drivers (lawC, link or
`no ESD pmtmlon on T593).
`o tsv density mzuimm.-nl signifiantly
`hidlcr than 3D-WLP: Pilth requirement
`down to 4-] sum.
`
`0 Station; of smallet circuit blodu.
`pans of IP-blocks sucked in vertical
`dimensions.
`0 Manly wafer-co-wfler sucking.
`a T511 density requirements wry hgh:
`Piuh requmemrnl down to I-4 um
`
`Waier Fab
`
`3lHm.egmud
`(limit
`(3046)
`
`0 Staddm of transistot lawn.
`a common BEOI. inu.-manner! start on
`muluplc layers ol FEOL
`- Rcqumrs 30 (onneuions at the density
`level I)! Iota] inlermnneds
`
`
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`JD integration mmofow - Irltlodvcubvr and ovum.-vr
`
`1.4 TECHNOLOGY PLATFORMS AND STRATEGIES
`
`A number of new enabling technologies must be developed and introduced
`into the existing fabrication process flow to malne 3D integration a mlity.
`Depending on the level ofgranularity, new capabilities inciurle wafer bonding
`(permanent or temporary], through silicon/strata via (1‘SV], wafer thinning
`and handling, precision alignment. and other related technologies. There are
`a number of references on technology platforms available in the literature and
`the references therein.i‘- "' A brief introduction to TSV process flow is given
`below and detailed coverage can be found in subsequent chapters on deep
`via etching and Cu filling This section primarily discusses low temperature
`Cu-Cu permanent bonding which is the author's core research expertise.
`
`Through Silicon Vin
`
`
`
`I-Iolupoet
`rdofidlfl
`entity
`
`I.iner-denosilon.
`lolouodby
`blrriotmtloood
`Iryotodopocltion
`
`stperoouorrnnl
`Cufinn
`
`ltunovdotcu
`ever-burden
`
`Fig. 1.8 A generic process flow of Cu-filled TSV fabrication.
`
`Figure 1.15 is a generic process flow of TSV fabrication flow using Cu as the
`core metal. It begins with high aspect ratio deep etching of Si. Dielectric liner
`layer is then deposited on the via sidewall followed by barrier and Cu seed
`layers deposition. Liner layer. which is made ofdielectric layer such as silicon
`dioxide. provides electrical isolation between Cu con: and Si substrate. The
`liner thidmess must be chosen appropriately to control leakage current and
`capacitance between Cu core and Si substrate. Cu super confomtal filling is
`then achieved with electro-plating process. Super conformal filling is required
`to prevent void fonnation in the Cu TSV. Finally, Cu over-burden is removed
`by chemical mechanical polishing. More information on TSV fabrication can
`be found in Chapoers 4-5.
`
`Cu-Or Pennanent Bonding
`
`3D integration of integrated circuits by means of bump-less Cu-Cu direct
`bonding is an atu-active choice as one accomplishes both electrical and
`mechanical bonds simultaneously. Cu-Cu direct bonding is desired compared
`to solder-based connections because: (I) Cu-Cu bond is more scalable and
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`feenoalogy Pfntfomrs ondsrmugios
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`ultra-line pinch can be achieved; (2] Cu has better elect:rical and themial
`conductivities; and (3) Cu has much better electro-migration resistance and
`can withstand higher current density in future nodes. Cu-Cu bond has better
`properties due to the absence of inter-metallic compound (lMC] found in
`solder based joint.
`Direct Cu-Cu bonding has been demonstrated using thermo-
`oompression bonding (also known as diffusion bonding]. As the name
`implies, thermo-compression bonding involves simultaneous mechanical
`pressing (~ 200 ltPa) and heating of the wafers (~ 300-400“C). Two wafers
`