United States Patent £!9J
`Cote et al.
`
`(II] Patent Number:
`(45] Date of Patent:
`
`4,910,155
`Mar. 20, 1990
`
`(54} WAFER FLOOD POLISHING
`
`[?5]
`
`Inventors: William J . Cote, Essex Junction;
`Michael A. Leach, Bristol, both of
`Vt.
`
`[73] Assignee:
`
`International Business Machines
`Corporation, A rmonk, N.Y.
`
`[21] Appl. No.: 263,842
`
`[22] F iled:
`
`Oct. 28, 1988
`
`[51]
`..... . ..................................... H OlL 21/304
`Int. Cl.4
`(52] U.S. Cl. ........................................ 437/ 8; 437/ 225;
`437/228; 156/636; 156/637; 51/90
`(58] Field of Search ....................... 156/636, 637, 645;
`437/225, 228, 8; 51/ 7, 90, 317
`
`[56]
`
`References Cited
`U.S. PATENT D OCUMENTS
`2,922,264 1/1960 Mushrush .............................. 51/281
`3,342,652 9/1967 Reisman et al. ...................... 156/17
`3,436,286 4/1969 Lange .................................. 156/636
`3,615,955 10/1971 Regh ................................... 156/636
`3,841,031 10/1974 Walsh .................................. :. 51/283
`4,2!56,535 3/1981 Banks .................................. 156/645
`4,373,991 2/1983 Banks .................................. 156/645
`4,671,85 I 6/1987 Beyer et al. ......................... 156/645
`4,702,792 10/1987 Chow et al. ........................ 156/628
`4,710,264 12/ 1987 Waschler et al. ................... 437/228
`
`F OREIGN PATENT D OCUMENTS
`
`0147589 4/ 1981 German Democratic
`Rep . .................................... 156/645
`
`OTHER PUBLICATIONS
`J . B. Brinton, "Spinning E tchant Polishes F lat, Fast",
`Electronics, Jan. 13, 1982, vol. 55, No. I, pp. 40-41.
`Y. Namba et a!., " Ultrafine Finishing of Ceramics and
`Metals by F loat Polishing", Laser Induced D amage in
`Optical Materials: 1980, Proceedings of a Symposium
`(NBS-SP-620) Boulder, Colo., 30 Sep.-1 Oct. 1980, pp.
`17 1- 179.
`Primary Examiner-O lik Chaudhuri
`Attorney, Agent, or Firm-William D . Sabo
`
`ABSTRACT
`(57]
`In a chem·mech polishing process for planarizing insu·
`lators such as silicon oxide and silicon nitride, a pool of
`slurry is utilized at a temperature between 85' F .-95' F .
`T he slurry particulates (e.g. silica) have a hardness com(cid:173)
`mensurate to the hardness of the insulator to be pol·
`ished. Under these conditions, wafers can be polished at
`a high degree of uniformity more economically (by
`increasing pad lifetime), without introducing areas of
`locally incomplete polishing.
`
`20 Claims, 1 Drawing Sheet
`
`001
`
`SONY 1008
`
`

`
`. U.S. Patent
`« US. Patent
`
`Mar.20, 1990
`Mar. 20, 1990
`
`FIG.l
`F IG.1
`
`4,910,155
`4,910,155
`
`30
`
`10
`
`12
`
`16
`
`20
`
`(
`
`16
`
`F162
`FIG.2
`
`30
`30
`
`•14
`014
`
`10
`10
`
`12
`12
`
`002
`
`002
`
`
`

`
`1
`
`4,910,155
`
`WAFER FLOOD POLISHING
`
`2
`No. 4,702,792 (issued 10/27/87 to Chow et al and as(cid:173)
`signed to ~BM), in which a polymer film is chem-mech
`polished to define an image pattern.
`BACKGROUND OF THE INVENTION
`In the above chem-mech polishing art, the amount of
`5 slurry is kept to a minimum. Typically, the slurry is
`1. Technical Field
`applied by a dropper suspended above the center of the
`The invention relates to a method of planarizing
`polish wheel. As the wheel spins, the slurry is spread
`workpieces utilizing an abrasive slurry in conjunction
`over the polish pad. Examples of low slurry content
`with a polishing pad.
`polishing are shown in U.S. Pat. No. 3,841,031, entitled
`2. Background Art
`In the art of forming metallic interconnection layers 10 "Process for Polishing Thin Elements"; U.S. Pat. No.
`3,342,652, entitled "Chemical Polishing of A Semi-Con(cid:173)
`on processed semiconductor substrates, it is known that
`ductor Substrate"; U.S. Pat. No. 4,256,535, entitled
`various processing difficulties are presented if the pri(cid:173)
`"Method of Polishing a Semiconductor Wafer"; U.S.
`mary passivation layer has an irregular topography.
`Pat. No. 4,373,991, entitled "Method and Apparatus for
`Such difficulties include unacceptable variations i metal
`layer thickness, which result in the possibility of unde- 15
`Polishing A Semiconductor Wafer"; and an article enti(cid:173)
`sired metal opens/shorts.
`tled "Spinning Etchant Polishes Flat, Fast" Electronics,
`At first, this problem was dealt with by using a pas(cid:173)
`Jan. 13, 1982, pp. 40-41.
`sivation material (such as phosphosilicate glass (PSG)
`Use of low slurry content polishing leads to several
`or boro-phosphosilicate glass (BPSG)) that could be
`difficulties. One difficulty is shortened polish pad "life(cid:173)
`melted (or reflowed) to smooth out the upper surface. 20
`time." Pad lifetime relates to the total number of wafers
`While this solution was perfectly acceptable for the
`that can be polished by a given pad. As the pad wears
`device densities of the day, recent advances in integra(cid:173)
`out, both the removal rate of the polished material and
`tion have forced workers in the art to consider other •
`the uniformity of removal across the wafer substantially
`alternatives. One such alternative is the socalled "plana(cid:173)
`degrade. Pad lifetime is determined by the hardness of
`rizing etch,back" procedure, in which a layer of con- 25
`the pad, the polish conditions, and the break-in/condi(cid:173)
`ventional photosensitive polymer (or "photoresist") is
`tioning procedures. Typically, in order to provide suffi-
`spin-applied on top of the passivation layer. The photo(cid:173)
`cient wetting of a polishing pad used in conjunction
`resist presents a planar upper surface. Then using an
`with a small amount of slurry, the pad must undergo a
`etch technique that is non-selective between the photo(cid:173)
`destructive break-in procedure (e.g., high-pressure
`resist and the passivation layer, the layers are simulta- 30
`scraping using a blade), as well as periodic conditioning
`neously etched such that the planar upper surface of the
`(lower pressure scraping). Such procedures substan-
`photoresist is transferred to the underlaying passivation
`tially reduce pad lifetime, such that the overall process
`layer. Such etch processes include sputter etches and
`is more expensive due to the frequency of pad replace-
`reactive ion etches (RIE) in CF4-02 plasmas. For exam(cid:173)
`ment.
`ple, see U.S. Pat. No. 4,710,264 (issued 12/1/87 to 35
`Another difficulty is the lack of removal rate unifor(cid:173)
`Waschler et al and assigned to Telefonken GmbH). This
`mity across a given wafer. Using low slurry content
`alternative has not been widely accepted in the art be(cid:173)
`processes, the inventors tried to optimize uniformity by
`cause it is very difficult to accurately determine etch
`changing the slurry content as well as varying the hard(cid:173)
`endpoint.
`ness of the pad. None of these changes appreciably
`Another alternative presently under consideration is 40
`enhanced uniformity.
`the so-called "chem-mech polish" (CMP) process. In
`Yet another difficulty is the occurrence of "bumps."
`this process, passivated substrates are rotated against a
`Bumps are areas along the substrate having locally in(cid:173)
`polishing pad in the presence of an abrasive slurry.
`complete polishing. Typically they occur over areas
`Typically the slurry is pH-controlled such that the etch
`that cover steep topologies. For example, when polish(cid:173)
`rate of the passivation layer can be controlled. In U.S. 45
`ing an oxide passivation layer on top of a gate electrode,
`Patent Application Ser. No. 791,860, entitled "Chem(cid:173)
`if the electrode provides a steep "step" (i.e., if it has a
`Mech Polishing Method for Producing Co-Planar
`. height more than approximately 0.5 microns), bumps
`Metal/Insulator Films On a Substrate," filed Oct. 28,
`will tend to form on the portion of the oxide above the
`1985, by Beyer et al and assigned to the assignee of the
`edges of the electrode. In low slurry content applica(cid:173)
`present invention, different slurry chemistries are used 50
`tions, bumps cannot be eliminated without adversely
`to optimize insulator-to-metal (or visa-versa) etch rate
`affecting some other parameter (e.g., rate uniformity,
`ratios to achieve a planar surface. For example, using an
`pad life) that needs to be optimized.
`abrasive pad at a pressure of 2-8 PSI, and a slurry of
`Accordingly, there is a need in the art for a planariza(cid:173)
`0.06 micron alumina particles in deionized water, a 1:1
`tion process in which both pad lifetime and polish rate
`etch rate ratio of metal:insulator was achieved. The 55
`uniformity can be maximized while simultaneously min(cid:173)
`metal etch rate increased (and the oxide etch rate de(cid:173)
`imizing the occurrence of bumps.
`creased) as different acids are used to lower the pH to
`2.2. Alternatively, by increasing the pH to 11-11.5, the
`insulator removal rate increased relative to metal when
`using silica particulates at a concentration of 1-10 60
`weight. In U.S. Patent Application Ser. No. 085,836
`entitled "Via Filling and Planarizing Technique," filed
`Aug. 17, 1987, by Cote et al and assigned to the assignee
`of the present invention, an alumina/deionized water/(cid:173)
`hydrogen peroxide slurry was used utilizing a pressure 65
`of 10-12 PSI to provide a planarized tuggsten-BPSG
`surface, such that filled vias and a planarized passivation
`layer were simultaneously formed. See also U.S. Pat.
`
`SUMMARY OF THE INVENTION
`It is thus an object of the invention to provide a
`chem-mech planarization process that maximizes both
`pad lifetime and planarization uniformity.
`It is another object of the invention to optimize the
`above parameters while simultaneously minimizing the
`occurrence of bumps.
`It is yet another object of the invention to provide a
`chem-mech polishing process wherein the need to selec(cid:173)
`tively introduce different slurries is eliminated.
`
`003
`
`

`
`4,910,155
`
`3
`The above and other objects have been met by ar(cid:173)
`ranging a retaining wall about the polishing table, and
`introducing a pool of slurry that completely immerses
`the polish pad. Moreover, the slurry temperature is
`raised above room temperature.
`By utilizing a polishing process under the above con(cid:173)
`ditions, polish uniformity is in the range of 97%. At the
`same time, pad lifetime is appreciably extended (up to
`lOX) because a less vigorous break-in procedure may
`now be used. Finally, these enhancements do not come
`at the expense of increased occurrence of bumps; rather,
`bumps are eliminated.
`
`4
`an exposed coarse film thereon for a relatively short
`amount of time (e.g. five minutes). The amount of wa(cid:173)
`fers is a function of polish pad hardness (the harder the
`pad, the less break-in is needed). For a very hard polish
`5 pad (e.g., the IC-40 pad sold by Rode! Corp. of Scotts(cid:173)
`dale, AZ), no break-in is necessary in this process.
`In carrying out experiments utilizing the polish appa(cid:173)
`ratus discussed above, the inventors found that the tem(cid:173)
`perature of the slurry plays a significant role in polish
`10 uniformity. Specifically, by raising the slurry tempera(cid:173)
`ture from room temperature to 85-95" F., the unifor(cid:173)
`mity of the planarization etch was greatly improved, by
`up to a factor of two in some experiments. These find-
`ings were not anticipated, particularly in polishing lay(cid:173)
`ers such as oxides where the process is predominantly
`mechanical in nature. Moreover, after this phenomena
`was uncovered, the inventors expected that it would
`hold (and even increase) as a function of increased tem-
`perature. However, the inventors found that at temper(cid:173)
`atures above approximately 95-100" F., uniformity sub-
`stantially degrades. The inventors postulate that at these
`higher temperatures, non-uniformity increases because
`it is very difficult to maintain constant slurry concentra-
`25 tion due to evaporation. In other words, above approxi(cid:173)
`mately 100" F., increases in polish uniformity are ne(cid:173)
`gated by slurry non-uniformity.
`The inventors have found that the percentage of
`particulates in the slurry, plays a role in the overall
`process. Specifically, the inventors found that when
`utilizing a pool of silica slurry, the polishing rate of the
`substrates increases (and the occurrence of bumps de(cid:173)
`creases) linearly with increasing solids percentage up to
`10%. Above 10%, both polish rate and polish rate uni-
`35 formity stay essentially constant, and bumps are at a
`minimum. Experiments indicate that above approxi(cid:173)
`mately 15 weight percent solids, polish rate uniformity
`degrades. When polishing in the presence of a small
`amount of slurry, both polish rate and polish rate non(cid:173)
`uniformity increase with increasing solids percent. In
`other words, there is no appreciable operating "win-
`dow" within which both polish rate and polish rate
`uniformity can be maximized by percent solids.
`The size of particulates also plays a role in the overall
`process. The inventors thought bumps were caused by
`small non-uniformities in the particulate concentration
`within the slurry. They tried to eliminate bumps by
`using a slurry having small (0.006 micron average size)
`particulates, on the assumption that smaller particulates
`would enhance the effective particulate concentration.
`Bumps continue to occur. When the size of the particu-
`lates was increased to 0.02 microns, bumps were elimi(cid:173)
`nated. These results were achieved at removal rates
`between approximately 500 and 1500 angstroms per
`minute. Above approximately 2000 angstroms per min(cid:173)
`ute, bumps could not be eliminated. Note that this re-
`moval rate limit is for blanket layers; in practice, when
`planarizing passivation layers overlaying steep topogra(cid:173)
`phies, localized removal rates of up to 6000 angstroms
`60 per minute have been achieved without bumps.
`Moreover, by utilizing a pool of slurry, large particu(cid:173)
`lates can be used for all polish applications, including
`those in which slurries having fine particulates are ordi(cid:173)
`narily used. In the invention, the slurry has been diluted
`in water to 12% (by weight) Si02 particulates (average
`diameter of 0.02 microns) suspended in water. The
`slurry is sold under the trade name "Cab-0-Sperse SCI"
`by Cabot Corp. Normally, a slurry having much smaller
`
`BRIEF DESCRIPTION OF THE DRAWING
`The above and other aspects of the invention will be 15
`described in more detail below. In the description to
`follow, reference will be made to the accompanying
`Drawing, in which:
`FIG. 1 is a top view of the polishing apparatus of the
`"w
`~~~~~
`FIG. 2 is a cross-sectional view of the polishing appa(cid:173)
`ratus of the invention.
`
`DESCRIPTION OF THE BEST MODE FOR
`CARRYING
`OUT THE INVENTION
`With reference to FIGS. 1 and 2, the invention is
`carried out on a rotating polish wheel10 having a circu-
`lar polishing pad 12 mounted thereon. The polishing
`wheel 10 rotates in a direction indicated by arrow 14. 30
`There are a number of commercial polish wheels upon
`which the invention can be carried out. The inventors
`have practiced the invention on a polish tool Model No.
`6CU sold by the Strasbaugh Co. of Huntington Beach,
`CA.
`Disposed about the periphery of polish wheel 10 is a
`retaining wall (or dam) 16. The purpose of the dam 16
`is to increase the amount of slurry 30 provided to the
`polish pad 12, to the point where a slurry "pool" 30 is
`formed which is sufficient to completely cover the pad 40
`12 even when it is spinning during the polishing process.
`See Namba et al, "Ultrafine Finishing of Ceramics and
`Metals by Float Polishing." Laser Induced Damage in
`Optical Materials" Conference Proceedings 1980, pgs.
`171-179. See also U.S. Pat. No. 2,922,264. In the present 45
`invention, the dam is two inches high, such that a slurry
`pool approximately i inch deep is formed covering the
`polish pad 12.
`The wafers 28 to be planarized are held against the
`spinning polish wheel 10 by a quill assembly 20. The 50
`quill assembly includes a moveable support arm 22 for
`bringing the wafer 28 into contact with the polish pad
`12, and a wafer support 24 that spins in a direction
`indicated by arrow 26. Note that the wafer support 26 is
`rotated by a belt assembly (not shown) disposed within 55
`support arm 22. The support 24 has an elastomeric pad
`(not shown) disposed within it for receiving the wafer
`28. Thus, the wafers 28 are polished by the action of the
`spinning support 24, the spinning pad 12, and the slurry
`pool 30 disposed therebetween.
`When utilizing large slurry amounts, the inventors
`have found that both greater uniformity and prolonged
`pad life results. Specifically, under these conditions
`polish uniformity across the surface of a wafer can be as
`high as 97%. At the same time, polish pad lifetime is 65
`increased because a less vigorous break-in procedure
`can be used. Specifically, break-in can now be per(cid:173)
`formed by polishing a number of blank wafers having
`
`004
`
`

`
`4,910,155
`
`5
`particulates would be used in situations in which only a
`small amount of material is to be polished away, and/or
`the underlaying surface is particularly sensitive to
`scratching (e.g., in polishing a thin silicon dioxide layer
`atop a polish-stop layer formed on a silicon substrate, 5
`we wish to avoid dislocations in the silicon crystallogra(cid:173)
`phy that can result from scratching the silicon surface).
`The inventors found that by utilizing a pool of slurry at
`an elevated temperature, the mechanism by which par(cid:173)
`ticulate size contributes to scratching is eliminated. 10
`Thus, under these conditions scratching becomes a sole
`function of pad hardness (the harder the pad, the more
`scratches). In low slurry applications, softer pads could
`not be used because bumps would occur; this problem
`could only be alleviated by utilizing the destructive pad 15
`break-in/conditioning procedures previously discussed.
`Here, one can use a softer pad without producing
`bumps and without utilizing such pad break-in/condi(cid:173)
`tioning procedures. Thus, the same coarse slurry can
`now be used in conventional fine slurry applications, 20
`reducing expense by eliminating the need to change
`slurries as a function of coarse/fine application.
`Further, in utilizing a pool of slurry, the spin speed of
`both the table 10 and the quill 20 is reduced from 120
`RPM to 15-30 RPM. Under these conditions, endpoint 25
`detection is facilitated. For example, when polishing
`oxide on a silicon wafer, it has been observed that sili(cid:173)
`con is much less susceptible to polishing. This means
`that when the silicon surface rubs against the polish
`wheel, it produces a far greater amount of drag than 30
`does the oxide. The inventors have taken advantage of
`this phenomenon to provide an accurate endpoint de(cid:173)
`tection method. When multiple wafers are being pol(cid:173)
`ished, a monitor (or dummy) wafer is included. The
`dummy wafer is a silicon substrate having the same 35
`amount of oxide on it as the amount of oxide on the
`product wafers to be removed by polishing. Once the
`oxide is removed form the dummy wafer, the exposed
`silicon surface provides a large amount of drag. This
`maximum drag can be detected with a quill motor cur- 40
`rent detector. The motor controller is set to allow the
`quill to slow down at maximum drag. The controller
`senses that the motor rotation speed is too low and the
`motor current increases sharply, producing a current
`"spike." Thus, process endpoint is signaled by current 45
`spikes in the motor that turns the quill.
`The above technique is applied to lower quill spin
`speeds, because at higher speeds the increased drag is
`less pronounced due to the increased angular momen(cid:173)
`tum of the wafer.
`The invention will now be discussed with reference
`to Example 1 below:
`
`6
`Thus, in the invention, a pool of slurry is used in
`which the temperature is raised above room tempera(cid:173)
`ture, such that both polish rate uniformity and pad life(cid:173)
`time are maximized without promoting bumps. These
`advantages of the invention can be realized whenever
`insulators such as silicon oxide or silicon nitride are to
`be polished. Moreover, the advantages of the invention
`are not limited to the best mode embodiment described
`above; for example, other particulates having hard(cid:173)
`nesses commensurate with the hardness of the insulator
`to be polished can be used.
`We claim:
`1. In a process of chem-mech polishing an insulator
`layer arranged on a semiconductor wafer, wherein the
`wafer is brought into contact with a rotating polish
`wheel having a polishing pad disposed thereon, the
`improvement comprising:
`providing sufficient slurry to form a pool defined by
`a dam disposed about the outer periphery of the
`polish wheel, wherein said polishing pad is im(cid:173)
`mersed in said pool during polishing, and wherein
`said slurry comprises a liquid suspension of solid
`particulates having a hardness commensurate to
`the hardness of the insulator layer; and
`elevating the temperature of said slurry to at least
`approximately .85° F ..
`2. The process as recited in claim 1, wherein said
`slurry is at a temperature between approximately 85°
`F.-95° F.
`3. The process as recited in claim 1, wherein said solid
`particulates have an average size of at least 0.02 mi(cid:173)
`crons.
`4. The process is recited in claim 1, wherein said solid
`particulates constitute approximately 10%-15% by
`weight of said slurry.
`5. The process as recited in claim 4, wherein said
`particulates are comprised of Si02.
`6. The process as recited in claim 1, wherein said
`polish wheel rotates at a speed no greater than approxi(cid:173)
`mately 30 RPM.
`7. The process as recited in claim 6, wherein said
`polish wheel rotates at a speed between approximately
`15 RPM-20 RPM.
`8. The process as recited in claim 6, wherein a plural(cid:173)
`ity of semiconductor wafers are simultaneously pol(cid:173)
`ished by being brought into contact with the same pol(cid:173)
`ish wheel.
`9. The process as recited in claim 8, wherein at least
`50 one of said wafers is a dummy wafer comprising a sili(cid:173)
`con substrate with a discrete layer thereon having a
`thickness commensurate to the amount of material to be
`removed from the remaining wafers.
`10. The process as recited in claim 9, further compris(cid:173)
`ing:
`monitoring said dummy wafer during polishing to
`indicate when the polishing process is completed.
`11. In a process of chem-mech polishing an insulator
`layer arranged on a semiconductor wafer, wherein the
`60 wafer is brought into contact with a rotating polish
`wheel having a polishing pad disposed thereon, the
`improvement comprising:
`providing sufficient slurry to form a pool defined by
`a dam disposed about the outer periphery of the
`polish wheel, wherein said polishing pad is im(cid:173)
`mersed in said pool during polishing, and wherein
`said slurry comprises a suspension of silica particu(cid:173)
`lates having an average size greater than 0.006
`
`65
`
`EXAMPLE 1
`PuDJose: To planarize a step height of approximately 55
`soooA of undoped oxide passivating a processed silicon
`substrate.
`slurry: Cab-0-Sperse SCI, diluted in water to 12
`weight percent
`quill spin speed: 17 RPM
`quill pressure: 9 PSI
`polish pad: Radel Suba 500
`polish wheel spin speed: 17 RPM
`slurry temperature: 90° F.
`number of wafers: 9, plus endpoint detection wafer
`Results: After 7 minutes, oxide is completely plana-
`rized on the silicon surface, without bumps or scratch(cid:173)
`ing.
`
`005
`
`

`
`7
`microns, said silica particles comprising approxi(cid:173)
`mately 10%-15% by weight of said slurry; and
`elevating the temperature of said slurry to at least
`approximately 85' F.
`12. The process as recited in claim 11, wherein said 5
`silica particulates have an average size of approximately
`0.01 microns.
`13. The process as recited in claim 12, wherein said
`polish wheel rotates at a speed no greater than approxi-
`mately 30 RPM.
`14. The process as recited in claim 13, wherein said
`polish wheel rotates at a speed between approximately
`15 RPM-20 RPM.
`15. The process as recited in claim 13, wherein a 15
`plurality of semiconductor wafers are simultaneously
`polished by being brought into contact with the same
`polish wheel.
`16. The method as recited in claim 15, wherein at
`least one of said wafers is a dummy wafer comprising a 20
`silicon substrate with a discrete layer thereon having a
`thickness commensurate to the amount of material to be
`removed from the remaining wafers.
`17. The method as recited in claim 16, further com-
`prising:
`monitoring said dummy wafer during polishing to
`indicate when the polishing process is completed.
`18. In a process of chem-mech polishing a layer of
`silicon oxide disposed on a semiconductor substrate,
`wherein the substrate is supported by a quill in contact 30
`
`25
`
`8
`with a rotating polish wheel having a polishing pad
`disposed thereon, the improvement comprising:
`providing an amount of slurry sufficient to form a
`pool defined by a dam disposed about the polish
`wheel, wherein said polishing pad is immersed in
`said pool during polishing, and wherein said slurry
`comprises a suspension of approximately 10%-15
`% silica particulates by weight, said partic"ulates
`having an average diameter of at least approxi(cid:173)
`mately 0.02 microns; and
`elevating the temperature of said slurry to at least
`approximately 85' F.; and wherein
`said polish wheel rotates at a speed no greater than
`approximately 30 RPM.
`19. The process as recited in claim 18, wherein said
`slurry is at a temperature between approximately 85' F.
`-95' F. and said polish wheel rotates at a speed between
`approximately 15 RPM-20 RPM.
`20. The process as recited in claim 19, wherein:
`a plurality of semiconductor wafers are simulta(cid:173)
`neously polished by being brought into contact
`with the same polish wheel; and
`at least one of said wafers is a dummy wafer compris(cid:173)
`ing a silicon substrate with a discrete layer thereon
`having a thickness commensurate to the amount of
`material to be removed from the remaining wafers;
`and further comprising:
`monitoring said dummy wafer during polishing to
`indicate when the polishing process is completed.
`* * * * *
`
`4,910,155
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`006