Paper No. ________
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`Sony Corporation
`
`Petitioner
`
`v.
`
`RAYTHEON COMPANY
`
`(record) Patent Owner
`
`Patent No. 5,591,678
`Issue Date: January 7, 1997
`
`Title: Process of Manufacturing a Microelectric Device using a Removable
`Support Substrate and Etch-Stop
`
`DECLARATION OF DR. RICHARD A. BLANCHARD
`
`i
`
`SONY 1002
`
`

`
`TABLE OF CONTENTS
`TABLE OF CONTENTS
`
`I.
`I.
`
`Engagement and compensation.......................................................................... 1
`Engagement and compensation ........................................................................ ..1
`
`II. Summary of opinions ......................................................................................... 1
`II.
`Summary of opinions ....................................................................................... ..1
`
`III. Qualifications ..................................................................................................... 2
`III. Qualifications ................................................................................................... ..2
`
`IV. My understanding of the relevant law ............................................................... 5
`IV. My understanding of the relevant law ............................................................. ..5
`
`A. Claim construction ......................................................................................... 5
`A. Claim construction ....................................................................................... ..5
`
`B. Anticipation .................................................................................................... 6
`B. Anticipation .................................................................................................. ..6
`
`C. Obviousness ................................................................................................... 6
`C. Obviousness ................................................................................................. ..6
`
`V. Technical introduction .....................................................................................10
`V. Technical introduction ................................................................................... .. 10
`
`A. Background ..................................................................................................10
`A. Background ................................................................................................ .. 10
`
`B.
`B.
`
`’678 Patent Disclosure .................................................................................11
`’678 Patent Disclosure ............................................................................... ..11
`
`VI. Level of ordinary skill in the art ......................................................................20
`VI. Level of ordinary skill in the art .................................................................... ..20
`
`VII. Predictability of the art .....................................................................................22
`VII. Predictability of the art................................................................................... ..22
`
`VIII. Relevant time frame for determining obviousness ..........................................22
`VIII.Relevant time frame for determining obviousness ........................................ ..22
`
`IX. Overview of the claims ....................................................................................23
`IX. Overview of the claims .................................................................................. ..23
`
`X. Construction of the claims ...............................................................................23
`X. Construction of the claims ............................................................................. ..23
`
`A. Claims 1, 3, 6-7, 11, 13 and 15 —"Microelectronic circuit element" .........23
`A. Claims 1, 3, 6-7, 11, 13 and 15 —"Microelectronic circuit element" ....... ..23
`
`B. Claims 1, 11 and 13—“Etching” and “etch-stop layer” ..............................24
`B. Claims 1, 11 and 13—“Etching” and “etch-stop layer” ............................ ..24
`
`C. Claims 1, 3-5, 11-13, 15-18 —“Wafer”.......................................................25
`C. Claims 1, 3-5, 11-13, 15-18 —“Wafer” ..................................................... ..25
`
`XI. Claims 1, 6-7 and 10-11 are unpatentable as anticipated by Bertin. ...............25
`XI. Claims 1, 6-7 and 10-11 are unpatentable as anticipated by Bertin. ............. ..25
`
`A. Summary of opinions relating to Bertin ......................................................25
`A.
`Summary of opinions relating to Bertin .................................................... ..25
`
`B. Bertin is prior art ..........................................................................................25
`B. Bertin is prior art ........................................................................................ ..25
`
`C. Summary of Bertin .......................................................................................25
`C.
`Summary of Bertin ..................................................................................... ..25
`
`D. Comparison of Bertin’s original patent application to the issued patent .....34
`D. Comparison of Bertin’s original patent application to the issued patent.....34
`
`E. Element-by-element analysis of claims 1, 6-7 and 10-11 in combination
`E. Element-by-element analysis of claims 1, 6-7 and 10-11 in combination
`with Bertin ............................................................................................................34
`with Bertin .......................................................................................................... ..34
`
`
`
`ii
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`

`
`1.
`
`Independent claim 1 .................................................................................35
`
`2. Claim 6 .....................................................................................................41
`
`3. Claim 7 .....................................................................................................43
`
`4. Claim 10 ...................................................................................................45
`
`5.
`
`Independent Claim 11 ..............................................................................46
`
`XII. Claims 5 and 12-13 are obvious as in Ground 1 in combination with
`Morimoto..................................................................................................................48
`
`A. Morimoto is prior art ....................................................................................48
`
`B. Summary of Morimoto ................................................................................48
`
`C. Element-by-element analysis of claims 5 and 12-13 over Bertin in
`combination with Morimoto ................................................................................56
`
`1. Dependent claims 5 and 12 ......................................................................56
`
`2.
`
`Independent claim 13 ...............................................................................59
`
`XIII. Claims 1-2, 4-5, 10, 13-14, and 16-17 are unpatentable as obvious over
`Morimoto in combination with any of the CMP / Etching references ....................62
`
`A. Summary of opinions relating to Morimoto and the CMP / Etching
`references .............................................................................................................62
`
`B. The CMP / Etching references are prior art .................................................62
`
`C. Summary of each of the CMP / Etching references ....................................63
`
`1. Hamaguchi et al. “Novel SOI Technology Using Preferential Polishing”,
`NEC Research Notes 1480 (70), 1987. (Ex. 1004). .......................................63
`
`2. U.S. Pat. No. 5,244,534 (“Yu”). (Ex. 1007). ..........................................64
`
`3. U.S. Pat. No. 4,910,155 (“Cote”). (Ex. 1008). .......................................65
`
`4. U.S. Pat. No. 5,064,683 (“Poon”). (Ex. 1009). .......................................65
`
`5. U.S. Pat. No. 5,069,002 (“Sandhu”). (Ex. 1010). ...................................66
`
`6. U.S. Pat. No. 5,189,500 (“Kusunoki”). (Ex. 1011). ...............................67
`
`7. U.S. Pat. No. 5,066,993 (“Miura”). (Ex. 1012). .....................................70
`
`D. There was motivation to combine Morimoto and any of the CMP / Etching
`references. ............................................................................................................71
`
`
`
`iii
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`

`
`E. Element-by-element analysis of claims 1-2, 4-5, 10, 13-14, and 16-17 in
`combination with Morimoto and any of the CMP / Etching references ..............72
`
`1.
`
`Independent claim 1 .................................................................................72
`
`2. Claim 2 .....................................................................................................96
`
`3. Claim 4 .....................................................................................................99
`
`4. Claim 5 ...................................................................................................100
`
`5. Claim 10 .................................................................................................102
`
`6.
`
`Independent claim 13 .............................................................................104
`
`7. Claim 14 .................................................................................................106
`
`8. Claim 16 .................................................................................................106
`
`9. Claim 17 .................................................................................................106
`
`XIV. Claims 8 and 18 are invalid as obvious over Morimoto and any of the CMP
`/ Etching references in combination with Oldham. ...............................................113
`
`A. Summary of opinions relating to Morimoto and any of the CMP / Etching
`references in combination with Oldham. ...........................................................113
`
`B. Oldham is prior art .....................................................................................113
`
`C. Summary of Oldham ..................................................................................113
`
`D. There was motivation to combine Morimoto and any of the CMP / Etching
`references and Oldham .......................................................................................114
`
`E. Element-by-element analysis of Morimoto and any of the CMP / Etching
`references in combination with Oldham ............................................................115
`
`XV. Claims 3 and 15 are invalid as obvious over as Morimoto and any of the CMP
`/ Etching references in combination with Bertin ...................................................117
`
`A. Summary of opinions relating to Morimoto and any of the CMP / Etching
`references in combination with Bertin ...............................................................117
`
`B. There was motivation to combine Morimoto and any of the CMP / Etching
`references with Bertin ........................................................................................118
`
`C. Element-by-element analysis of Morimoto and any of the CMP / Etching
`references in combination with Bertin. ..............................................................119
`
`XVI. Claim 9 is invalid as obvious over Bertin in combination with Ying .......121
`
`A. Summary of opinions relating to Bertin in combination with Ying ..........121
`
`
`
`iv
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`

`
`B. Ying is prior art ..........................................................................................121
`Ying is prior art ........................................................................................ ..121
`
`C. Summary of Ying .......................................................................................121
`Summary of Ying ..................................................................................... ..121
`
`D. There was motivation to combine Bertin with Ying .................................121
`There was motivation to combine Bertin with Ying ............................... .. 121
`
`FHUOPU
`
`E. Element-by-element analysis of Bertin with Ying ....................................122
`E1ement—by—e1ement analysis of Bertin with Ying .................................. .. 122
`
`XVII.
`XVII.
`
`Oath ........................................................................................................126
`Oath ...................................................................................................... .. 126
`
`
`
`v
`
`

`
`1.
`
`I, Richard A. Blanchard hereby declare as follows:
`
`I. Engagement and compensation
`
`2.
`
`I have been retained by Sony Corporation to serve as an expert in the
`
`inter partes review proceeding described above. I have been asked to provide my
`
`technical review, analysis, insights, and opinions regarding the references that form
`
`the basis for the grounds of unpatentability set forth in The Petition for Inter Partes
`
`review of US 5,591,678 (the ’678 Patent). For this service, my billing rate is an
`
`hourly consulting fee of $375/hour, and I am reimbursed for actual expenses. My
`
`compensation in no way depends on the outcome of this matter.
`
`II. Summary of opinions
`
`3.
`
`It is my opinion that claims 1, 6-7 and 10-11 are of U.S. Pat. No.
`
`5,591,678 (“the ’678 patent”) are unpatentable as anticipated by Bertin (Ex. 1017).
`
`4.
`
`It is further my opinion that claims 5 and 12-13 are obvious based on
`
`Bertin in combination with Morimoto (Ex. 1005, translation at Ex. 1006).
`
`5.
`
`It is also my opinion that claims 1-2, 4-7, 10-14 and 16-17 obvious
`
`based on Morimoto in combination with any of the CMP / Etching references
`
`(1007-1012).
`
`6.
`
`It is further my opinion that claims 8 and 18 are invalid as obvious
`
`based on Morimoto in combination with any of the CMP / Etching references in
`
`combination with Oldham.
`
`
`
`1
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`

`
`7.
`
`It is further my opinion that claims 3 and 15 are invalid as obvious
`
`based on Morimoto in combination with any of the CMP / Etching references in
`
`combination with Bertin.
`
`8.
`
`It is further my opinion that claim 9 is invalid as obvious based on
`
`Morimoto in combination with any of the CMP / Etching references in
`
`combination with Ying.
`
`III. Qualifications
`
`9.
`
`I am a consultant for InSciTech, Inc., a company specializing in
`
`accident investigation and expert witness litigation support. I also provide
`
`technical consulting services to the semiconductor and electronics industry through
`
`Blanchard Associates.
`
`10. My academic credentials include both a Bachelor of Science Degree
`
`in Electrical Engineering (BSEE) in 1968 and a Master of Science Degree in
`
`Electrical Engineering (MSEE) from the Massachusetts Institute of Technology in
`
`1970. I subsequently obtained a Ph.D. in Electrical Engineering from Stanford
`
`University in 1982.
`
`11. My professional background and technical qualifications are stated
`
`above and are also reflected in my curriculum vitae, which is attached as Appendix
`
`1. These qualifications are summarized below.
`
`
`
`2
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`

`
`12.
`
`I have worked or consulted for more than 40 years as an
`
`Electrical Engineer. My primary focus has been the development, manufacture,
`
`operation and use of discrete devices and integrated circuits, the assembly of these
`
`discrete devices and integrated circuits, products that use them, and their failures.
`
`My employment history following my graduation from MIT began at Fairchild
`
`Semiconductor in 1970. At Fairchild, my responsibilities included circuit and
`
`device design, process development and product engineering in the Linear
`
`Integrated Circuits Department.
`
`13.
`
`In 1974, I joined Foothill College as an Associate Professor in the
`
`Engineering & Technology Division. My responsibilities included developing a
`
`program in Semiconductor Technology as well as teaching other courses in the
`
`division. While at Foothill College, I co-founded two companies, Cognition and
`
`Supertex. Cognition developed and manufactured semiconductor pressure sensors
`
`using a wafer bonding technique, while Supertex designed and manufactured
`
`discrete semiconductor devices and integrated circuits. In 1978, I joined Supertex
`
`as Vice President, where I developed discrete DMOS (double-diffused metal oxide
`
`semiconductor) transistors as well as integrated circuits that contained DMOS
`
`transistors. At Supertex, I also supervised the in-house assembly area, which
`
`included responsibility for the packaging of discrete DMOS transistors as well as
`
`integrated circuits that contained DMOS transistors.
`
`
`
`3
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`

`
`14.
`
`I left Supertex to join Siliconix in 1982, where I soon became Vice
`
`President of Engineering, with the responsibility for directing all of the company’s
`
`product design and development. At Siliconix, I directed and contributed to the
`
`development of both discrete transistors and integrated circuits, including aspects
`
`of their assembly.
`
`15.
`
`In 1987, I joined IXYS Corporation as a Senior Vice President with
`
`the responsibility for organizing an integrated circuits department. At IXYS, I
`
`developed integrated circuits that contained DMOS transistors or that interfaced to
`
`DMOS devices. My responsibilities included the design, the fabrication, the
`
`assembly, and the testing of these integrated circuits.
`
`16. These duties continued until 1991, when I left IXYS to set up
`
`Blanchard Associates, a consulting firm specializing in semiconductor technology,
`
`including intellectual property. Soon, thereafter, I was invited to join Failure
`
`Analysis Associates, which I did in late 1991. At Failure Analysis Associates, I
`
`investigated failures in electrical and electronic systems in addition to performing
`
`design and development consulting.
`
`17.
`
`I left Failure Analysis in 1998 to join IP Managers, which later
`
`merged with the Silicon Valley Expert Witness group, which is now known as
`
`Thomson Reuters Expert Witness Services (“Thomson Reuters”). At Thomson
`
`Reuters, I worked with companies on patent and trade secret matters. I also
`
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`4
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`

`
`consulted for a number of semiconductor companies, working with them to
`
`develop products and intellectual property, or assisting them in other technical
`
`areas through Blanchard Associates.
`
`18.
`
`In 2014, I became a Staff Consultant at InSciTech, Inc., where I
`
`continue to consult with clients on patent and trade secret matters. I also work
`
`with semiconductor and electronics companies on other technical matters.
`
`19. As shown in my resume (see Appendix 1), I am a named inventor on
`
`more than 200 issued or pending U.S. patents, have co-authored a number of
`
`articles, and have co-authored or contributed to a number of books.
`
`20.
`
`I am a member of a number of professional societies, including the
`
`institute of Electrical and Electronic Engineers, the International Microelectronic
`
`Device Failure Analysis Society, and the Electrostatic Discharge Society.
`
`IV. My understanding of the relevant law
`
`A. Claim construction
`
`21.
`
`I understand that, when a patent is expired, a claim term in an inter
`
`partes review is to be interpreted in the following manner: First, the language of
`
`the claims themselves is of primary importance in the effort to determine precisely
`
`what it is that is patented. The terms used in a claim are generally given the
`
`ordinary and customary meaning that the terms would have to a person of ordinary
`
`skill in the art in question at the time of the alleged invention, unless the term is
`
`
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`5
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`

`
`expressly defined in the patent. The person of ordinary skill in the art reads the
`
`claim in the context of the entire patent, including the specification. Next to the
`
`language of the claims, the specification is the single best source for interpreting
`
`the claim terms. The claims may also be interpreted using the record of
`
`correspondence between the patent applicant and the Patent Office, and also with
`
`reference to other sources of evidence that can help to define the meaning of terms
`
`to a person of ordinary skill in the relevant time frame. I define the relevant time
`
`frame in ¶55, below.
`
`B. Anticipation
`
`22.
`
`I understand that a claim in an issued patent can be invalid if it is
`
`anticipated. In this case, “anticipation” means that there is a single prior art
`
`reference that discloses every element of the claim, arranged in the way required
`
`by the claim.
`
`23.
`
`I understand that an anticipating prior art reference must disclose each
`
`of the claim elements expressly or inherently. I understand that “inherent”
`
`disclosure means that the claim element, although not expressly described by the
`
`prior art reference, must necessarily be present based on the disclosure. I
`
`understand that a mere probability that the element is present is not sufficient to
`
`qualify as “inherent disclosure”.
`
`C. Obviousness
`
`
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`6
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`

`
`24.
`
`I understand that a claim in an issued patent can be invalid if it is
`
`obvious. Unlike anticipation, obviousness does not require that every element of
`
`the claim be in a single prior art reference. Instead, it is possible for claim
`
`elements to be described in different prior art references, so long as there is
`
`motivation or sufficient reasoning to combine the references.
`
`25.
`
`I understand that a claim is invalid for obviousness if the differences
`
`between the claimed subject matter and the prior art are such that the subject
`
`matter as a whole would have been obvious at the time the alleged invention was
`
`made to a person having ordinary skill in the art to which said subject matter
`
`pertains.
`
`26.
`
`I understand, therefore, that when evaluating obviousness, one must
`
`consider obviousness of the claim “as a whole”. This consideration must be from
`
`the perspective of the person of ordinary skill in the relevant art, and that such
`
`perspective must be considered as of the “time the invention was made”.
`
`27. The level of ordinary skill in the art is discussed in ¶¶48-53, below.
`
`28. The relevant time frame for obviousness, the “time the invention was
`
`made”, is discussed in ¶55, below.
`
`29.
`
`I understand that in considering the obviousness of a claim, one must
`
`consider four things. These include the scope and content of the prior art, the level
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`
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`7
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`

`
`of ordinary skill in the art at the relevant time, the differences between the prior art
`
`and the claim, and any “secondary considerations”.
`
`30.
`
`I understand that “secondary considerations” include real-world
`
`evidence that can tend to make a conclusion of obviousness either more probable
`
`or less probable. For example, the commercial success of a product embodying a
`
`claim of the patent could provide evidence tending to show that the claimed
`
`invention is not obvious. In order to understand the strength of the evidence, one
`
`would want to know whether the commercial success is traceable to a certain
`
`aspect of the claim not disclosed in a single prior art reference (i.e., whether there
`
`is a causal “nexus” to the claim language). One would also want to know how the
`
`market reacted to disclosure of the invention, and whether commercial success
`
`might be traceable to things other than innovation, for example the market power
`
`of the seller, an advertising campaign, or the existence of a complex system having
`
`many features beyond the claims that might be desirable to a consumer. One
`
`would also want to know how the product compared to similar products not
`
`embodying the claim. I understand that commercial success evidence should be
`
`reasonably commensurate with the scope of the claim, but that it is not necessary
`
`for a commercial product to embody the full scope of the claim.
`
`31. Other kinds of secondary considerations are possible. For example,
`
`evidence that the relevant field had a long-established, unsolved problem or need
`
`
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`8
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`

`
`that was later provided by the claimed invention could be indicative of non-
`
`obviousness. Evidence that others had tried, but failed to make an aspect of the
`
`claim might indicate that the art lacked the requisite skill to do so. Evidence of
`
`copying of the patent owner’s products before the patent was published might also
`
`indicate that its approach to solving a particular problem was not obvious.
`
`Evidence that the art recognized the value of products embodying a claim, for
`
`example, by praising the named inventors’ work, might tend to show that the claim
`
`was non-obvious.
`
`32.
`
`I further understand that prior art references can be combined where
`
`there is an express or implied rationale to do so. Such a rationale might include an
`
`expected advantage to be obtained, or might be implied under the circumstances.
`
`For example, a claim is likely obvious if design needs or market pressures existing
`
`in the prior art make it natural for one or more known components to be combined,
`
`where each component continues to function in the expected manner when
`
`combined (i.e., when there are no unpredictable results). A claim is also likely
`
`invalid where it is the combination of a known base system with a known
`
`technique that can be applied to the base system without an unpredictable result.
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`In these cases, the combination must be within the capabilities of a person of
`
`ordinary skill in the art.
`
`
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`9
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`

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`33.
`
`I understand that when considering obviousness, one must not refer to
`
`teachings in the specification of the patent itself. One can, however, refer to
`
`portions of the specification admitted to be prior art, including the
`
`“BACKGROUND” section. Furthermore, a lack of discussion in the patent
`
`specification concerning how to implement a disclosed technique can support an
`
`inference that the ability to implement the technique was within the ordinary skill
`
`in the prior art.
`
`V. Technical introduction
`
`A. Background
`
`34. The following is a brief technical background covering some concepts
`
`relevant to the ’678 patent specification and its claims.
`
`35. The ’678 patent has the title “PROCESS OF MANUFACTURING A
`
`MICROELECTRIC DEVICE USING A REMOVABLE SUPPORT SUBSTRATE
`
`AND ETCH-STOP”. This title provides only a modest amount of information
`
`about the problem that the ’678 patent addresses. However, the section of the ’678
`
`patent title “Background of the Invention” contains the following information
`
`concerning the problems the inventors address.
`
`“The present inventors have determined that for some applications it
`
`would be desirable to stack and interconnect a number of such two-
`
`dimensional microelectronic devices fabricated on a substrate wafer,
`
`one of top of the other to form a three-dimensional device. The stack
`
`
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`10
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`
`might also include other circuit elements such as interconnect layers
`
`and thin film sensors as well.” (Ex. 1001, 1:44-50).
`
`Stacking two or more semiconductor die has several possible advantages.
`
`Typically, a circuit board is a rectangle of material, and may have to fit in a
`
`compact computer or other device. Because of the size limitations of the housing
`
`of the computer or other device, circuit boards often have limited area. Stacked die
`
`will occupy less area on a substrate such as a printed circuit board, so allow
`
`physically smaller electronic systems in applications that use die mounted on a
`
`substrate. They also allow multiple die to be incorporated into a single package
`
`that occupies approximately the same area on the circuit board as a single die,
`
`resulting in both less surface area on a substrate and a smaller package volume,
`
`which can further reduce the system size in an application that uses packaged ICs
`
`mounted to the substrate. It is also possible to join ICs made using different
`
`technologies, producing a circuit with the combined features of each IC. There
`
`was an active industry in designing stack semiconductor die arrangements during
`
`the relevant time frame. (e.g. Ex. 1006, p. 1; Ex. 1017, 1:29-52).
`
`B. ’678 Patent Disclosure
`
`36. The specification of the ’678 patent provides a description of the
`
`fabrication method (Ex. 1001 2:15-28) as well as showing a diagrammatic process
`
`
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`11
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`

`
`flow diagram of the steps used in the process in Figure 1 of the ’678 patent as
`
`shown below.
`
`“In accordance with the invention, a method of fabricating a
`
`microelectronic device comprises the steps of furnishing a first
`
`substrate having an etchable layer, an etch-stop layer overlying the
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`etchable layer, and a wafer overlying the etch-stop layer, and forming
`
`a microelectronic circuit element in the wafer of the first substrate.
`
`The method further includes attaching the wafer portion of the first
`
`substrate to a second substrate, and etching away the etchable layer of
`
`the first substrate down to the etch-stop layer. The second substrate
`
`may include a microelectronic device, and the procedure may include
`
`the further step of interconnecting the microelectronic device on the
`
`first substrate with the microelectronic device on the second
`
`substrate.” (Ex. 1001, 2:15-28).
`
`
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`12
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`

`
`Figure 1 of the ’678 patent. (Ex. 1001, Fig. 1).1
`
`Figure 1 of the ’678 patent shows the technique described in this patent. The
`
`
`
`
`1 Note: The drawing labeled 26 in Figure 1 appears to contain an error. The
`
`element labeled 56 in drawing 24 and 28 is missing in drawing 26.
`
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`13
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`specific steps shown in Figure 1 are discussed in ¶¶37-42 below.
`
`37. Stacks are made using semiconductor-based building blocks referred
`
`to as “substrates”. The first step, 20, (labeled
`
`“Furnish First Substrate” in Fig. 1) is furnishing
`
`a substrate, 40, shown in the portion of Fig. 1 of
`
`the ’678 patent at right, with highlighting added.
`
`’678 Pat., FIG. 1
`
`The substrate has three layers:
`
`42 – An etchable layer (colored blue);
`
`44 – An etch stop layer (in this instance, a layer of silicon dioxide)
`
`(colored green); and
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`46 – A layer of single crystal silicon (a “wafer”) (colored yellow),
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`containing integrated circuit elements, such as transistors.
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`The three-layer substrate, 40, was not new. The ’678 patent states that “[s]uch
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`substrates can be purchased commercially.” (Ex. 1001, 4:2). Also shown in
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`Figure 1, for the first step (labeled “20”) is a via, 48, etched through layer 46.
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`38. The second step, 22, (labeled “Form Microelectronic Circuit” in Fig.
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`1) is a process sequence consisting of well-known semiconductor fabrication steps
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`which is first used to form one or more microelectronic circuit elements (50). The
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`present substrate is next processed so that both front side conductors (indium
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`bumps, 61) and back side conductors (backside electrical interconnect) are present.
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`14
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`

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`39.
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`In the third step, 24, (labeled “Attach Second Substrate” in Fig. 1), a
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`second substrate, 58, which may include devices, is attached to the front of the
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`structure, and is electrically contacted by the indium bumps, 61. An excerpt from
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`Fig. 1 is reproduced below, with the second substrate, 58, highlighted in yellow.
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`
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`The second substrate, 58, and wafer, 46, are physically bonded (using, for
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`example, epoxy), and are electrically connected (using, for example, an indium
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`solder process). The second substrate may include its own microelectronic circuit
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`element.
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`40.
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`In the fourth step, 26, (labeled “Remove Etchable Layer in Fig. 1), the
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`etchable layer, 42, is removed, but the etch stop layer, 44, and the layers above 44
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`are left. The structure may be attached a base (for example, a piece of aluminum
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`oxide, preferably sapphire), 62, by a layer of wax, 64. An excerpt from Fig. 1 is
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`reproduced below, with the sapphire support and wax layer highlighted in yellow.
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`15
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`

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`
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`The etchable layer, 42, is removed, for example, by an etching process in which
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`the etchable layer is exposed to a liquid etchant. The ’678 describes the etchant in
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`the following passage:
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`“The etchant is chosen so that it attacks the etchable layer 42
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`relatively rapidly, but the etch-stop layer 44 relatively slowly or not at
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`all. The terms 'etchable' and 'etch-stop' indicate a relative relation to
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`each other in a particular etchant, as used herein. They are relative to
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`each other and to the selected etchant.” (Ex. 1001, 5:52-57).
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`41.
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`In the fifth ste