United States Patent [191
`Tran et al.
`
`[54] SOLID STATE ELECTROMAGNETIC
`RADIATION DETECTOR FET ARRAY
`
`[75] Inventors: Nang T. Tran, Cottage Grove, Minn;
`Neil w. Loeding, Wills Point, Tex.;
`David V- NillS, late Of 51- P?lll, Minn,
`by Mary J- NinS, administrator
`
`_
`[73] Ass1gnee: Minnesota Mining and
`Mfmllfacml'illg Company, 51- P8111,
`Mlm'h
`
`[211 APPL NO~= 564,632
`_
`[22] Flled:
`
`Aug‘ 8’ 1990
`
`llllllllllllllllllllllllllllllllllllllllllIllllIllllIllllllllllllllllllllll
`US005 1 82624A
`[11]
`5,182,624
`Patent Number:
`[45] Date of Patent:
`Jan. 26, 1993
`
`FOREIGN PATENT DOCUMENTS
`58-182280 10/1983 Japan .
`
`OTHER PUBLICATIONS
`Japanese Journal of Applied Physics, vol. 27, No. 12, Dec.
`1988, pp. 2404-2408, Hiroshi Tsunemi et al., “Applica
`tion of a Frame Transfer-Type CCD as an X-Ray
`Image Sensor”‘
`Proceedings of Electronic Imaging West, Pasadena, Calif.,
`pp. 210—2l3, (Feb. 25-28, 1990), Biac, “A Wide Field of
`View IR CCD Camera”.
`'
`s. Sherr, Electronic Displays, pp. 182-320, (1979), Wiley
`& Sons, NY.
`Toshihisa Hamano et al., (Proc. of the 13th Conference
`on Solid State Devices, Tokyo, 1981), Japanese Journal
`
`o
`
`
`
`
`
`CéiS .................................. g o I n - e - e - a e u e Q - ~ - u n u a s 4 a - I e 4 e - - - 0 I a ‘-
`
`,
`
`n
`
`,
`
`
`
`Physics, vol‘ 21’ _ 4 ‘6
`
`' H‘
`
`
`
`
`
`supplement 21-1’ L' I
`
`250/3383; 250/338.4; 257/292; 257/444;
`257/442; 257/59; 257/41
`,
`Fleld 0f Se?rCh .................. no
`G,
`H,
`357/30 1’ 30 D’ 32’ 28’ 59 F’ 2’ 25’ 8’ 4;
`250/3381, 338.3, 338.4
`
`221833’ A“ Ammph‘ms S‘ ‘gh Speed ‘near mage
`SID International Symposium Digest of Technical Pa
`ers
`Ma
`et al
`EAmopphouySilicon A110’ Coiitact T e Ima e Sen:
`some rp
`y
`W g
`
`[56]
`
`References‘Cited
`Us’ PATENT DOCUMENTS
`
`Primary Examiner-William Mintel
`Attorney, Agent, or Firm-Gary L. Griswold; Walter N.
`Kim; David B. Kagan
`
`3,539,803 12/1967 Beerman . . . . . . . . . . .
`
`. . . . . . .. 250/83
`
`,
`
`,
`
`er et al. .... ..
`
`307/88 ET
`. . . . . 1 ., 357/31
`
`357/23
`
`250/338
`264/22
`364/22
`250/338
`357/301
`358/ 21341
`358/213 11
`
`ABSTRACT
`[57]
`3,809,920 5/1974 Cohen et al. ..
`The present invention provides a large area, high pixel
`3,346,820 11/1974 Lampe 61 al . . . . .
`density solid state radiation detector with a real-time
`gngeier 8:211‘ """ "
`and a non-destructive read-out. The solid state detector
`4’024’56O 5/1977 M’hglc Cr C a‘ """ "
`compnses a plurallty of ?eld effect transistors deposited
`4,258,259 3/1981 Chara a 3L ____ __
`onto a substrate to form an array. A planarization layer
`4,606,371 55/1936 Kmeger et a1_
`is deposited over the array of translstors. An energy
`4,615,848 10/1986 Krueger et a1.
`sensitive layer is deposited onto the planarization layer.
`4,626,687 12/1986 Nara et a1. .......... l.
`Means is provided for electrically connecting the en
`4,670,765 6/1987 Nakamura et al
`ergy sensitive layer with each transistor of the array. A
`4y672,454 6/1987 Cannena 6‘ a1~ ---- --
`top electrode layer is deposited onto the energy sensi
`416751739 6/1987 caclllmle 8‘ al'
`tive layer. The solid state detector also comprises cir
`gislzlalslgslii
`''''' "
`. . . .. 357/32 x “my means for Providing electmnic read'out from
`4:739:384 4/1988 Hi?asi et al.
`. .
`357/30 H each PET of the may
`4,740,824 4/1988 Yano et al.
`.. 250/370.0l
`4,8l0,881 3/1989 Berger et al. .
`4,820,586 4/1989 Krueger et a1. ................... .. 428/421
`
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`Raytheon2063-0001
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`Sony Corp. v. Raytheon Co.
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`1
`
`SOLID STATE- ELECTROMAGNETIC RADIATION
`DETECTOR FET ARRAY
`
`FIELD OF THE INVENTION
`The present invention relates to a solid state detector
`for detecting electromagnetic radiation, and more par
`ticularly to a large area, high pixel density solid state
`detector based on a two dimensional array of ?eld effect
`transistors and an energy sensitive layer coating the
`array.
`
`20
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`25
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`35
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`5,182,624
`2
`pyroelectric material of these devices is individually
`bonded to the ?eld effect transistor, it has been dif?cult
`to achieve pixel sizes on the order of l mm><l mm or
`less.
`As another drawback, the active detection area of
`such devices is, at most, only a few square centimeters
`in size.
`-
`As another drawback, hybrid structures tend to be
`susceptible to harm caused by events such as radiation
`induced damage. For example, if too much voltage is
`applied to such detectors, such voltage can irreparably
`damage the pyroelectric material, i.e., the gate dielec
`tric layer, of the FET. This kind of damage could im
`pair the performance of, or even destroy, the detector.
`As a consequence of these drawbacks, previously
`known hybrid structures have not been practical for
`high density, large area applications.
`Solid state detector arrays have also been known.
`One type of solid state detector array is the charged
`coupled device (“CCD”). In essence, a CCD is a shift
`register formed by a string of closely spaced MOS ca
`pacitors. A CCD can store and transfer analog-charge
`signals, either electrons or holes, that may be intro
`duced electrically or optically.
`In Japanese Journal of Applied Physics, vol. 27, no.
`12, December 1988, pp. 2404-2408, Hiroshi Tsunami et
`al. discuss the application of CCD’s to take x-ray images
`of about 8 keV and 1.5 keV for different objects. High
`resolution CCD sensors which have more than 2 to 4
`million pixels have also been reported, for example, in
`the Proceedings of Electronic Imaging West, Pasadena,
`California, pp. 210-213 (Feb. 25-28, 1990); and in Elec
`tronic, pp. 61-62 (Feb. 29, 1988).
`The high cost of the CCD, however, has been a bar
`rier to widespread commercial acceptance of these de
`vices. CCD’s, too, require an optical system in order to
`enlarge the ?eld of view. The use of an optical system,
`unfortunately, causes a signi?cant reduction in quantum
`ef?ciency. This makes it impractical to use the CCD for
`large area detectors. To date, the largest CCD array
`reported has been less than one square inch in size.
`Amorphous silicon recently has become a material of
`choice in many solid state detector applications due to
`its capability for large area deposition and the low cost
`of amorphous silicon detectors. Amorphous silicon
`based solid state detectors generally have been in the
`form of a linear array. Such devices have gained wide
`spread acceptance for use as monolithic, full page high
`resolution detectors, due to the following advantages:
`(1) large area deposition capability, (2) low temperature
`deposition, (3) high photoconductivity, (4) spectral
`response in the visible light region and (5) high doping
`ef?ciency.
`An amorphous silicon linear array is discussed by
`Toshihisa Hamano et al. (Proc. of the 13th Conference
`on Solid State Devices, Tokyo, 1981, Japanese Journal
`of Applied Physics, Vol. 21 (1982) supplement 21-1, pp.
`245-249). In this structure, metal (Au, Ni, or Cr, thick
`ness of 3,000 angstroms) is used for the bottom elec
`trode and Indium Tin Oxide transparent conducting
`?lm is used for the top electrode. Glass plates (Coming
`7059, PYREX) are used for the substrate. Amorphous
`silicon (a-SizH) ?lm with a thickness of 1 micron is
`deposited by plasma-enhanced chemical vapor deposi
`tion technique onto the substrate.
`For x-ray applications, US. Pat. No. 4,675,739 de
`scribes a solid state linear array made from photosens
`
`60
`
`_ BACKGROUND OF THE INVENTION
`Solid state electromagnetic radiation detectors have
`been developed for consumer, commercial, scienti?c,
`medical, military and industrial applications. Consumer
`applications range from video to high density television.
`Industrial uses include robotic and machine vision; elec
`tronics imaging for advertising and communication;
`integrated text; and images in of?ce work and publish
`ing. Image sensors are also used for medical (mammog
`raphy, chest x-rays), astronomy, spectroscopy, surveil
`lance, airport luggage inspection, inspection for foreign
`objects in foodstuffs, non-destructive testing in indus
`try, and many other applications.
`Solid state devices used for detecting electromagnetic
`radiation, such as x-rays, infrared radiation, ultraviolet
`radiation, and visible light, store the image momentarily
`and then, after a selected time interval, convert the
`image to an electrical signal. A variety of solid state
`detectors are known. One type of solid state detector is
`the “hybrid” detector. A hybrid detector generally
`comprises a pyroelectric material that is bonded to a
`?eld effect transistor (“FET”). The FET in such detec
`tors is used as an ampli?cation means to amplify the
`signal from the detector before the signal is sent to the
`read-out electronics. Crystalline pyroelectric materials
`such as strontium barium niobate, lead titanate, and
`triglycine sulfate (“TGS”) are well known in the art. In
`addition, ?lms of organic polymers such as polyvinyli
`dene ?uoride and polyacrylonitrile have also been used
`as pyroelectric materials.
`For example, U.S. Pat. No. 3,809,920 teaches the use
`of a polyvinylidene ?uoride ?lm in conjunction with an
`FET as being an effective and useful infrared radiation
`detector.
`U.S. Pat. No. 4,024,560 discloses an infrared detector
`which is a combination of a pyroelectric body secured
`by electrostatic bonding to the gate area of a ?eld effect
`transistor such that the pyroelectric body is interposed
`between the semiconductor body and the gate elec
`trode. In this position, the pyroelectric body forms the
`gate dielectric of the device. A pyroelectric crystal is
`typically cleaved, or cut, to form the pyroelectric body.
`Japanese Kokai (Laid-Open) Publication JP58
`55
`182280 discloses a photodetector comprising a thin ?lm
`FET and a pyroelectric material. The pyroelectric ma
`terial forms the gate'dielectric layer in this device.
`Previously known hybrid structures suffer from a
`number of drawbacks. One drawback of hybrid struc
`tures concerns the pixel size of such devices. Generally,
`pixel size corresponds to the resolution of a detector. A
`smaller pixel size means a higher density of pixels for
`higher resolution. In previously known hybrid struc
`tures, the pyroelectric material has been positioned as
`the gate dielectric layer of the FET. As a result of this
`approach, achieving smaller pixel sizes has been limited
`by the size of the'pyroelectric material. Because the
`
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`process, especially when the energy sensitive layer is
`ing elements. Each photosensing element includes back
`relatively thick, i.e., thicker than. 10 microns. As a con
`to-back diodes: one a photoresponsive diode and the
`sequence, the solid state detector is amenable to mass
`other, a blocking diode. Each of the diodes has an asso
`production techniques so that large area, solid state
`ciated capacitance formed by its electrodes. The magni
`detectors can be fabricated in large numbers at rela
`tude of the charge remaining on a given capacitor is
`tively low cost. Large area means that the detector may
`sensed and relates back to the intensity of the incident
`have a radiation detecting area greater in size than 10
`radiation impinging upon the photosensitive diode. In
`this structure, an amplifying means, i.e., a ?eld effect
`cm X10 cm.
`'
`Further, the present invention also differs from previ
`transistor is not used.
`ously known FET-containing, solid state detectors in
`Solid state detectors in the form of a linear array,
`that the energy sensitive layer of the present invention is
`however, must be moved in order to get a two-dimen
`not positioned as the gate dielectric layer of the FET’s.
`sional image. This introduces a long read-out time,
`Instead, the energy sensitive layer functions as an addi
`which makes real-time read-out impractical. This draw
`tional capacitance which is, in effect, connected in se
`back prevents the linear array detector from being used
`ries with the gate capacitance of each FET of the array.
`in applications where high speed is required, e.g., medi~
`This approach provides at least two advantages.
`cal x-ray applications.
`First, this approach provides solid state detectors with
`U.S. Pat. No. 4,689,487 describes the use of a large
`higher pixel density than previously known structures
`area solid state detector (40 cm X40 cm). The solid
`that are based on the FET. According to the present
`state detector includes pixels in the form of a
`invention, pixel size is determined by the size of the gate
`2,000X2,000 matrix. Each pixel consists of a photodi
`region on each FET of the array. In preferred embodi
`ode conductively connected in parallel to a capacitor.
`ments of the present invention comprising a plurality of
`The photodiode and the capacitor are both then con
`thin ?lm FET’s, the gate region of each FET is ex
`ductively connected to the drain of a metal-oxide-semi
`tremely small. Sizes of from 20 microns><20 microns to
`conductor ?eld effect transistor (MOSFET). The pho
`50 microns><50 microns are typical. As a result, pixel
`todiodes are of a polycrystalline or amorphous material
`densities as high as 250,000 pixels/cm2 can be achieved.
`This diode-MOSFET device has at least four main
`Second, this approach provides solid state detectors
`drawbacks. First, a non-destructive read-out cannot be
`that are less susceptible to harm caused by events such
`used. Second, the sensitivity of the device is low. Third,
`as radiation induced damage. According to the present
`the diode has to be operated in the forward mode in
`invention, it is the energy sensitive layer that protects
`order to turn on the transistor. Fourth, the device re
`quires at least 8 complex microlithography and deposi
`the solid state radiation detector from such harm. If a
`high voltage is applied to the detector, the voltage of
`tion steps for fabrication, causing yields to be low.
`preferred embodiments will tend to drop mainly in the
`U.S. Pat. Nos. 4,606,871, 4,615,848, and 4,820,586
`energy sensitive layer, whose capacitance is typically
`disclose a pyroelectric material that is a blend of polyvi
`lower than the gate capacitance. In this way, damage to
`nylidene ?uoride (“PVFZ”) and at least one polymer
`the FET’s of the array is minimized.
`miscible therewith at a temperature above the melting
`The present invention is also a real-time detector.
`point of the PVF1. The ?lm may be polarized to render
`Read-out times of the detector of from 1 to 4 seconds
`the PVFZ blend pyroelectric and isotropically piezo
`are feasible. Read-out time is de?ned as the time elaps
`electric. Example 10 in each of these patents describes
`ing between the time an object is subjected to illumina
`the coating of an integrated circuit slice of a single
`tion and the time an image appears on the monitor.
`crystal silicon chip with the PVFZ blend, followed by
`The present invention also has a non-destructive
`the sputtering of gold onto the surface of the PVF; for
`poling.
`read-out. Non-destructive read-out means that the
`charge stored in the energy sensitive layer will dis
`charge gradually over a period of time. This allows
`several readings to be taken at each exposure. The sig
`nal can then be averaged, thereby enhancing the signal
`to noise ratio.
`
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`SUMMARY OF THE INVENTION
`The present invention provides a large area, high
`pixel density, solid state detector with a real-time and a
`non-destructive read-out. It is believed that the solid
`state detector of the present invention is the ?rst practi
`cal, large area, high pixel density solid state detector
`that is based on a two-dimensional array of ?eld effect
`transistors (“FET’s” .
`The solid state detector of the present invention com
`prises a plurality of ?eld effect transistors (“FET’s”)
`55
`deposited onto a substrate to form an array. A planari
`zation layer is deposited over the array of FET’s. An
`energy sensitive layer is deposited onto the planariza
`tion layer. Means is provided for electrically connecting
`the energy sensitive layer with each FET of the array.
`A top electrode layer is deposited onto the energy sensi
`tive layer. The solid state detector also comprises cir
`cuitry means for providing electronic read-out from
`each FET of the array.
`The present invention enjoys a unique combination of
`advantages. Because the energy sensitive layer is coated
`65
`over the entire array of FET’s, patterning or individual
`placement of the energy sensitive layer onto each FET
`is not required. This greatly simpli?es the fabrication
`
`60
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a cut-away isometric view of the solid state
`detector of the present invention shown in schematic
`with parts broken away and shown in section.
`’ FIG. 2 is an electronic circuit diagram of the solid
`state detector of the present invention shown in FIG. 1.
`FIG 3a is a side section of a substrate useful in the
`practice of the present invention.
`FIG. 3b is a side section of a substrate useful in the
`practice of the present invention.
`FIG. 30 is a side section of a substrate useful in the
`practice of the present invention.
`FIG. 3d is a side section of a substrate useful in the
`practice of the present invention.
`FIG. 4 is a side section of a solid state detector of the
`present invention.
`'
`FIG. 5a is a side section of the solid state detector
`shown in FIG. 4, wherein the planarization layer has a
`double layer structure.
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`FIG. 5b is a side section of the solid state detector
`shown in FIG. 4, wherein the planarization layer has a
`triple layer structure.
`FIG. 5c is a side section of the solid state detector
`shown in FIG. 4 further comprising a phosphor layer.
`FIG. 5d is a side section of the solid state detector
`shown in FIG. 4, further comprising an additional insu
`lating layer for charge storage.
`FIG. 6 is a side section of an alternative embodiment
`of the present invention.
`FIG. 7 is the equivalent circuitry for one FET of a
`solid state detector of the present invention.
`FIG. 8 shows an apparatus useful for poling an en
`ergy sensitive layer which comprises a PVFZ blend.
`
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`6
`long as the various .top electrode elements are electri
`cally connected together so as to form a common top
`electrode. For example, the top electrode layer 23 may
`be patterned such that there is one top electrode ele
`ment for each FET 11 of the array. As another example,
`the top electrode layer 23 may be patterned such that
`there is one top electrode element for each row or col
`umn of FET’s 11 in the array.
`Generally, the solid state detector 10 works as fol
`lows. A power source 28 is used to apply a charge to the
`energy sensitive layer 20. Incident radiation causes a
`corresponding change in the charge of the energy sensi
`tive layer 20. This change in charge, in turn, causes the
`gate voltage of the FET’s 11 to increase or decrease,
`depending upon the type of FET used in the array. This
`change in voltage is detected as a difference in the
`drain-source current of the FET 11. The difference in
`current is then ampli?ed and detected as an output
`signal by the read-out electronics. As seen in FIG. 2,
`one possible read-out electronics scheme may include
`operational ampli?ers 24 for boosting the analog signal
`from the FET’s 11. This analog signal is then converted
`into a digital signal by an A/D converter 25. The digital
`signal is then stored in the memory of a memory storage
`device 26. As is also shown in FIG. 2, source lines 17
`are coupled to shift register 27.
`Preferred substrates useful in the practice of the pres
`ent invention are shown in FIGS. 30, 3b, 3c, and 3d.
`FIG. 3a shows a substrate 29 comprising a ?exible base
`layer 30. Generally, the base layer 30 is planar in shape.
`Useful materials for forming the flexible base layer 30
`include stainless steel and polymers such as polyirnide,
`polysulfone, or polyester. If the base layer 30 is formed
`from a polymeric material, the base layer 30 should be
`subjected to a conventional outgassing treatment before
`any other layers are deposited onto the base layer. Pref
`erably, the base layer 30 has a thickness of about 50
`microns.
`When the base layer 30 is formed from a polymeric
`material, it is preferred that the base layer 30 is ?rst
`coated on both sides with top and bottom layers 31 and
`32 of stainless steel as described in assignee’s copending
`application U.S. Ser. No. 07/471,670 ?led Jan. 24, 1990,
`currently pending, which is a continuation of U.S. Ser.
`No. 07/163,520 ?led Mar. 2, 1988, now abandoned.
`Each of the stainless steel layers 31 and 32 preferably
`has a thickness of about 200 angstroms. The stainless
`steel is used to prevent or suppress the outgassing of
`low mass residual contaminants from the base layer 30.
`Next, an insulating layer 33 is coated onto the top
`stainless steel layer 31. The insulating layer 33 is used to
`electronically isolate the base layer 30 from the ?eld
`effect transistors subsequently deposited onto the sub
`strate 29. The insulating layer 33 also helps prevent
`impurities in the base layer 30 from diffusing into the
`?eld effect transistors. The insulating layer 33 may be
`prepared from any suitable material such as SiOx, SiNX,
`silicon oxide nitride, or combinations thereof. Prefera
`bly, the insulating layer 33 has a thickness of about 1
`micron. Optionally, an additional insulating layer 34
`may be coated onto the bottom layer 32 of stainless steel
`as is shown in FIG. 3b for the substrate 29’.
`Another embodiment of a substrate 35 useful in the
`practice of the present invention is shown in FIG. 30. In ‘
`FIG. 3c. the substrate 35 comprises a rigid, nonpoly
`meric base layer 36. Useful materials for forming the
`rigid base layer 36 include silicon, glass, quartz, alu
`mina, or metal. In this embodiment, an insulating layer
`
`60
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`A preferred solid state detector 10 of the present
`invention will now be described with reference to FIG.
`1 and FIG. 2. A plurality of thin ?lm, ?eld effect transis
`tors (“FET’s”) 11 are deposited onto a substrate 12 to
`form an array. Preferably, the FET’s 11 are aligned on
`the substrate 12 in rows and columns as shown in FIG.
`1. However, the FET’s 11 may be arranged in other
`patterns on the substrate 12. For example, adjacent
`FET’s 11 may be offset up, down, or diagonally from
`each other. Each of the FET’s 11 has a source electrode
`13, a drain electrode 14, and a gate electrode 15. As seen
`best in FIG. 2, each FET 11 also has a gate capacitance,
`30
`C(;.
`The solid state detector 10 comprises circuitry means
`for providing electronic read-out from each FET 11 of
`the array. The design requirements for such circuitry
`are described, for example, in L. Tannas, Jr., ed., Flat
`Panel Displays and CRTs, pp. 91-137 (1987); and S.
`Sherr, Electronic Displays, pp. 182-320 (1979). Prefera
`bly, the circuitry means comprises a plurality of source
`lines 17 linking the source electrodes 13 in each row of
`FET’s 11 and a plurality of drain lines 18 linking the
`drain electrodes 14 in each column of FET’s 11. For
`40
`example, for an array comprising a 2000x2000 matrix
`of FET’s, there will be 2000 source lines and 2000 drain
`lines in the solid state detector.
`The various source lines 17 and drain lines 18 should
`45
`not be in electrical contact with one another. That is, a
`source line should not contact other source lines or any
`of the drain lines, and a drain line should not contact
`other drain lines or any of the source lines. For this
`reason, at least one planarization layer 19 is deposited
`over the array of FET’s 11 in order to electrically iso
`late the source lines 17 and the drain lines 18.
`An energy sensitive layer 20 is deposited onto the
`planarization layer 19. Means 21 is provided for electri
`cally connecting the energy sensitive layer 20 with each
`FET 11 of the array. Preferably, such means 21 electri
`cally connects the energy sensitive layer 20 with the
`gate electrode 15 of each FET 11 of the array. As seen
`best in FIG. 2, using this preferred approach, the energy
`sensitive layer 20 functions as an additional capacitance,
`Ca, which is, in effect, electrically connected in series
`with the gate capacitance C6 of each FET 11 in the
`array.
`A top electrode layer 23 is deposited onto the energy
`sensitive layer 20 in order to complete the solid state
`detector 10. The top electrode layer 23 shown in FIG.
`1 has not been patterned to form a plurality of top elec
`trode elements. However, the top electrode layer 23
`optionally may be patterned in a variety of ways, so
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`Raytheon2063-0010
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`15
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`20
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`25
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`30
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`35
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`7
`37 may be preferably deposited directly onto the top
`surface of the base layer 36 as needed in order to pre
`vent impurities from migrating from the base layer 36
`into the FET’s and/or to electronically isolate the
`FET’s from the base layer 36. Optionally, as shown in
`FIG. 34', an additional insulating layer 38 may be depos
`ited onto the bottom surface of the base layer 36 of the
`substrate 35,
`FIG. 4 is a cross-section of a portion of a preferred
`solid state radiation detector 40 of the present invention,
`in which two thin ?lm, metal-oxide-semiconductor ?eld
`effect transistors (“MOSFET’s”) 41 of the array are
`shown. For purposes of clarity, source lines and drain
`lines are not shown in FIG. 4. As is known to those
`skilled in the art, each thin ?lm MOSFET 41 generally
`_ comprises a channel layer 42; a gate dielectric layer 43,
`i.e., oxide layer; insulating shoulders 44; source and
`drain regions 45 and 46; source and drain electrodes 47
`and 48; a polysilicon gate 49; and a gate electrode 50;
`each of which will be described in more detail below. In
`FIG. 4, the vertical dimensions of the various layers are
`greatly exaggerated for purposes of illustration. In ac
`tual practice, the total thickness of the solid state radia
`tion detector 40 is from about 3 to about 600 microns.
`As shown in FIG. 4, a channel layer 42 of an undoped
`semiconducting material is formed on the substrate 51
`for each thin ?lm transistor of the array. The channel
`layer 42 can be formed in a variety of ways. For exam
`ple, a layer of the undoped semiconducting material can
`be deposited onto the substrate 51 and then etched or
`laser scribed to form the channel layer 42 for each
`MOSFET 41. Alternatively, a mask can be used to
`deposit the discrete islands of undoped semiconducting
`material onto the substrate 51 to directly form the chan
`nel layer 42.
`The channel layer 42 may be formed from any un
`doped semiconducting material suitable for large area
`applications. Examples of such materials include hydro
`genated amorphous silicon, cadmium selenide, single
`crystal silicon, and polysilicon. Single-crystal silicon
`based FET’s are well known in the art and are de
`scribed, for example, in S. M. Sze, Physics of Semicon
`ductor Devices, 2d edition, pp. 431-510 (1981).
`When forming the channel layer 42 from hydroge
`nated amorphous silicon, the hydrogenated amorphous
`45
`silicon may be deposited using plasma-enhanced chemi
`cal vapor deposition at 200° C. to 350° C. from a gase
`ous mixture of SiH4 and hydrogen. Cadmium selenide
`may be deposited onto the substrate 51 by deposition
`techniques well known in the art. For example, by using
`a cadmium selenide source, thermal evaporation or
`sputtering techniques may be used to deposit the cad
`mium selenide. Alternatively, a cadmium layer and a
`selenium layer may be deposited onto the substrate 51
`and then heat treated at 100° C. to 400° C. in an atmo
`sphere comprising hydrogen selenide and argon in
`order to form the cadmium selenide layer. The cad
`mium and selenide layers may be deposited using elec
`troplating or sputtering techniques.
`Preferably, the channel layer 42 is formed from
`polysilicon. When forming the channel layer 42 from
`polysilicon, polysilicon can be deposited onto the sub
`strate 51 using a variety of techniques, including:
`(i) low pressure chemical vapor deposition at‘ a tem
`perature from 620' C. to 650° C.;
`(ii) deposition of amorphous silicon by low pressure
`chemical vapor deposition at a temperature from 520°
`C. to 540° C., followed either by annealing at 620° C. to
`
`5,182,624
`8
`1000" C. for 2 to 24 hours in a nitrogen atmosphere to
`form polysilicon, or by rapid thermal annealing at 620°
`C. for 1 to 4 minutes in a nitrogen atmosphere to form
`polysilicon;
`(iii) deposition of amorphous silicon at 200° C. to 300°
`C. via plasma-enhanced chemical vapor deposition,
`followed by furnace annealing, laser annealing, or rapid
`thermal annealing;
`.
`(iv) high temperature chemical vapor deposition of
`polysilicon at 620° C., conversion of the polysilicon to _
`amorphous silicon via ion implantation with silicon
`ions, followed by annealing at 620° C. for 4 to 24 hours
`to form polysilicon.
`Typically, the channel layer 42 of undoped polysili
`con has a thickness of from about 1000 to 3000 ang
`stroms. Because polysilicon is deposited onto the sub
`strate 51 at relatively high temperatures, the base layer
`of the substrate 51 for the polysilicon-based MOSFET’s
`should comprise a material that does not degrade at
`such temperatures, e.g., quartz, silicon, alumina, or
`glass.
`An oxide, i.e., gate dielectric, layer 43 and insulating
`shoulders 44 are formed on the channel layer 42. To
`accomplish this, a layer of an insulating material, such
`as SiOx, SiNx, silicon oxide nitride, or combinations
`thereof, is grown by thermal oxidation on the channel
`layer 42. The layer of insulating material is then etched,
`or laser scribed, to form the insulating shoulders 44 and
`the gate dielectric layer 43. This process also uncovers
`two spaced~apart surfaces on the channel layer 42 for
`the subsequent formation of source and drain electrodes
`47 and 48, respectively.
`A polysilicon gate 49 is deposited onto the gate di
`electric layer 43. Typically, the polysilicon gate 49 has
`a thickness of about 500 to about 3500 angstroms. Pref
`erably, the ‘polysilicon gate 49 is deposited orito the
`layer of insulating material before the layer is etched, or '
`laser scribed, to form the insulating shoulders 44 and the
`gate dielectric layer 43.
`Using the polysilicon gate 49 and insulating shoulders
`44 as a mask, the source and drain regions 45 and 46 are
`formed by using conventional ion implantation tech
`niques to dope the source and drain regions 45 and 46
`with either boron ions (p-type) or phosphorous ions
`(n-type). The ion concentration will vary with the par
`ticular electrical characteristics and sensitivity of the
`desired detector. As an example, ion concentrations of
`IX 1014 ions/cm2 to 9 X 1015 ions/cm2 are typical.
`Ion implantation to form the source and drain regions
`45 and 46 can occur either before or after the layer of
`insulating material is etched, or laser scrib