O
`
`United States Patent [19]
`Wahlstrom
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,829,018
`May 9, 1989
`
`A 31151“! S§1‘¥“°°“d‘;°t:f.m‘e§m§d ‘mu; ‘5. fab”
`135; 148/DIG. 164; 156/657; 156/633; 357/75
`[58] Field 6: Search .............. .. 357/75; 148/DIG. 12, “F . y Pm“ mg a P ‘1’ “Y ° 5“ Pirates .avmg a“
`epltaxlal layer On One sllll'face and a. SlhcQn OXld?: layer
`on the surface of the epitaxial layer. The substrates are
`sequent1ally stacked w1th the when made layers 1n
`contact and fused together. One substrate is retained as
`afsupplortt: and other substrates are removed by etching
`a ter t e usion of the silicon oxide layers, thereby leav
`.
`.
`.
`. .
`mg. my the Stacked eplmlal my?“ Separated "2’ Sum“
`oxide. The stacked structure facilitates the vertical fab
`ncatwn of CMOS translstor palrs Shanng a common
`gate electrode in an epitaxial layer between the two
`transistors. Electrical isolation between the epitaxial
`layers is provided by the fused silicon oxide or by re
`‘fmving the sllldc‘g‘ °x1de “$1.5m: “95151899111950
`°¥mmg f‘ "°‘_ “ween ‘1 Jaw‘ eP‘Fa’“. Wm 1r‘
`cu" _deY1C=S m the Plurahty 0f epltaxlal layers are
`readlly Interconnected by forming conductive vias be‘
`tween the epitaxial layers.
`
`[54] MULTILEVEL INTEGRATED CIRCUITS
`EMPLOYING FUSED OXIDE LAYERS
`[76] Inventor: Sven E. Wahlstrom, 570 Jackson 131.,
`P310 Alto, Calif. 94303
`
`_
`[21] Appl' No" 879’738
`[22] Filed:
`Jun. 27, 1986
`{51] Int. c1» .................... .. H01L 21/70; H01L 27/00
`[52] US. Cl. .................................... .. 437/51; 437/915;
`437/ 84; 437/208; 437/984; 437/ 974; 148/DIG.
`
`[56]
`
`437/974, 984’ 40, 51’ 83’ 84’ 225’ 208, 915
`.
`References Clted
`us, PATENT DOCUMENTS
`
`1 al. .... .. 148/1316. 12
`3,508,980 4/1970 J ks ,J .
`........... .. 148/DIG. 164
`3,564,358 2/1971
`148/DIG_ 135
`3,959,045 5/1976 Amypas
`3,997,381 12/1976 Wanlass ............................. .. 156/657
`4,009,057 2/1977 de Brebisson et a1. ............. .. 437/31
`4,142,925 3/1979 King etal- -------------- -- 148/DIG- 135
`
`33g’???
`
`£15212” - - ' - -
`
`- ~ ~ - - - ~ ~
`
`,
`
`,
`
`un . . . . . . . . . . . . .
`
`. . . ..
`
`4,601,779 7/1986 Abernathey et al. .............. .. 148/l.5
`4,612,083 9/1986 Yasumoto et al. ..... .. 148/DIG. 164
`4,638,552 1/1987 Shimbo et a1.
`148/1316. 12
`4,649,627 3/1987 Abemithey et a1.
`l48/DIG. 164
`
`FOREIGN PATENT DOCUMENTS
`0161740 11/1985 European Pat. Off.
`l48/DIG. 12
`
`31 /
`
`OTHER PUBLICATIONS
`Fabm'am” P’mc'Ple" 1°11“ w?ey and
`Sham?"
`-
`“S, 11°"
`Primary Examiner-Brian E. Hearn
`Assistant Examiner-M. Wilczewski
`Attorney, Agent, or Firm-Flehr, Hohbach, Test,
`Album“ 8‘ Herbs"
`[57]
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`US. Patent May 9,1989
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`US. Patent‘ May 9, 1989
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`US. Patent May 9,1989
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`US. Patent May 9, 1989
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`Sheet 6 of 7
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`4,829,018
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`TRANSFER GATE
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`Raytheon2057-0007
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`

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`US. Patent '
`
`May 9, 1989
`
`Sheet 7 of 7
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`4,829,018
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`D-FLIP FLUP 3 LEVEL LAYEIUT
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`

`
`1
`
`MULTILEVEL INTEGRATED CIRCUITS
`EMPLOYING FUSED OXIDE LAYERS
`
`5
`
`4,829,018
`2 ,
`throughs can be readily provided. The ability to align
`the masks for processing the top layer after fusion and
`thinning to the epitaxial layer is facilitated by incorpo
`rating an alignment mark in the previous layer which
`can be seen through the top layer.
`In a preferred embodiment, an epitaxial layer is
`grown on the surface of a supporting substrate of single
`crystal material, and the surface of the epitaxial layer is
`oxidized. The oxidized surface is then bonded to the
`oxidized surface of a second, supporting substrate.
`Thereafter, the first substrate is removed by chemical
`etching. A heavily doped wafer with a thin epitaxial
`layer of lighter doping can be etched from the back
`with enough control to leave only the thin epitaxial
`layer. This process can be continued to form three or
`more layers of semiconductor material in which circuits
`and components can be fabricated.
`The ?rst layer may or may not be part of the support
`wafer. When employed as part of the support wafer,
`one less fusion and thinning step is required, but circuit
`speeds can suffer due to junction capacitances of the
`source and drain regions. On the other hand, by having
`a support wafer with a thick oxide layer and fusing the
`?rst active wafer to the thicker oxide, junction capaci
`tances can be eliminated and separation of devices can
`be provided by deep milling and etching down to the
`interface oxide.
`The invention and objects and features thereof will be
`more readily apparent from the following detailed de
`scription and appended claims when taken with the
`drawing, in which:
`
`20
`
`BACKGROUND OF THE INVENTION
`This invention relates generally to semiconductor
`integrated circuit technology, and more particularly the
`invention relates to multilayer integrated circuits.
`The semiconductor integrated circuit is fabricated by
`the selective introduction of dopants into a single crys
`tal semiconductor body through the use of photoresist
`masking and chemical etching of dopant barrier layers,
`diffusion and ion implantation of dopants through the
`patterns, and electrical interconnection layers. Circuit
`density is increased as these manufacturing techniques
`have improved. Typically, the integrated circuits have
`been fabricated in and on a single surface of a semicon
`ductor substrate.
`Greatly increased circuit density can be realized by
`providing layers of integrated circuits. U.S. Pat. No.
`4,233,671 describes a three dimensional processor sys
`tem in which a read only memory is fabricated in a
`polycrystalline silicon layer over a single crystal silicon
`substrate in which the microprocessor is fabricated. An
`25
`article entitled, “Simple Wafer Fusion Builds Better
`Power Chips” in Electronics Magazine, Dec. 23, 1985,
`page 20, discloses the formation of PN junction device
`structures in which P and N type silicon wafers are
`bonded together to make power devices. U.S. Pat. Nos.
`3,840,888 and 4,317,686 disclose discrete devices fabri
`cated on a supporting substrate.
`
`45
`
`SUMMARY OF THE INVENTION
`The present invention is directed to the fabrication of
`multilevel integrated circuits. The use of multilayers
`35
`facilitates the fabrication of a single circuit both verti
`cally and horizontally in the structure, thereby increas
`ing circuit density. In accordance with one aspect of the
`invention CMOS transistor pairs are vertically fabri
`cated in separate layers with a shared common gate
`therebetween.
`A feature of the invention is the stacking of semicon
`ductor epitaxial layers by fusing silicon oxide on the
`surfaces of the layers. Each epitaxial layer can accom
`modate a circuit and can cooperatively define circuits
`components such as CMOS transistors and capacitors.
`The bonded silicon oxide layers can provide dielectric
`isolation between the two semiconductor bodies. In
`creased dielectric isolation between circuit elements,
`for example, can be provided by forming voids in the
`fused silicon oxide layers.
`The voids can serve the same purpose as the ?eld
`oxide in conventional processes. A thick oxide is used to
`prevent turning on parasitic transistors in the layer un
`derneath the oxide. This requires a low capacitance
`between the layers. Due to the approximately 3.9 times
`lower dielectric constant in the void as compared to
`silicon oxide, a relatively thin void may serve the same
`purposes as a thicker silicon oxide. On the other hand,
`parasitic transistors are formed between diffused areas
`in a common body of silicon with the opposite dopant,
`so the problem will not occur where the devices are
`separated by deep trenches. In such cases, the only
`purpose of the voids is to minimize the capacitive cou
`pling between circuit elements in the two layers.
`Another feature of the invention is the use of optical
`alignment techniques which are readily employed in
`stacking the semiconductor bodies, and circuit feed
`
`55
`
`65
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIGS. 1-9 are section views of a semiconductor
`structure in accordance with the invention showing the
`steps in fabricating the structure including the fabrica
`tion of contacting and non-contacting feedthroughs.
`FIGS. 10A and 10B are a section view and electrical
`schematic of an MOS transistor and capacitor memory
`bit in accordance with an embodiment of the invention.
`FIGS. 11A and 11B are a section view and schematic
`of a CMOS inverter in accordance with one embodi
`ment of the invention.
`FIGS. 12A and 12B are a second view and a sche
`matic of a CMOS inverter in accordance with another
`embodiment of the invention.
`. FIG. 13 is a description of symbols utilized in illus
`trating a multilayer circuit in accordance with the in
`vention.
`'
`FIGS. 14A-14C illustrate symbolically a transfer
`gate.
`FIGS. ISA-15C illustrate symbolically an inverter.
`FIGS. 16A and 16B illustrate schematically a D flip
`?op circuit.
`FIG. 17 is a perspective view of the ?ip-flop circuit
`of FIGS. 16A and 16B in a multilayer integrated circuit
`in accordance with the invention.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`Referring now to the drawings, FIGS. 1-9 are sec
`tion views illustrating steps in fabricating an integrated
`circuit in accordance with the invention. As illustrated
`in FIG. 1, a ?rst silicon semiconductor substrate 10
`includes an epitaxial layer 12 grown thereon and a sili
`con oxide layer 14 grown on the epitaxial layer 12. A
`second silicon substrate 16 has an epitaxial layer 18 on
`
`Raytheon2057-0009
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`25
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`4,829,018
`4
`3
`from the bottom of the etched hole whereby deposited
`the surface thereof, and a silicon oxide layer 20 is
`silicide 24 (e.g. tungsten silicide or polysilicon) can
`formed on the surface of the epitaxial layer 18. In accor
`physically and electrically contact the epitaxial layer 12
`dance with the invention, the two substrates are placed
`without contacting layer 18.
`together with the silicon oxide layers 14, 20 in abutment
`as illustrated in FIG. 2. The two oxide layers are fused
`FIG. 7 shows a second milling/deposition step used
`together by heating the stacked structure to a tempera
`to interconnect circuits in layers 18 and 12. The comple
`ture in the range of 800°-l200° C. This causes the sili
`tion of the operation involves resist and oxide removal
`con oxide layers to fuse together without any lateral
`and surface cleaning, FIG. 8, and oxidation, FIG. 9. In
`distortion on either wafer. The time and temperature
`FIGS. 7 and 8 a similar interconnect via 26 is formed in
`for the fusion step is limited to prevent “drive-in” of the
`which the epitaxial layers 12 and 18 are electrically
`ions. After the stacked device is completed a ?nal heat
`interconnected. In FIG. 9 the top surface of an epitaxial
`treatment is provided for uniform “drive-in” in the
`layer 18 is oxidized before fusion of a third wafer.
`stacked layers.
`FIG. 10A illustrates a similar stacked structure in
`As illustrated in FIG. 3, the substrate 16 is removed
`cluding two additional epitaxial layers 28 and 29 sepa
`by chemical etching thereby leaving the silicon sub
`rated by oxide 30 formed on the structure. An MOS
`strate 10 as a supporting substrate for the epitaxial layer
`transistor 31 is formed in the top epitaxial layer 29 by
`12 and the epitaxial layer 18 with the two epitaxial
`diffusing a P-region 32 in N layer 29. A word line is
`layers being separated by the fused oxide layers labeled
`provided by a metal or silicide layer 33 formed on a
`14. The removal of substrate 16 by etching utilizes the
`silicon oxide layer 34 on the surface of epitaxial layer
`strong dependence in the etch rate on the resistivity of
`20
`28. The bit line 36 is formed in the top epitaxial layer 28
`the semiconductor material. For example, heavily
`and consists of N+silicon. A capacitor 38 includes a
`doped wafers with a thin epitaxial layer of much lighter
`portion of epitaxial layer 29 and underlying portions of
`doping can be etched from the back with enough con
`epitaxial layer 28, 18, and 12. The completed circuit is
`trol to leave only the thin epitaxial layer, as shown in
`shown schematically in FIG. 10B.
`FIG. 3. In this case, wafer 10 can be protected from the
`The memory structure of FIG. 10A results after three
`etch by a suitable photoresist mask.
`fusion and thinning operations plus normal processing
`The fusion and etchant steps illustrated in FIGS. 1-3
`of the top layer. It will be noted that essentially only
`can be repeated to form a multilayer structure as re
`two masks are required to build the lower layers of the
`quired for a particular three dimensional integrated
`multilayer capacitor. The function of the two masks are
`circuit with the circuit components fabricated in the
`interchanged at the addition of the next layer while a
`epitaxial layers and with the epitaxial layers electrically
`third mask will be used for surrounding the capacitor
`isolated by an insulating layer such as silicon oxide,
`layers with an insulating zone. In its simplest form the
`silicon nitride, or other feasible materials. Each layer
`insulation is accomplished by milling or reactive ion
`after fusing and thinning can be processed to contain the
`etching through the epitaxial layer thus creating a void
`devices and interconnection vias to the underlying lay
`when the next wafer is fused. Alternatively, the insula
`ers.
`tion zone can be a silicon oxide or silicon nitride.
`In order to manufacture circuits with multiple layers
`Using the techniques described above a simple
`having distinct circuit functions in each layer, the suc
`CMOS circuit can be readily fabricated. This is illus
`cessive layers must be accurately aligned. In one ap
`trated in FIGS. 11A and 11B which show a CMOS
`proach the individual circuits are fabricated in the wa
`inverter in three layers. The middle epitaxial layer is
`fers before fusion of the wafers. In this approach the
`used primarily for gate electrodes and for interconnec
`placement of one wafer on top of the other is made by
`tion from outputs to the gates. The field insulation is
`accurate lateral displacement using mechanical/ optical
`provided by voids created by milling, as described
`alignment techniques or by the use of laser drilled holes
`above. The sum of the oxide layers on the two fused
`that can function as a reference point for alignment.
`wafers de?nes the thickness of the gate oxide. The prac
`However, the preferred method of alignment takes
`tical controllable thickness of the semiconductor layer
`advantage of the topology feedthrough to the unpro
`is considerably less than one micron, which makes it
`cessed thin epitaxial layer after thinning. An alignment
`feasible to change the full depth of the layer by ion
`mark can be incorporated in the processing of the previ
`implant and drive-in. The formation of the transistors
`ous layer. If the new layer is thinner than approximately
`can be either by implant of P dopant into an N layer or
`one micron most of the visible spctrum can penetrate
`by implant of N dopant into a P layer. The simplicity of
`the layer making it possible to see an alignment mark of
`the CMOS circuits helps in reducing the chip area re
`sufficient contrast and thus permitting the use of stan
`quired for the sense ampli?ers in a dynamcc random
`dard mask aligners. For thicker layers short wavelength
`access memory such as described above with reference
`fringes due to the topology make it possible to locate an
`to FIG. 10A
`alignment mark that touches the new layer. The process
`The routing of signals if the successive silicon oxide
`of fusion and thinning can be repeated for increased
`layers are only a few hundred angstroms apart could
`stacking of layers, but with increased layers comes a
`lead to excessive capacitive loads. This is easily cor
`reduction in production yield. Three or four epitaxial
`rected by milling and thereby creating a void at cross
`layers on a supporting substrate is a optimum structure
`using conventional process techniques.
`overs.
`Consider now the fabrication of a multilevel dynamic
`FIGS. 12A and 12B are a section view and a sche
`matic, respectively, of an inverter in accordance with
`random access memory the fabrication of which is illus
`another embodiment of the invention. The embodiment
`trated in the cross sectional views of FIGS. 4-10. FIG.
`4 illustrates the initial etching of the structure for an
`is similar to the embodiment of FIGS. 11A and 11B
`except that the substrate 62 provides only support and
`interconnect via through the use of reactive ion etching,
`for example. In FIG. 5 an oxide layer 22 is grown over
`does not accommodate any electrical devices. Such a
`the etched surface, and in FIG. 6 the oxide is removed
`structure increases speed of circuit operation and obvi
`
`50
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`15
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`ates the need for junction or oxide isolation within the
`providing a second silicon semiconductor substrate
`substrate.
`having a ?rst silicon epitaxial layer on one surface
`The substrate 62 supports in order a ?rst oxide layer
`and a second silicon compound dielectric layer on
`63, a ?rst epitaxial layer 64, a second oxide layer 65, a
`a surface of said second epitaxial layer,
`second epitaxial layer 66, a third oxide layer 67, a third
`stacking said second silicon semiconductor substrate
`epitaxial layer 68, a ?eld oxide layer 67, and metal layer
`on said ?rst silicon semiconductor substrate with
`said ?rst and second silicon dielectric layers in
`contact,
`fusing said dielectric layers together,
`removing said second substrate by etching thereby
`leaving said ?rst substrate as a support for said ?rst
`epitaxial layer,
`forming elements of an electrical device in said ?rst
`epitaxial layer using photoresist masking,
`providing a third silicon compound dielectric layer
`on the surface of said ?rst epitaxial layer,
`providing a third silicon semiconductor substrate
`having a second silicon epitaxial layer on one sur
`face and a fourth silicon compound dielectric layer
`on the surface of said third epitaxial layer,
`stacking said fourth dielectric layer on the third di
`electric layer on said ?rst epitaxial layer,
`fusing said fourth dielectric layer to said third dielec
`tric layer on said surface of said ?rst epitaxial layer,
`removing said third silicon semiconductor substrate
`by etching thereby leaving said ?rst substrate as a
`support for said ?rst and second silicon epitaxial
`layers,
`forming elements of an electrical device in said sec
`ond epitaxial layer using photoresist masking and
`wherein a photomask is optically aligned by look
`ing through said second epitaxial layer to align
`ment marks on said ?rst epitaxial layer, and
`providing conductive vias between said ?rst epitaxial
`layer and said second epitaxial layer for intercon
`necting electrical components in said ?rst and sec
`ond epitaxial layers.
`~
`2. The method as de?ned by claim 1 and further
`including the steps of
`providing a ?fth silicon compound dielectric layer on
`the surface of said second silicon epitaxial layer,
`providing a fourth silicon semiconductor substrate
`having a third silicon epitaxial layer on one surface
`and a sixth silicon compound dielectric layer on a
`surface of said third epitaxial layer,
`stacking said fourth semiconductor substrate and said
`third epitaxial layer on said second epitaxial layer
`with said ?fth and sixth dielectric layers in contact,
`fusing said ?fth and sixth dielectric layers together,
`removing said fourth substrate by etching thereby
`leaving said third epitaxial layer,
`forming elements of an electrical device in said third
`epitaxial layer using photoresist masking and
`wherein a photomask is optically aligned by look
`ing through said third epitaxial layer to alignment
`marks after fusing said third epitaxial layer to said
`second epitaxial layer,
`providing conductive vias between said second epi
`taxial layer and said third epitaxial layer,
`forming a source and a drain of a ?rst ?eld effect
`transistor in said ?rst epitaxial layer,
`forming a source and a drain of a second ?eld effect
`transistor in said third epitaxial layer, and
`forming a gate electrode in said second epitaxial layer
`for said ?rst and second ?eld effect transistors, said
`?rst and second ?eld effect transistors forming a
`CMOS transistor pair.
`
`25
`
`4-0
`
`70.
`‘
`The n-channel transistor 75 is formed in the ?rst epi
`taxial layer 64, the p-channel transistor 74 is formed in
`the third epitaxial layer 68, and the common gate is
`formed in the second epitaxial layer 66. The metal 55
`via 71 contacts a silicide or polysilicon contact to the
`second epitaxial layer, the metal VCC contact 72
`contacts the third epitaxial layer 68, and the IN metal
`contact 73 contacts the ?rst and third epitaxial layers
`64, 68. Oxide isolation and void isolation is employed as
`described above.
`Considering the advantage of the optical alignment
`by looking through the last applied epitaxial layer, the
`preferred arrangement is to fuse an unprocessed wafer
`to the processed layer on the support wafer. This is
`illustrated for a D ?ip-?op in a three level structure
`shown in the exploded perspective view of FIG. 17.
`The layout of the circuitry of FIG. 17 can be more fully
`appreciated using the symbols for layout planning illus
`trated in FIG. 13, the symbols for a transfer gate as
`illustrated in FIG. 14, the symbols for an inverter illus
`trated in FIG. 15, and the schematic of the flip-flop in
`FIGS. 16A and 16B using the symbols of FIGS. 13-15.
`As noted from the schematics, the ?ip-?op comprises
`four transfer gates and four inverters fabricated from
`CMOS transistor pairs. In the three level layout of FIG.
`17, the ?rst level accommodates the P channel transis
`tors, the second level provides the gates for the transis
`tor pairs, and the top or third level provides the N
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`channel transistors. Interconnect vias are provided as
`indicated by the dots on each level and the lines inter
`connecting the dots. The fusion of the silicon oxide of
`the several layers occurs only where the oxide contacts
`the adjacent layer. Voids are formed elsewhere in the
`layers to provide electrical isolation, as described
`above.
`A multilevel integrated circuit in accordance with
`the invention increases circuit density and facilitates the
`stacked formation of circuit components such as CMOS
`45
`transistor pairs and capacitors. By fusing silicon oxide
`layers on several substrates and then removing all but
`one bulk substrate by chemical etching, the total height
`of the multilevel structure can be limited to the thick
`nesses of the epitaxial layers and the fused silicon oxide
`material along with the one supporting substrate.
`While the invention has been described with refer
`ence to specific embodiments, the description is illustra
`tive of the invention and is not to be construed as limit
`ing the invention. For example, lateral bipolar transis
`tors and circuits can be formed in the layers of the
`structure. Thus, various modi?cations and applications
`may occur to those skilled in the art without departing
`from the true spirit and scope of the invention as de?ned
`by the appended claims.
`What is claimed is:
`1. In the fabrication of multilevel semiconductor inte
`grated circuits, a method of forming devices in multi
`layers of silicon semiconductor material comprising the
`steps of
`providing a ?rst silicon semiconductor substrate hav
`ing a ?rst silicon compound dielectric layer on a
`surface of said substrate,
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`Raytheon2057-0011