United States Patent [19]
`Raschke
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4 815 208
`9
`9
`Mar. 28, 1989
`
`[54] METHOD OF JOINING SUBSTRATES FOR
`
`47902 2/1979 Japan ................................. .. 437/209
`
`PLANAR ELECTRICAL
`
`7677 1/1980 Japan . . . . . . .
`
`. . . . . . . .. 357/80
`
`INTE
`
`NNE
`HYB
`CHONS 0F Rm
`
`32425 2/ 1983 Japan . . . . . . .
`. . . . . .. 437/209
`4351 1/1987 Japan ................................. .. 437/209
`
`HosK 3/30
`
`[56]
`
`Primary Examiner-Carl J. Arbes
`_
`Attorney, Agent, or Firm—Rene E. Grossrnan; James T.
`[75] Inventor' Curt R’ Raschke’ Dallas’ Tex‘
`Comfort; Melvin Sharp
`[73] Assignee: Texas Instruments Incorporated,
`[57]
`ABSTRACT
`Dallas, Tex.
`The disclosure relates to a method of forming a hybrid
`[21] APP!‘ No’: 53’459
`circuit wherein two substrates, preferably though not
`[22] Filed:
`May 22, 1987
`necessarily, of diverse materials, are aligned on and
`[51] Int C14
`were?ag?lplmbylagershofpggmewhicgge
`[521 u.sl.ci.IIIII"""""""'IIIIIIIIIII357832;351/12;
`e portion 0 t e
`se ective y etc a e as to eac ot er.
`357/80; 437/209
`-
`F°Pm°S‘ P°1Ymer layer Whlch '5 “twee? the subsFmes
`[58] Field of Search ............... .. 29/832, 833, 834, 836,
`18 removed and the space therebetween 1s ?lled with an
`29/34O; 357/72, 80; 437/209
`electrically insulating material which adheres to the
`Cl d
`R f
`substrates to form a surface between the substrates
`e el'ellces
`'03
`which is coplanar-with the circuit containing surfaces of
`U_S_ PATENT DOCUMENTS
`357/72 X the substrates. Interconnects are then formed on the
`3466 741 9/1969 wiesner
`electrically insulating surface which extend onto both
`.. 437/209 X
`3,501,832 3/1970 Saburoiwats et a1.
`of the substrates. The remaining polymer layers are
`357/72 X
`3,903,590 9/1975 Yokogawa .......... ..
`removed and the hybrid circuit which has been formed
`4,466,181 8/1984 Takishima ....................... .. 357/80 X
`is then placed on a support to provide rigidity and, if
`necessary, heat sinking properties.
`
`FOREIGN PATENT DOCUMENTS
`
`23565 3/1978 Japan ................................... .. 29/832
`47901 l/1979 Japan ................................. .. 437/209
`
`16 Claims, 1 Drawing Sheet
`
`9 2327
`//7_ 251,2; W /3
`l
`l
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`L
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`Raytheon2056-0001
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`Sony Corp. v. Raytheon Co.
`IPR2015-01201
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`

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`- US. Patent
`
`Mar. 23, 1939
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`L
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`4,815,208
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`Raythe0n205 6-0002
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`Raytheon2056-0002
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`

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`1
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`4,815,208
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`METHOD OF JOINING SUBSTRATES FOR
`PLANAR ELECTRICAL INTERCONNECTIONS OF
`HYBRID CIRCUITS
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`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This application relates to a method of interconnect
`ing the pads of the diverse substrates or chips to form a '
`hybrid circuit.
`2. Brief Description of the Prior Art
`A problem which has limited full exploitation of the
`advantages of hybrid circuits has been that of reliably
`making electrical interconnection between the chips on
`a scale consistent with the scale of circuit integration on
`the chips themselves. A variety of methods exist for
`making planar interconnections on an appropriate scale.
`To use these methods, however, requires an adhesive
`bond between the chips which is uniform and ?at to the
`scale of the interconnection geometry, level with the
`chip surfaces and rigid and adherent over the planned
`temperature use range.
`The ideal circuit will often be a hybrid with, for
`example, one part formed from gallium arsenide and the
`second part formed from lithium niobate, where a cir
`cuit design cannot be optimized on a single substrate.
`When such hybrid circuits are used, it is necessary to
`lithographically interconnect the two different types of
`substrates. The interconnection presents problems of a
`type not encountered in the formation of interconnects
`on a single substrate. The two substrates must be suffi
`ciently close together and suf?ciently coplanar
`whereby standard lithographic techniques can be ap
`plied. The two substrates must be coplanar on the order
`of the line width of the interconnections. Therefore, if
`the interconnection line widths are, for example, seven
`microns, the substrates must be coplanar on the order of
`at least seven microns for the entire length of joint
`therebetween.
`The prior art attempted to solve this problem by
`glueing the two substrates together in advance and then
`polishing down both substrates together including the
`adhesive therebetween whereby, by this polishing ac
`tion, both substrate surfaces and the intervening adhe
`sive are coplanar. The substrates are then operated upon
`45
`individually in standard manner to form the circuits
`therein. This system is economically ‘ineffective, espe
`cially when substrates such as gallium arsenide are in
`volved. This is because gallium arsenide processing is so
`complex and the yield thereof is so low that, statisti
`cally, the likelihood of obtaining a hybrid circuit
`wherein both the gallium arsenide circuit‘and the sec
`ond circuit are simultaneously functioning is very small.
`Accordingly, it is desirable to seek a method for forma
`tion of hybrid circuits wherein the statistical likelihood
`of obtaining such circuits in a completely functional
`manner is substantially increased.
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`SUMMARY OF THE INVENTION
`In accordance .with the present invention, there is
`provided a method of making such hybrid circuits
`wherein the statistical likelihood of success is materially
`improved.
`Brie?y, in accordance with the present invention, the
`desired circuits are initially formed on the surfaces of
`the substrates of both materials of the hybrid circuit.
`The individual circuits are then tested for operability
`individually with the inoperative circuits being dis
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`carded. It is then necessary to interconnect the diverse
`substrates by running leads from the pads of one sub
`strate to the pads of the other. This has caused a prob
`lem in that it is necessary that the circuit containing
`5 surfaces of the two diverse substrates being connected
`as well as the adhesive which holds the substrates to
`gether in close proximity to each other be absolultely
`planar on the order of the width of the photolitho
`graphic interconnect lines formed over the adhesive to
`interconnect the pads of the substrates. This has pres
`ented a major problem which is now solved by the
`present invention.
`Accordingly, a glass slide is provided with markings
`thereon for accurate placement of the substrates. A ?rst
`transparent polymer layer with a thickness of 1 to 10
`microns and preferably 5 microns which adheres well to
`glass is then formed over the glass slide. Preferred poly
`mers for this ?rst layer are polymethylmethacrylate,
`polymethylsiloxane and polyimides of sufficiently low
`viscosity that they can be deposited uniformly to the
`desired thickness. A second transparent polymer layer
`with a thickness of 1 to 10 microns and preferably 5
`microns which adheres to the ?rst polymer layer and is
`moderately cross-linked is then formed over the ?rst
`polymer. The polymers which have the desired proper
`ties for the ?rst layer will generally be used for the
`second layer. In this case the ?rst and second layer are
`deposited as one layer.
`A third polymer layer, which is preferably a photore
`sist or an uncured polyimide, such as PL-lOOO of Hita
`chi, with a thickness of less than 2 microns and prefera
`bly 1 micron is then formed over the second polymer
`layer which adheres to the second polymer layer and is
`etchable with an etchant which does not etch the ?rst or
`second polymer layer. The third polymer layer is either
`suf?ciently thin or sufficiently transparent so that the
`markings on the glass slide are, visible therethrough.
`The substrates or chips with circuits formed on a sur
`face thereof are then placed on the third layer with the
`circuit containing surface contacting the third layer and
`aligned with the markings on the glass slide.
`The third polymer layer is then removed in the re
`gion between the substrates down to the second poly
`mer layer with an etchant selective to the third layer as
`opposed to the second and ?rst layer. The etchants can
`be solvents such as butyl acetate or methyl alcohol or
`can be oxygen gas in an excited state such as formed in
`an RF plasma. A fourth polymer in the form of an ep
`oxy, such as a well known casting compound such as
`Emerson Cumins Stycast 2651-40 which forms a
`smooth surface or cyanoacrylate or methylacrylic ester,
`is then introduced into the region between the sub
`strates and cured. The entire assembly is then soaked in
`a solution which does not attack the fourth layer but
`removes or makes removable the ?rst and second lay
`ers, such as N-butyl acetone, acetone, N-methyl pyrilli
`done, so that the two substrates joined together by the
`fourth layer remain. The circuit containing surfaces of
`the substrates and the intervening adhesive will be es
`sentially coplanar since the glass acts as a planarizing
`surface therefore during fabrication.
`The hybrid circuit thus formed is then placed on a
`metal support, such as brass, which also provides heat
`sinking properties thereto. The interconnect lines are
`then formed between the two substrates over the fourth
`layer, in standard manner using standard lithographic
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`Raytheon2056-0003
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`BRIEF DESCRIPTION OF THE DRAWINGS
`FIGS. 1 to 4 are schematic drawings which depict
`the result obtained after different manufacturing steps in
`the process have been performed for formation of the
`hybrid circuit in accordance with the present invention;
`and
`FIG. 5 is a top view of FIG. 4.
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`tively simple processing steps and which utilizes all
`techniques. The device is then packaged in standard
`operable chips.
`manner.
`Though the invention has bee described with respect
`to active semiconductor substrates it should be under
`stood that other types of substrates, both active and
`passive, can be substituted for one or both of the sub
`strates herein.
`Though the invention has been described with re
`spect to a speci?c preferred embodiment thereof, many
`variations and modi?cations will immediately become
`apparent to those skilled in the art. It is therefore the
`intention that the appended claims be interpreted as
`broadly as possible in view of the prior art to include all
`such variations and modi?cations.
`I claim:
`1. A method of forming an electrical circuit compris
`ing the steps of:
`(a) providing a planar support;
`(b) forming a layer of an adhesive on said support;
`(c) providing ?rst and second substrates, each having
`a circuit formed on a surface thereof;
`(d) securing the circuit containing surface of each of
`said substrates to said adhesive layer;
`(e) removing the portion of said adhesive layer be
`tween said substrates;
`(f) ?lling the region between said substrates with a
`substrate adhering material to form an insulating
`surface between said circuit containing surfaces
`coplanar with said surfaces; and
`(g) forming interconnect lines on said insulating sur
`face extending from said ?rst to said second sub
`strate.
`2. The method of claim 1 wherein said substrates are
`formed of different materials.
`3. The method of claim 1 further including providing
`alignment marks on said support and, in step (d) further
`aligning said substrates with said alignment marks.
`4. The method of claim 2 further including providing
`alignment marks on said support and, in step (d) further
`aligning said substrates with said alignment marks.
`5. The method of claim 1 wherein step (b) includes,
`prior to formation of said adhesive layer, forming a
`transparent layer of a material adherable to said support
`and resistant to etching by an etchant for said adhesive
`layer.
`6. The method of claim 2 wherein step (b) includes,
`prior to formation of said adhesive layer, forming a
`transparent layer of a material adherable to said support
`and resistant to etching by an etchant for said adhesive
`layer.
`7. The method of claim 3 wherein step (b) includes,
`prior to formation of said adhesive layer, forming a
`transparent layer of a material adherable to said support
`and resistant to etching by an etchant for said adhesive
`layer.
`8. The method of claim 4 wherein step (b) includes,
`prior to formation of said adhesive layer, forming a
`transparent layer of a material adherable to said support
`and resistant to etching by an etchant for said adhesive
`layer.
`9. The method of claim 5 further including, before
`step (g), removing said transparent layer of a material
`adherable to said support.
`10. The method of claim 6 further including, before
`step (g), removing said transparent layer of a material
`adherable to said support.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`Referring now to the FIGURES and speci?cally to
`FIG. 1, there is shown a transparent glass plate 1 having
`markings 3 thereon for later alignment of chips or sub
`strates. The glass plate de?nes the planar surface which
`the remainder of the process will be referenced against.
`A ?rst transparent polymer layer 5 of polymethylsilox
`ane having a thickness of 5 microns is then deposited
`over the plate 1 and a second transparent polymer layer
`7 of polymethylmethacrylate having a thickness of 5
`microns is deposited over the layer 5. A third thin layer
`9 of a photoresist AZ1350B of American Hoechst hav
`ing a thickness of one micron, which acts as a tempo
`rary glue for the chips to be placed on the plate 1, is
`then deposited over the layer 7 and the substrates 11 and
`13 are aligned on the layer 9 in locations determined by
`the alignment markings 3 on the glass plate 1 which are
`visible through each of the layers 5, 7 and 9. At this time
`in the procedure, the system will appear as shown in
`FIG. 1.
`The entire device of FIG. 1 is then masked to permit
`etching of the portion of the layer 9 which exists in the
`region 15 between the substrates 11 and 13. The region
`15 is then etched away using butyl acetate followed by
`an oxygen plasma to remove any residues to provide the
`arrangement as shown in FIG. 2. The space 17 which
`now exists between the substrates 11 and 13 is then ?lled
`with an epoxy 19, such as the casting compound Emer
`40
`son and Cuming Stycast 2651-40 which forms a smooth
`surface and degassed to provide the arrangement as
`shown in FIG. 3 with the epoxy layer 19. The epoxy
`layer 19 secures the substrates 11 and 13 thereto and
`forms the surface over which the interconnects will
`later be formed to form the structure as shown in FIGS.
`4 and 5.
`The structure as shown in FIG. 3 is then treated with
`acetone to dissolve the layers 5 and 7 and the remnant of
`layer 9 to provide the substrates 11 and 13 with circuits
`50
`formed in the downward facing faces thereof, the sub
`strates being secured together by the epoxy 19 which
`provides a surface coplanar with the circuit containing
`surfaces of the substrates. This arrangement is glued
`with an epoxy to a brass support surface 21 which also
`acts as a heat sink for the hybrid circuit being formed as
`shown in FIG. 4. It can be seen that the circuit carrying
`surface of each of the substrates 11 and 13 is facing
`away from the support 21. This structure is then pat
`terned with a photoresist in standard manner and inter
`connect lines 23 are formed in standard manner which
`extend from pads 25 on substrate 11 to pads 27 on sub
`strate 13 as shown in FIGS. 4 and 5 to form the com
`pleted hybrid circuit. The hybrid circuit can then be
`packaged in standard manner to provide the completed
`usable circuit.
`It can be seen that there has been provided a method
`for making a hybrid circuit which utilizes few and rela
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`5
`11. The method of claim 7 further including, before
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`4, 8 15,208
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`13'. The method of clam 9 further mcludmg the“
`securing the substrates to a support.
`14. The method of claim 10 further including then
`securing the substrates to a support.
`15. The method of claim 11 further including then
`securing the substrates to a support.
`16. The method of claim 12 further including then
`securing the substrates to a support.
`it
`* * t *
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`step (g), removing said transparent layer of a material
`adherable to said support.
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`12. The method of claim 8 further including, before
`step (g), removing said transparent layer of a material
`adherable to said support.
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