United States Patent [191
`Yasumoto et a1.
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,612,083
`Sep. 16, 1986
`
`[54] PROCESS OF FABRICATING
`THREE-DIMENSIONAL SEMICONDUCTOR
`DEVICE
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`[75] Inventors:
`
`Masaaki Yasumoto; Hiroshi Hayama;
`Tadayoshi Enomoto, all of Tokyo,
`Japan
`
`[73] Assignee: NEC Corporation, Tokyo, Japan
`
`[21] Appl. No.: 755,987
`
`[22] Filed:
`
`Jul. 17, 1985
`
`Foreign Application Priority Data
`[30]
`Jul. 20, 1984 [JP]
`Japan .............................. .. 59-150598
`
`[51] Int. Cl.4 ...................... .. B44C l/22; B29C 17/08;
`C09J 5/02; C23F l/02
`[52] US. Cl. ................................. .. 156/633; 29/576 J;
`29/591; 148/15; 156/634; 156/643; 156/653;
`156/656; 156/657; 156/659.1; 156/668;
`156/307.3; 357/71; 427/89; 430/313; 430/314;
`430/317; 430/318
`[58] Field of Search ............. .. 156/633, 634, 643, 644,
`156/646, 653, 656, 657, 659.1, 668, 307.3, 313;
`430/313, 314, 315, 317, 318; 427/38, 39, 88-91;
`357/65, 71; 29/571, 576 R, 576 W, 576 J, 578,
`588, 591; 148/15, 187
`
`4,400,868 8/1983 Antypas et al. .................. .. 29/576 J
`156/307.3
`4,552,607 11/1985 Frey .................. ..
`Primary Examiner-William A. Powell
`Attorney, Agent, or Firm-Sughrue, Mion, Zinn,
`Macpeak, and Seas
`ABSTRACT
`[57]
`A process of fabricating a three-dimensional semicon
`ductor device, comprising the steps of preparing at least
`two multilayer structures each including at least one
`semiconductor element and a conductor connected at
`one end to the semiconductor element and having at the
`other end an exposed surface, at least one of the multi
`layer structures further including a thermally fusible
`insulating adhesive layer having a surface coplanar with
`the exposed surface of the conductor, positioning the
`multilayer structures so that the exposed surfaces of the
`respective conductors of the multilayer structures are
`spaced apart from and aligned with each other, moving
`at least one of the multilayer structures with respect to
`the other until the exposed surfaces of the conductors of
`the multilayer structures contact each other, and heat
`ing the multilayer structures for causing the insulating
`adhesive layer of at least one of the multilayer struc
`tures to thermally fuse to the other multilayer structure
`with the semiconductor elements electrically connected
`together.
`
`15 Claims, 8 Drawing Figures
`
`(f)
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`Raytheon2053-0001
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`Sony Corp. v. Raytheon Co.
`IPR2015-01201
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`

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`1
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`4,612,083
`
`PROCESS OF FABRICATING
`THREE-DIMENSIONAL SEMICONDUCTOR
`DEVICE
`
`FIELD OF THE INVENTION
`The present invention relates to a process of fabricat
`ing a three-dimensional semiconductor device and,
`more particularly, to a process of forming a three-di
`mensional semiconductor device by ?rst preparing two
`or more multilayer structures each having at least one
`semiconductor element formed therein and thereafter
`integrally uniting the multilayer structures together
`while providing electrical connections between the
`semiconductor elements in the multilayer structures.
`
`2
`ties are encountered in parallelizing the process steps
`and accordingly an objectionably prolonged period of
`time is required for the fabrication of a three-dimen
`sional semiconductor device. It may also be pointed out
`that the semiconductor elements which have been
`formed on the substrate are subjected to heat during the
`step of crystallizing a polysilicon layer and would cause
`changes in the design parameters of the elements.
`Where, furthermore, a defective semiconductor ele
`ment happens to be produced in any of the functional
`layers being formed one after another, such a semicon
`ductor element could not be found out pending the
`post-fabrication inspection. This would also lead to a
`decrease in the yield of fabrication of a three-dimen
`sional semiconductor device. Another problem is that
`the prior-art method is not fully acceptable for the pro
`duction of semiconductor devices on a quantity basis
`since techniques making it possible to implement SOI
`structures with suf?cient areas are indispensable for this
`purpose.
`Another known method of fabricating a three-dimen
`sional semiconductor device is proposed by R. D. Etch
`ells et al and is described in the article “Development of
`a three-dimensional circuit integration technology and
`computer architecture”, SPIE, vol. 282, Technical Is
`sues in Focal Plane Development, pp. 64-74, 1981. This
`article focuses on the techniques of forming “feed
`throughs” in each of stacked silicon chips and the tech
`niques of forming “microinterconnects” to carry signals
`through the silicon chips. The feedthroughs are pro
`duced by the deposition of an array of aluminum dots
`on the surface of a silicon chip followed by the ther
`momigration of liquid droplets of aluminum through
`the chip. On the other hand, the formation of the mi
`crointerconnects starts with the deposition of a 1 mil
`thick spacer-bump on the surface of a chip. A thin ?lm
`of solder alloy connected to a circuit connection is
`deposited on this spacer bump and thereafter the spacer
`bump is etched out to allow the solder alloy ?lm to ?oat
`as a free-standing structure over the surface of the chip.
`The solder alloy, or microspring, on one silicon chip
`extends in crossing relationship to the microspring on
`the adjacent chip. The stacked silicon chips are then
`lightly pressed upon to cause the microsprings on the
`adjacent silicon chips to plastically deform against each
`other, whereupon the microsprings thus brought into
`contact with each other between every two of the
`stacked silicon chips are thermally fused together.
`In connection with this prior-art method of fabricat
`ing a three-dimensional semiconductor device, there is
`further an article published by J. Y. M. Lee et al in
`“Aluminum Thermomigration Technology for 3
`Dimensional Integrated Circuits”, IEDM Technical
`Digests, 1983, pp. 66. This article teaches formation of
`an integrated circuit with CMOS FETs on a wafer
`which has been formed with feedthroughs by the ther
`momigration process, followed by formation of alumi
`num pads on the reverse surface of the wafer. No partic
`ulars regarding the geometry, particularly the length
`wise measurements of the microinterconnects are clari
`?ed in the article although the feedthroughs are stated
`to measure 4 mils in diameter. The illustrations appear
`ing in the article according to R. D. Etchells et a1 how
`ever suggest that the lengths of the interconnects are
`approximately 3.3 times the diameters of the feed
`throughs. Such lengths of the interconnects must be
`required to avoid break of the interconnects when the
`
`25
`
`30
`
`BACKGROUND OF THE INVENTION
`Two-dimensional semiconductor devices presently in
`production on a commercial basis include active and
`passive elements formed on one major surface of a sub
`strate. In this instance, the integration density of the
`semiconductor elements formed on a single substrate
`can be increased by reducing the design rules and the
`sizes of the semiconductor elements. Excessive reduc
`tion of the design rules would however raise another
`problem in the fabrication process of semiconductor
`devices and would thus invite substantial reduction in
`the yield in the production of the devices. This means
`that reduction of the design rules is restricted from both
`technological and commercial points of view.
`A three-dimensional semiconductor device has there
`fore been proposed with a view to achieving a drasti
`cally increased degree of integration density. Some
`methods are presently available for the fabrication of
`such a three-dimensional semiconductor device.
`35
`One of these prior-art methods is proposed by S.
`Kawamura and disclosed in International Electron De
`vices Meeting (IEDM) Technical Digests, 1983, pp.
`364. In Kawamura’s method, active and passive semi
`conductor elements are ?rst formed on and/or in a
`major surface of a substrate and an insulating layer is
`thereafter deposited on the surface of the substrate to
`cover the individual semiconductor elements. In the
`description that follows, the layer which is thus formed
`on the major surface of a substrate and which contains
`active and/or passive semiconductor elements formed
`on and/or in the substrate and electrically isolated from
`other semiconductor elements will be referred to as
`functional layer. A polysilicon layer is then deposited
`on the insulating layer formed on the functional layer
`and is irradiated with a laser beam or an electron beam
`or heated by a strip heater so that the polysilicon is
`crystallized to provide a silicon-on-insulator (SOI)
`structure. In this crystallized polysilicon layer are then
`formed active and passive semiconductor elements to
`form a second functional layer, followed by interlayer
`wiring between the semiconductor elements in the ?rst
`and second functional layers.‘ These steps are repeated
`until a three-dimensional semiconductor device includ
`ing two or more functional layers electrically isolated
`from one another results.
`Thus, the method of Kawamura is, in essence, such
`that a plurality of functional layers are stacked one upon
`another by repeating the step of crystallizing a polysili
`con layer, the step of forming semiconductor elements
`65
`on the crystallized polysilicon layer and the step of
`covering these semiconductor elements with an insulat
`ing layer. Such a method has drawbacks in that dif?cul
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`45
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`interconnects are caused to plastically deform distances
`approximating the 1 mil spacing between the surface of
`the chip and the interconnects ?oating over the chip
`surface. Where such long interconnects are arranged in
`crossing relationship between the adjacent silicon chips,
`considerably large proportions of the total areas of the
`chips are used for the coupling of the interconnects.
`This imposes restriction on the number of the intercon
`nects available on each chip and results in reduction in
`the area of the chip available for the formation of semi
`conductor elements.
`It is, accordingly, an important object of the present
`invention to provide a process of fabricating a three-di
`mensional semiconductor device with a drastically in
`creased integration density.
`It is another important object of the present invention
`to provide a process of fabricating a three-dimensional
`semiconductor device which can be manufactured by
`steps some of which can be parallelized to permit reduc
`tion of the time required for the production of the three
`dimensional semiconductor device.
`It is still another important object of the present in
`vention to provide a process of fabricating a three-di
`mensional semiconductor device wherein each of the
`semiconductor elements formed during the process can
`be inspected for proper functioning at any stage of the
`process.
`It is still another important object of the present in
`vention to provide a process of fabricating a three-di
`mensional semiconductor device composed of multi
`layer structural portions resulting from two or more
`multilayer structures which can be integrally combined
`together by heating at a relatively low temperature
`which will not affect the performance characteristics or
`design parameters of each of the semiconductor ele
`ments in the multilayer structures.
`It is still another important object of the present in
`vention to provide a process of fabricating a three-di
`mensional semiconductor device composed of multi
`layer structural portions resulting from two or more
`40
`multilayer structures which can be integrally combined
`together with use of minimum areas of the multilayer
`structures and without sacri?cing the number of the
`semiconductor elements to be formed in each of the
`multilayer structures even when an increased number of
`multilayer structures are to be combined together.
`Yet, it is another important object of the present
`invention to provide a process of fabricating a three-di
`mensional semiconductor device economically and
`with a satisfactory fabrication yield.
`
`25
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`50
`
`4
`ing at least one of the semiconductor structures with
`respect to the other until the exposed surface portions of
`the respective conductors of the semiconductor struc
`tures are brought into contact with each other, and (4)
`heating the semiconductor structures, preferably, at a
`temperature which will substantially not affect the per
`formance characteristics of the semiconductor element
`in each of the semiconductor structures, for causing the
`insulating adhesive layer of at least one of the semicon
`ductor structures to thermally fuse to the other semi
`conductor structure with the semiconductor elements
`electrically connected together.
`
`0
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The features and advantages of a process according
`to the present invention will be more clearly appreci
`ated from the following description taken in conjunc
`tion with the accompanying drawings in which:
`FIG. 1 consists in sections (a) to (0 which are frag
`mentary cross sectional views showing a preferred ex
`ample of a process according to the present invention;
`FIG. 2 is a fragmentary cross sectional view showing
`an example of a three-dimensional semiconductor de
`vice which can be fabricated by the process represented
`by sections (a) to (f) of FIG. 1;
`FIG. 3 is a fragmentary cross sectional view showing
`another example of a three-dimensional semiconductor
`device which can be fabricated by the process repre
`sented by sections (a) to (f) of FIG. 1;
`FIG. 4 is a perspective view view showing a pre
`ferred example of a practical application of a three-di
`mensional semiconductor device fabricated in accor
`dance with the present invention;
`FIG. 5 is a perspective view showing another pre
`ferred example of a practical application of a three-di
`mensional semiconductor device fabricated in accor
`dance with the present invention;
`FIG. 6 consists in sections (a) to (g) which are frag
`mentary cross sectional views showing another pre
`ferred example of a process according to the present
`invention;
`FIG. 7 is a view consisting of in sections (a) to (e)
`which are fragmentary cross sectional views showing
`still another preferred example of a process according
`to the present invention; and
`FIG. 8 is a fragmentary cross sectional view showing
`an example of a three-dimensional semiconductor de
`vice which can be fabricated by the process represented
`by sections (a) to (e) of FIG. 7.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`A process according to the present invention will be
`hereinafter described ?rst with reference to sections (a)
`to (f) of FIG. 1.
`In section (a) of FIG. 1 is shown a multilayer struc
`ture 10 resulting from the ?rst step of the process ac
`cording to the present invention. The multilayer struc
`ture 10 comprises a substrate 12, an interlevel functional
`layer 14 overlying the substrate, and an insulating layer
`16 of, for example, silicon dioxide deposited on the
`functional layer 14, the functional layer 14 having vari
`ous semiconductor elements formed therein though not
`shown in FIG. 1. The substrate 12 may be formed of a
`semiconductor such as monocrystalline silicon or sili
`con dioxide or an insulator such as highly resistive gal
`lium arsenide or sapphire. The substrate 12 of any of
`these materials is fabricated with use of any combina
`
`SUMMARY OF THE INVENTION
`In accordance with the present invention, there is
`provided a process of fabricating a three-dimensional
`semiconductor device, comprising the steps of (1) pre
`paring at least two multilayer or otherwise con?gured
`semiconductor structures each including at least one
`semiconductor element and a conductor electrically
`connected at one end to the semiconductor element and
`having at the other end thereof an exposed surface por
`tion, at least one of the semiconductor structures further
`including a thermally fusible insulating adhesive layer
`having a surface substantially coplanar with the ex
`posed surface of the conductor, (2) positioning the semi
`conductor structures with respect to each other so that
`the exposed surface portions of the respective conduc
`tors of the semiconductor structures are spaced apart
`from and substantially aligned with each other, (3) mov
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`5
`tion of the known semiconductor process technologies
`such as, for example, the thermal oxidation, diffusion,
`ion implantation, epitaxial growing, chemical or physi
`cal vapor deposition and photolithographic techniques
`used for the fabrication of two-dimensional integrated
`circuit devices. The interlevel functional layer 14 in
`cludes various active and/or passive semiconductor
`elements formed in and/or on the substrate 12 and elec
`trically isolated from one another, though not shown in
`the drawings. These semiconductor elements may in
`clude not only such typical components of an electronic
`circuit as bipolar transistors, ?eld-effect transistors
`(FETs), capacitors and resistors but also transducer
`elements such as optoelectric transducers, magnetoelec
`tric transducers and photoelectromagnetic (PEM)
`transducers depending upon the application of the chip
`to result from the substrate. The material to form the
`substrate 12 is selected depending on the types and the
`desired performance characteristics of such semicon
`ductor elements. Though not shown in FIG. 1, these
`semiconductor elements are electrically connected to
`gether by internal conductor layers 18 embedded in the
`insulating layer 16 to form a certain circuit. In brief, the
`multilayer structure 10 is fabricated by the use of a
`material and a process technology selected to suit thev
`25
`speci?c con?guration and application of the circuit to
`be formed therein and depending upon the physical
`parameters which the ?nal semiconductor chip are to
`provide for the intended application of the device.
`The multilayer structure 10 thus fabricated to the
`con?guration shown in section (a) of FIG. 1 is pro
`cessed, typically using photolithographic techniques, to
`form openings in the insulating layer 16 to have the
`individual internal conductor layers 18 exposed through
`these openings. For this purpose, a photoresist is applied
`to the surface of the insulating layer 16 and, upon appro
`priate preliminary treatment, a patterned photomask is
`placed on the photoresist coating, which is then selec
`tively exposed, developed and etched as is customary.
`The exposed regions of the insulating layer 16 are thus
`removed from the multilayer structure 10 to form open
`ings arranged in a pattern following the pattern on the
`photomask used. As the etchant for the etching of the
`insulating layer may be used hydro?uoric acid (HF)
`where the insulating layer 16 consists of silicon dioxide.
`Appropriate electrically conductive metal such as typi
`cally gold is deposited on the surface of the insulating
`layer 16 to a thickness greater than the thickness of the
`insulating layer 16 with the ?lm of the photoresist left
`on the insulating layer 16. Thus, the layer of gold in part
`covers the residual photoresist coating on the insulating
`layer 16 and in part ?lls the openings in the insulating
`layer 16. The layer of gold is then selectively etched to
`be removed or “lifted off” together with the photoresist
`coating remaining on the insulating layer 16 from its
`areas coextensive with the initial openings in the insulat
`ing layer 16. The layer of gold is in this fashion left in
`the initial openings in the insulating layer 16 and forms
`in each of the openings a bump slightly protruding from
`the surface of the insulating layer 16 as indicated at 20 in
`section (b) of FIG. 1. The metal bumps 20 thus formed
`have the thickness of about 1.5 micron from the surface
`of the interlevel functional layer 14, and of about 0.5
`micron from the surface of the insulating layer 16 by
`way of example.
`An appropriate dielectric polymeric adhesive is ap
`plied to the surface of the insulating layer 16 of the
`multilayer structure 10 now having the con?guration
`
`6
`shown in section (b) of FIG. 1. For this purpose, the
`dielectric polymeric adhesive, which may for example
`be a polyimide resin, is applied uniformly to the insulat
`ing layer 16 with the multilayer structure 10 ?xedly
`supported on a spinner rotating at a high speed. A pla
`nar, insulating adhesive resin layer 22, which may be
`about 2.5 microns thick, is thus formed on the surface of
`the insulating layer 16 and the top faces of the individ
`ual metal bumps 20 as shown in section (0) of FIG. 1.
`The insulating adhesive resin layer 22 can be formed to
`a desired thickness accurately and uniformly over the
`area of the insulating layer 16 by appropriately selecting
`the speed of rotation and the period of time used for the
`spin coating operation. The spin coating process is thus
`adapted to form a suf?ciently uniplanar adhesive coat
`ing on the insulating layer 16 without respect to the
`presence of the metal bumps 20 protruding from the
`surface of the layer 16' The insulating adhesive resin
`layer 22 is thereafter etched in, for example, the atmo
`sphere of oxygen plasma to a depth which is uniform
`throughout its area to allow the individual metal bumps
`20 to be exposed at a plane substantially ?ush with the
`surface of the residual adhesive resin layer 22 as shown
`in section (d) of FIG. 1.
`The successive steps of forming the multilayer struc
`ture 10 having the con?guration shown in section (d) of
`FIG. 1, viz., the step of forming the interlevel func
`tional layer 14 on the substrate 12, the step of depositing
`the insulating layer on the functional layer 14, the step
`of forming the metal bumps 20, the step of forming the
`insulating adhesive resin layer 22, and the step of par
`tially removing the adhesive resin layer 22 as above
`described may vary from one multilayer structure to
`another or may be common to a plurality of multilayer
`structures. In whichsoever case, two or even more of
`the multilayer structures having either similar or differ
`ent con?gurations generally represented by the con?gu
`ration shown in section (d) of FIG. 1 are to be used in
`the process steps subsequent to the step which has re
`sulted in the con?guration illustrated in section (d) of
`FIG. 1.
`In section (e) of FIG. 1, these multilayer structures
`are shown consisting of two, ?rst and second, multi
`layer structures 10 and 10’. These ?rst and second multi
`layer structures 10 and 10 are assumed, by way of exam
`ple, as having similar con?gurations each represented
`by the con?guration ‘of the multilayer structure 10 illus
`trated in section (d) of FIG. 1. The components of each
`of the ?rst and second multilayer structures 10 and 10'
`are thus assumed to be respectively similar to those of
`the multilayer structure 10 shown in section (d) of FIG.
`1 and, for this reason, the components of the second
`multilayer structure 10' are designated by numerals,
`each with a prime, identical with those of the respec
`tively corresponding components of the ?rst multilayer
`structure 10 and accordingly of the multilayer structure
`shown in section (d) of FIG. 1.
`The ?rst and second multilayer structures 10 and 10’
`are ?xedly held in position on a pair of stages (not
`shown), respectively, of an aligner/ welder system. One
`of these stages of the aligner/welder system is movable
`relative to the other in three perpendicularly transverse
`directions so that the two multilayer structures 10 and
`10’ carried on the stages are positioned with respect to
`each other with the metal bumps 20 in the ?rst multi
`layer structure 10 respectively aligned with the metal
`bumps 20' in the second multilayer structure 10’ using
`an off-axis alignment technique. The off-axis alignment
`
`45
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`50
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`55
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`65
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`Raytheon2053-0014
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`

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`4,612,083
`7
`8
`method is implemented typically in the optical system
`insulating layer 28 of silicon dioxide overlying the sub
`of a de-magnifying projection exposure equipment and
`strate 26. The insulating layer 28 has provided therein a
`is per se well known in the art. Each of the stages carry
`silicon layer in which are formed a source region 30, a
`ing the ?rst and second multilayer structures 10 and 10’
`drain region 32 laterally spaced apart from the source
`is moved until a predetermined location of the stage is
`region 30, and a channel region 34 intervening between
`brought into registry with each of the two alignment
`the source and drain regions 30 and 32. A diffused sili
`marks located at a predetermined distance from each
`con gate 36 is vertically spaced apart from the channel
`other in the aligner/welder system. Thereupon, one of
`region 34 across a gate insulator. These source region
`the two stages is moved over the predetermined dis
`30, drain region 32, channel region 34, silicon gate 36
`tance with respect to the other stage so that the former
`and gate insulator construct one of a plurality of thin
`is positioned immediately below the latter. The two
`?lm transistors, the particular one being indicated at 38.
`stages are in this manner moved to positions in which
`The source region 30 and the drain region 32 are held in
`the metal bumps 20 in the ?rst multilayer structure 10
`contact with metal conductor layers 40 and 42, respec
`are respectively held in alignment and contact with the
`tively, received in the insulating layer 28. These metal
`metal bumps 20' in- the second multilayer structure 10’.
`conductor layers 40 and 42 and the transistor 38 are
`Experiments have revealed that, with a presently avail
`associated with various active and/or passive elements
`able alignment technique, layers each having ?fty thou
`also provided in the interlevel insulating layer 28 and
`sand metal bumps each of which measures 10 square
`constitute in combination with these active and/0r pas
`microns can be united together with the metal bumps of
`sive elements a desired semiconductor integrated cir
`one layer correctly aligned with those of the other.
`cuit. Thus, the insulating layer 28 having the transistor
`20
`The ?rst and second multilayer structures 10 and 10’
`38 formed therein corresponds to each of the interlevel
`are then heated to cause fusion between the respective
`functional layers 14 and 14’ in the multilayer structure
`insulating adhesive resin layers 22 and 22’ of the struc
`shown in section (0 of FIG. 1. On this interlevel insulat
`tures 10 and 10’. Where the insulating adhesive resin
`ing layer 28 is formed a insulating layer 44 of silicon
`layer of each of the multilayer structures 10 and 10’ is
`dioxide which has the thin-?lm transistor 38 and the
`formed of a polyimide resin as previously noted, the
`metal conductor layers 40 and 42 embedded therein so
`multilayer structures 10 and 10 may be heated at a tem~
`that the diffused gate region 36 of the transistor 38 are
`perature ranging from about 250° C. to about 400° C.
`isolated from the metal conductor layers 40 and 42 and
`for about 20 minutes to about 60 minutes. When the
`the other regions of the transistor 38. On the surface of
`insulating adhesive resin layers 22 and 22’ thus fused
`the insulating layer 44, in turn, is formed a spin-coated
`together are thereafter allowed to cool and solidify, the
`insulating adhesive resin layer 46 through which a metal
`two multilayer structures 10 and 10’ are united together
`bump 48 extends from the metal conductor layer 42 for
`into a unitary multilayer structure as shown in section
`the drain region 32 of the transistor 38 to a plane sub
`(f) of FIG. 1. In this unitary multilayer structure 10/10',
`stantially ?ush with the surface of the adhesive resin
`the active and/ or passive elements forming part of the
`layer 46 as shown.
`interlevel functional layer 14 of the original ?rst multi
`The second multilayer structural portion 24’ consists
`layer structure 10 are electrically connected to those in
`of components which are respectively similar to these
`the functional layer 14’ of the original second multilayer
`components of the ?rst multilayer structural portion 24
`structure 10’ through the metal bumps 20 of the former
`and which are thus designated by numerals, each with a
`~multilayer structure and the metal bumps 20' of the
`prime, identical with those of the corresponding com
`latter as will be seen from section (f) of FIG. 1. If de
`ponents of the ?rst multilayer structural portion 24. The
`sired, the unitary multilayer structure 10/10’ may be
`respective insulating adhesive resin layers 46 and 46’ of
`pressed upon in the direction of thickness so that the
`the ?rst and second multilayer structural portions 24
`multilayer structural portions resulting from the multi
`and 24’ are fusion bonded together so that all the pairs
`layer structures 10 and 10’, respectively, are forced
`of corresponding components of the multilayer struc
`against each other and as a consequence each of the
`tural portions 24 and 24' are located symmetrically with
`metal bumps 20 and 20’ in the multilayer structural
`respect to the interface between the insulating adhesive
`portions is prestressed. When the multilayer structure
`resin layers 46 and 46' of the multilayer structural por
`10/10’ is heated thereafter, each of the prestressed metal
`tions 24 and 24' with the metal bumps 48 and 48’ aligned
`bumps 20 and 20’ is caused to diffuse and alloy into the
`together. The metal bumps 48 and 48’ of the multilayer
`associated metal bump with a consequent decrease in
`structural portions 24 and 24’ are held in contact each at
`the contact resistance between every associated two of
`one end with the metal conductor layers 48 and 48’,
`the metal bumps 20 and 20', let alone the enhanced
`respectively, and are connected together at the other
`cohesion between the insulating adhesive layers 22 and
`ends thereof, thereby establishing electrical connection
`22’.
`between the respective drain regions 32 and 32’ of the
`FIG. 2 of the drawings shows the con?guration of an
`multilayer structural portions 24 and 24’.
`example of the three-dimensional semiconductor de
`FIG. 3 of the drawings shows the con?guration of
`vices which can be fabricated by the use of the process
`another example of the three-dimensional semiconduc
`described above. As shown, the semiconductor device
`tor devices which can be fabricated by the process
`comprises two, ?rst and second, multilayer structural
`described with reference to sections (a) to (t) of FIG. 1.
`portions 24 and 24’ resulting from multilayer structures
`As shown, the semiconductor device comprises two
`similar to the ?rst and second multilayer structures 10
`multilayer structu