Nov. 30, 1971
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`Filed Oct. 22, 1969
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`3,623,219
`A_ |_ STOLLER ETAL
`METHOD FOR ISOLATING SEMICONDUCTOR DEVICES
`FROM A WAFER OF SEMICONDUCTING MATERIAL
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`Arthur I. Stoller and
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`www@
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`ATTORNEY
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`Raytheon2049-0001
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`Sony Corp. v. Raytheon Co.
`IPR2015-01201
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`

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`NOV. 30, 1971
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`Filed Oct. 22, 1969
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`3,623,219
`A. |. STQLLER EVAL
`METHOD FOR ISOLATING SEMICONDUCTOR Dmvlcl-:s
`FROM A WAFER OF SEMICONDUCTING MATERIAL
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`Raytheon2049-0002
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`

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`United States Patent O
`ICC
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`1
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`3,623,219
`Patented Nov. 30, 1971
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`1
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`3,623,219
`METHOD FOR ISOLATING SEMICONDUCTOR
`DEVICES FROM A WAFER 0F SEMICON
`DUCTING MATERIAL
`Arthur Irwin Stoller, North Brunswick, and William
`Henry Schilp, Flemington, NJ., assignors to RCA Cor
`poration
`Filed Oct. 22, 1969, Ser. No. 868,470
`Int. Cl. B01j 17/00; H011 5/00
`U.S. Cl. 29-580
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`8 Claims
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`sirable to employ a slightly deformable material for the
`handle body to avoid the need for extremely .ñat surfaces.
`SUMMARY OF THE INVENTION
`The present invention comprises a method for forming
`a body of electrically isolated semiconductor devices from
`a semiconducting wafer having two opposed major sur
`faces, in which the devices are initially formed adjacent
`a first one of the surfaces. A protective layer of a sub
`stance A‘which is resistant to an etchant for a particular
`refractory glass, is deposited on the first surface. A handle
`body of the refractory glass is sealed to the protective
`layer and portions of the wafer between adjacent devices
`is removed, so as to provide an array of electrically
`isolated devices. An insulating body of softened glass
`which is less refractory than the glass of the handle body
`is pressed into the isolated array, and between adjacent
`devices. The handle body is then removed by using an
`etchant which does not attack the protective layer.
`In the drawings:
`FIGS. 1 to 8 are representative steps in the preferred
`embodiment of the method of the present invention.
`PIG. 9 illustrates alternative steps in the method of the
`present invention.
`DETAILED DESCRIPTION
`A preferred embodiment of the present method will
`be described with reference to FIGS. 1-8.
`A crystalline semiconductor wafer 10 having two op
`posed major surfaces 12 and 14, is first provided (FIG.
`1). The wafer 10l may be either of P or N type con
`ductivity; however, for purposes of illustration, an N
`type wafer is described. As shown in FIG. 2, a plurality
`of discrete semiconductor devices are formed in the
`wafer 10 through the surface 12 by standard planar
`techniques well known in the art. The devices may com
`prise transistors, diodes, resistors, capacitors, or any
`combination thereof. By way of example, three P-N diodes
`1‘6-18 are shown in FIG. 2, each diode comprising a P
`type region 15 disposed in an adjacent portion of the
`N type wafer 10, with a P-N junction therebetween. Dur
`ing P region diffusion, an insulating coating 20 is left
`deposited on the upper surface 12. Alternatively, this
`coating may be stripped from the surface 12, and a more
`uniform insulating coating 20 may be deposited on the
`surface by any one of a Variety of techniques known
`in the art.
`Next, a protective layer |22 of a substance which is
`resistant to an etchant fo-r a particular refractory glass,
`is deposited on the insulating coating 20- (FIG. 3). There
`after, a handle body 24 (FIG. 4) of the particular re»
`fractor glass is sealed to the protective layer 22; prefer~
`ably, the refractory glass has a thermal expansion co
`efiicient closely matching that of the material of the semi
`conducting wafer 10, and has a softening temperature
`below 1100° C. The handle body 2.4 is sealed to the
`passivating layer 22 by heating the wafer 10` and the glass
`handle body 24» to` a temperature just above the soften
`ing point of the glass, and pressing the body |24 and wafer
`10 together with a pressure of between 50 and 1000
`p.s.i. for about 5 minutes.
`lPortions of the wafer 10 between adjacent diodes 16
`'118 are then removed to provide an array of electrically
`isolated devices. This is accomplished 'by first thinning
`the wafer 10` by abrasion or etching of the second sur
`face 14. An insulating layer is then deposited on the
`newly formed surface of the thinned wafer 10‘. The layer
`is treated with a photoresist, masked corresponding to the
`desired isolation, and the photoresist is exposed and
`developed to leave unprotected the surface of the, un
`wanted portions of the insulating layer. The layer is
`then treated with a suitable etchant, to remove the un
`
`ABSTRACT OF THE DISCLOSURE
`An array of devices is ñrst formed in a silicon wafer.
`A protective layer of silicon nitride is deposited on the
`surface of the wafer, and a glass handle body having
`a thermal expansion coeñìcient closely matching that of
`silicon is sealed to the silicon nitride layer. That portion
`of the wafer between adjacent devices is etched away,
`and a body of a softened glass which has a like expansion
`coefficient, but is less refractory than the glass handle
`body, is hot-pressed into the array of isolated devices.
`The handle body is then removed by etching.
`
`BACKGROUND OF THE INVENTION
`This invention relates to methods for forming an
`array of isolated zones of semiconductor material from
`a wafer of the material, and relates, in particular, to such
`methods where semiconductor devices are formed in the
`zones prior to the isolation process.
`Several methods have been developed in the semicon
`ductor art for dividing up a wafer of semiconductor
`material into an array of isolated zone, in order that
`adjacent devices subsequently formed in the zones are
`free of parasitic impedances. Some of these methods in
`clude actual physical separation of the zones and employ
`a “handle,” or a “support body” -which is disposed on
`the semiconducting wafer to lend structural support to
`the wafer during the isolation process. After the wafer
`is processed to separate the zones, the array of isolated
`zones is then hot-pressed into a softened insulating sub
`strate, such as glass; alternatively, a thin layer of insu
`lating material is deposited over the array of zones and
`an epitaxial layer of polycrystalline semiconducting mate
`rial is deposited over the insulating material to impart
`structural strength. The support body is then removed,
`and the devices are formed in the isolated zones of the
`semiconductor material. Examples of these processes are
`disclosed in Pats. 3,332,137 and 3,391,023.
`While methods previously known in the art provide
`isolation between adjacent devices, these methods suffer
`several disadvantages. First, the high temperatures re
`quired for the handle body disposing step prevents device
`fabrication until after the isolation process is completed.
`Thus, normal device fabrication, for example by the
`planar technique, is not feasible. Further, the high tem
`peratures required during the step of hot-pressing the
`array of zones into the insulating substrate tends to
`create unwanted dislocations in the zones. For example
`in silicon devices, it is known that dislocations begin
`to occur, and diffusion profiles are adversely affected,
`when the devices are subjected to processing temperatures
`above l100° C. for an appreciable period of time. In
`addition, in order that the surface of the wafer be com
`pletely bonded to the handle body during the isolation
`process, both the wafer and the body must be extremely
`flat, and thus, more costly.
`Therefore, it would be desirable to employ a low tem
`perature isolation process, so that the devices might be
`initially formed in the wafer. Further, it would be de
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`EXAMPLE
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`3,623,219
`protected portions of the layer, exposing those portions
`which is 25.0 mils thick is suitable. The Corning #1715
`glass was sealed to the silicon nitride layer by hot
`of the thinned surface of the wafer 10 which are to be
`pressing in a vacuum at l080° C. using 500 p.s.i. of pres
`removed. The wafer 10 is then treated with a suitable
`sure for 5 minutes. The glass and the wafer were then
`etchant, to remove those portions of the Wafer 10` be
`tween adjacent devices and provide the array of isolated
`l cooled to 860° C., at which temperature the body and
`devices 16-18. iIn FIG. 5, the array of isolated diodes
`the wafer were annealed with no pressure applied.
`16418 is shown with the protected portions of the mask
`The #1715 glass was then lapped to make its exposed
`insulating layer (numbered 26) remaining on each device.
`surface parallel to that of the wafer’s surface, and the
`Optionally, these portions of the layer 26 may then be
`lower surface of the wafer was polished to a thickness
`stripped away.
`of 1.0 mil, using a Lustrox polishing technique. A 1.0
`As shown in FIG. 6, an insulating body 28 of a
`micron layer of silicon dioxide was deposited on the
`softened glass which is less refractory than the glass of
`polished lower surface of the wafer by the pyrolytic de
`handle body 24, is hot-pressed into the isolated array
`composition of silane in oxygen at 450° C. The SiO2 layer
`and between adjacent devices. Preferably, the glass of the
`was then densiiied by heating in air to 800° C. for 10
`minutes. Using a photoresist technique, the SiO2 layer was
`insulating Vbody 28 also has a thermal expansion co
`efficient closely matching that of the material of the
`etched with buffered hydroiluoric acid, to define in the
`wafer 10, portions of which comprise the N type region
`layer a pattern ‘of bars 2.0 mils wide on 4.0 mils centers.
`of the three diodes 16-1‘81 in FIIG. 6. The insulating body
`The pattern was registered so that `a row of diodes was
`28 may ‘be pressed into the isolated array of devices by
`included in each bar; the bar pattern was then defined by
`heating the handle body 24, devices 16-18», and the in
`etching the wafer in a boiling solution of 25.0 grams of
`sulating body 28 to a temperature above the softening
`potassium hydroxide (KOH) in 100 cc. of Water for about
`point of the glass of the insulating body, and hot-pressing
`5 minutes. Since this particular etchant is crystallographi
`the body «28 into the array at a pressure between 50 and
`cally selective, it was necessary that the rows of the P-N
`1000 p.s.i. for about 5 minutes,
`diodes in the wafer be aligned parallel to the intersections
`Thereafter, the handle body 24 is removed (FIG. 7)
`of| the (lll) planes with the (100) surface of the wafer.
`using an etchant which does not attack the protective
`An insulating body of Corning #7070 glass was then hot
`layer 22. During the handle body removal step, the ex
`pressed into the array of silicon diodes, filling the regions
`posed surface and Sides of the insulating body 28Á are
`between adjacent diodes. This glass softens at a tempera
`covered with a suitable protective material.
`ture of about 715° C., has a thermal expansion coeñicient
`As illustrated in FIG. 8, the protective layer 22 is
`of about 32><10(cid:173)r1 cm./cm.° C., which closely matches
`then removed by etching. The underlying insulating
`that of silicon, and consists essentially of the following
`coating 20 is then treated with a photoresist-etch se
`by weight: silicon dioxide (SiOg), 70.0%; aluminum
`quence to define contact apertures 30, exposing portions
`oxide (Al2O3), 1.1%; Potassium dioxide (KZO), 0.5%;
`of the semiconducting regions 10 and 15 of the devices
`boron oxide (B203), 28.1%; and lithium oxide (LizO),
`16~1~8 at the surface 1\2. A metal contact layer is then
`1.2%. The thickness of the insulating body is not critical;
`deposited on the remaining insulating coating 20` and
`suitably, it is also about 25.01 mils thick. The hot-pressing
`through the contact apertures. The desired contact pattern
`step was done at 710° C. for about 10 minutes using 500
`is then defined, using a final photoresist-etch sequence.
`p.s.i. of pressure, and annealing at 500° C. for 15 minutes
`By way of illustration, contact structure 32 of FIG. 9
`with no pressure applied.
`bridges the coating 20 and makes contact through the
`The #1715 glass, which served as a temporary handle
`apertures to interconnect the diodes 16-18 in series.
`during the isolation process, was then removed by lapping
`Alternatively, the protective layer 22 may be treated
`the glass to about 3.0 mils thickness and dissolving the
`with a photoresist-etch sequence to define the contact
`remainder in a 49% hydrofluoric acid solution; during this
`apertures through the protective layer 22 and the in
`step, the #7070 glass w’as protected by being waxed with
`sulating coating 20; the remaining portions of the protec
`paraffin to an alumina disc. The silicon nitride layer was
`tive layer 22 thus serve as further protection from the
`then removed by etching in hot phosphoric acid. The
`ambient.
`contact apertures were defined in the oxide layer by using
`a photoresist sequence and a buffered hydrofluoric acid
`etch.
`An alternate embodiment of, the present method will
`be described with reference to FIG. 9. The method is
`essentially the s'ame as that described above, except that,
`alternatively, a refractory metal structure 32 is deposited
`and defined on the insulating coating 20, before deposi
`tion of the protective layer 22. Suitable refractory metals
`include tungsten and molybdenum; however, tungsten is
`preferred.
`Another alternative step in the basic process comprises
`depositing a thin metal layer 40 (FIG. 9) on each N type
`region 10 of the isolated diodes 16-18, after the step of
`removing portions’ of the wafer, and before the step of
`pressing the array into the insulating body 28. Preferably,
`the metal layer 40 comprises nickel deposited by an elec
`troless process. The nickel layer serves to reduce the
`equivalent resistance of the semiconducting region upon
`Which it is deposited.
`The isolation process of the present invention offers
`many advantages. First, the maximum temperature used
`in the process does not exceed 1100" C., and thus, does
`not cause a substantial change in device diffusion pro
`ñles, allowing isolation to be carried out after the devices
`are fabricated by normal planar techniques. Further, the
`lower temperatures and pressures used in either hot
`pressing step minimizes the introduction of dislocations
`in the semiconducting wafer. In addition, the use of a.
`
`A specific example of the present method, as employed
`to produce an isolated array of diodes for use as an
`image sensor, will now -be described. The starting ma
`terial was an N type monocrystalline silicon wafer hav
`ing a rectangular grid of P`(cid:173)N diodes diffused into the
`wafer, with the diodes spaced 4.0l mils -apart in both
`directions. The dimensions of the wafer are not critical;
`by way of example, a wafer 1.5 inches in diameter and
`6.0 mils thick is suitable. During device diffusion, a thin
`layer of silicon dioxde was deposted on the surface of
`the wafer.
`Next, a protective layer of silicon nitride about 1000
`A. thick, was deposited on the silicon dioxide layer by
`the pyrolytic decomposition from the reaction of silane
`(SiH4) and ammonia (NH3). Silicon nitride serves as a
`good protective layer, since it resists hydrofluoric acid,
`whch is an excellent etchant for most refractory glasses.
`Thereafter, a handle body of Corning #1715 glass
`was sealed to the silicon nitride protective layer. This
`glass softens at a temperature of about 1060° C., has
`a thermal expansion coefficient of about 35x10*7 cm./
`cm./ ° C., which closely matches that of silicon, and
`Vconsists essentially of the following, by weight: silicon
`tdioxide (SiOZ), 63.7%; aluminum oxide (A1203), 25.0%;
`and calcium oxide (CaO), 113%. The thickness of the
`glass handle body is not critical; for‘instance, a body
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`Raytheon2049-0004
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`glass handle body, as described, eliminates the need for
`extremely íiat semiconducting wafers and handle bodies.
`What is claimed is:
`1. A method for forming a body of electrically isolated
`semiconductor devices from a semiconducting wafer in
`which the devices are initially formed, comprising the
`steps of :
`providing a crystalline semiconducting wafer having
`two opposed major surfaces;
`forming a plurality of semiconductor devices in the
`wafer adjacent a first one oft the surfaces;
`depositing `a protective layer of silicon nitride on the
`íirst surface;
`sealing a handle body of a refractory glass to the
`protective layer;
`removing portions of the 'wafer between adjacent de
`vices so as to provide an array of electrically isolated
`devices;
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`pressing an insulating body of softened glass which is
`less refractory than the glass of the handle body, into
`the array of devices and between adjacent devices;
`and
`dissolving the handle body using a chemical etchant
`which does not attack the protective layer.
`2. A method in accordance with claim 1, including the
`additional step of:
`disposing a refractory metal contact pattern on the
`upper surface of the wafer after the device forming
`step; and
`depositing the protective layer onto the first surface and
`the contact pattern.
`3. A method in accordance with claim 1, wherein the
`etchant consists of hydrotiuoric acid.
`4. A method in accordance with claim 1, wherein the
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`3,623,219
`glass handle body and the glass insulating body have a
`coeiiicient of thermal expansion closely matching that of
`the semiconducting wafer.
`5. A method in accordance with claim 4, wherein the
`glass of the handle body has a softening temperature
`below ll00° C.
`6. A method in accordance with claim 1, wherein the
`handle tbody sealing step comprises:
`heating the handle body to a temperature above the
`softening point of the refractory glass; and
`pressing the handle body and the wafer together with
`a pressure suflicient to seal the handle body to the
`protective layer.
`7. A method in accordance with claim 1, including the
`additional step of depositing a metal layer on each iso~
`lated device, after the step of removing portions of the
`wafer.
`8. A method in accordance with claim 1, including the
`additional step of depositing a protective material on the
`insulating body after the insulating body pressing step.
`
`References Cited
`UNITED STATES PATENTS
`9/1967 Donovan „___ 29‘-576 IW UX
`4/196‘8 Thornton ___-- 29-576 I‘W UX
`2/ 1968 Cave ______ __ 29--576` IW UX
`9/ 1967 lRamsey ____ __ 29-576 IW UX
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`25
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`3,343,255
`3,381,182
`3,370,204
`3,341,743
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`30
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`JOHN F. CAMPBELL, Primary Examiner
`W. TUPMAN, Assistant Exominer
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`156-17
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`U.S. C1. X.R.
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`Raytheon2049-0005