1975 IEEE Text Speech
`
`Gordon E. Moore, Co-founder
`Intel Corporation
`
`Progress In Digital
`Integrated Electronics
`
`Complexity of integrated circuits has approxi-
`mately doubled every year since their introduc-
`tion. Cost per function has decreased several
`thousand-fold, while system performance
`and reliability have been improved dramatically.
`Many aspects of processing and design
`technology have contributed to make the
`manufacture of such functions as complex
`single chip microprocessors or memory cir-
`cuits economically feasible. It is possible to
`analyze the increase in complexity plotted in
`Figure 1 into different factors that can, in turn,
`be examined to see what contributions have
`been important in this development and how
`they might be expected to continue to evolve.
`The expected trends can be recombined to
`see how long exponential growth in complexity
`can be expected to continue.
`
`Figure 1 Approximate component count for complex
`integrated circuits vs. year of Introduction.
`
`A first factor is the area of the integrated
`structures. Chip areas for some of the
`largest of the circuits used in constructing
`Figure 1 are plotted in Figure 2. Here again,
`the trend follows an exponential quite well,
`but with significantly lower slope than the
`complexity curve. Chip area tor maximum
`complexity has increased by a factor of ap-
`proximately 20 from the first planar transistor
`in 1959 to the 16,384-bit charge-coupled
`device memory chip that corresponds to the
`point plotted for 1975, while complexity,
`according to the annual doubling law, should
`have increased about 65,000-fold. Clearly
`much of the increased complexity had to
`result from higher density of components on
`the chip, rather than from the increased area
`available through the use of larger chips.
`
`
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`
`
`Figure 2 Increase in die area for most complex integrated
`devices commercially available.
`
`Density was increased partially by using finer
`scale microstructures. The first integrated
`circuits of 1961 used line widths of 1 mil (~25
`micrometers) while the 1975 device uses 5
`micrometer lines. Both line width and spacing
`between lines are equally important in improving
`density. Since they have not always been equal,
`
`G. E. Moore, “Progress in Digital Integrated Electronics.” © 1975 IEEE. Reprinted, with permission, from Technical
`Digest 1975. International Electron Devices Meeting, IEEE, 1975, pp. 11-13.
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`Figure 3 Device density contribution from the decrease in line widths
`and spacings.
`
` Figure 4 Decomposition of the complexity curve into various components.
`
`the average of the two is a good parameter to relate to the
`area that a structure might occupy. Density can be expected to
`be proportional to the reciprocal of area, so the contribution
`to improve density vs. time from the use of smaller dimensions
`is plotted in Figure 3.
`
`Neglecting the first planar transistor, where very conserva-
`tive line width and spacing was employed, there is again a
`reasonable fit to an exponential growth. From the exponential
`approximation represented by the straight line in Figure 3,
`the increase in density from this source over the 1959-1975
`period is a factor of approximately 32.
`
`Combining the contribution of larger chip area and higher
`density resulting from geometry accounts for a 640-fold
`increase in complexity, leaving a factor of about 100 to
`account for through 1975, as is shown graphically in Figure 4.
`This factor is the contribution of circuit and device advances
`to higher density. It is noteworthy that this contribution to
`complexity has been more important than either increased
`chip area or finer lines. Increasingly the surface areas of the
`integrated devices have been committed to components
`rather than to such inactive structures as device isolation
`and interconnections, and the components themselves
`have trended toward minimum size, consistent with the
`dimensional tolerances employed.
`
`Can these trends continue?
`
`Extrapolating the curve for die size to 1980 suggests that
`chip area might be about 90,000 sq. mils, or the equivalent
`of 0.3 inches square. Such a die size is clearly consistent with
`the 3 inch wafer presently widely used by the industry. In fact,
`the size of the wafers themselves have grown about as fast as
`has die size during the time period under consideration and
`can be expected to continue to grow. Extension to larger die
`size depends principally upon the continued reduction in the
`density of defects. Since the existence of the type of defects
`that harm integrated circuits is not fundamental, their density
`can be reduced as long as such reduction has sufficient
`economic merit to justify the effort. I see sufficient continued
`merit to expect progress to continue for the next several
`years. Accordingly, there is no present reason to expect a
`change in the trend shown in Figure 2.
`
`With respect to dimensions, in these complex devices we
`are still far from the minimum device sizes limited by such
`fundamental considerations as the charge on the electron
`or the atomic structure of matter. Discrete devices with
`sub-micrometer dimensions show that no basic problems
`should be expected at least until the average line width and
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`slope in the next few years as shown in Figure 5. The new
`slope might approximate a doubling every two years, rather
`than every year, by the end of the decade.
`
`Even at this reduced slope, integrated structures containing
`several million components can be expected within ten
`years. These new devices will continue to reduce the cost of
`electronic functions and extend the utility of digital electronics
`more broadly throughout society.
`
`
`Figure 5 Projection of the complexity curve reflecting the limit on
`increased density through invention.
`
`spaces are a micrometer or less. This allows for an additional
`factor of improvement at least equal to the contribution
`from the finer geometries of the last fifteen years. Work in
`non-optical masking techniques, both electron beam and
`X-ray, suggests that the required resolution capabilities will
`be available. Much work is required to be sure that defect
`densities continue to improve as devices are scaled to take
`advantage of the improved resolution. However, I see no
`reason to expect the rate of progress in the use of smaller
`minimum dimensions in complex circuits to decrease in
`the near future. This contribution should continue along
`the curve of Figure 3.
`
`
`With respect to the factor contributed by device and circuit
`cleverness, however, the situation is different. Here we are
`approaching a limit that must slow the rate of progress. The
`CCD structure can approach closely the maximum density
`practical. This structure requires no contacts to the compo-
`nents within the array, but uses gate electrodes that can be
`at minimum spacing to transfer charge and information
`from one location to the next. Some improvement in overall
`packing efficiency is possible beyond the structure plotted as
`the 1975 point in Figure 1, but it is unlikely that the packing
`efficiency alone can contribute as much as a factor of four,
`and this only in serial data paths. Accordingly, I am Inclined
`to suggest a limit to the contribution of circuit and device
`cleverness of another factor of four in component density.
`
`With this factor disappearing as an important contributor,
`the rate of increase of complexity can be expected to change
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