Ulllted States Patent [19]
`Piwonka et al.
`
`US006073206A
`[11] Patent Number:
`[45] Date of Patent:
`
`6,073,206
`Jun. 6, 2000
`
`[54] METHOD FOR FLASHING ESCD AND
`VARIABLES INTOA ROM
`_
`_
`[75] Inventors: Mark A. Plwonka; Louis B. Hobson,
`both of Tomball; J e?'rey D. Kane,
`Spring; Randall L- HESS, Cypress, all
`Of TeX-
`
`Intel Corporation, “PentiumTM Processor’s User’s Manual,
`vol. 3: Architecture and Programming Manual,” @ Intel
`Corporation, 1996, pp. 20.1—20.9.
`
`Intel Corporation, “Intel486TM SL Microprocessor SuperSet
`Programmer’s Reference Manual,” Nov., 1992, pp.
`6.28—6.53.
`
`[73] Assignee: Compaq Computer Corporation,
`Houstoth Tex
`
`[21] Appl- N93 09/070,866
`[22]
`Filed:
`Apr. 30, 1998
`
`Primary Examiner—Do Hyun Yoo
`Assistant Examiner—Nasser MoaZZami
`Attorney, Agent, or Firm—Akin, Gump, Strauss, Hauer &
`Feld, LLP
`
`[51]
`
`Int. c1.7 .................................................... .. G06F 13/00
`
`[57]
`
`ABSTRACT
`
`[52] US‘
`
`’ 707/204;
`’
`’
`’
`[58] Field of Search ................................... .. 711/102, 103,
`711/161 162 170 714/4 5 6_ 395/653
`’
`’
`’
`70%/2b2: 203, 204;
`
`[56]
`
`References Cited
`
`U'S' PATENT DOCUMENTS
`
`5,339,437
`5,608,876
`5,724,027
`5,748,94O
`5,864,698
`
`8/1994 Yuen ..................................... .. 395/700
`3/1997 Cohen et al.
`..
`3/1998 Shipman et al. ................. ..
`5/1998 Angelo et al. ........................ .. 711/163
`1/1999 Krau et al. ................................ .. 713/2
`OTHER PUBLICATIONS
`Compaq Computer Corporation, PhoeniX Technologies Ltd.,
`Intel Corporation, “‘Preliminary’ Plug and Play Bios Speci
`?cation, Version 1.0A, ” Mar. 10, 1994, pp. 7—23, 57—64.
`.
`.
`.
`Compaq Computer Corporation, Intel Corporation, Phoenix
`Technologies Ltd‘ Extended System Con?guration Data
`speci?cation’versi’on 1 02 Feb 14 1994 @1993 pp 1_33
`Advanced ’Micro
`be‘licesi
`’Inc~ ’ “Am2’91P002Ty
`Am29F002B, 2 Megabit (262,144><8—Bit) CMOS 5.0 Vol-
`t—only, Sector Architecture Flash Memory,” @ 1996, pp.
`1—34.
`
`A computer system for ?ashing Extended System Con?gu
`ration Data (ESCD) and associated variables to a ?ash
`read-Only memory (ROM) 15 proYlded' Dunng. Power-On
`Self-Test (POST) code, a ROM image is copied from an
`ESCD sector of a read-only memory to an ESCO original
`buffer and an ESCD Write buffer. The ESCD Write buffer
`may be updated by POST code. FolloWing the POST
`operations, the contents of the ESCD Write buffer are copied
`to an ESCD runtime buffer. The contents of the ESCD
`
`Original buffer or the ESCD Seeter are Compared to the
`contents of the ESCD runtime buffer. If the contents of the
`runtime bu?er di?er from the Contents of the Com
`pared buffer or Sector, SMI Code ?ashes the ROM image in
`the ESCD runtime buffer to the ?ash ROM‘ If the ESCD
`runtime buffer is the same as the contents of the compared
`buffer or sector, a ROM ?ash it not performed. POST is then
`exited and the computer system is booted. During runtime,
`if a Write is performed to ESCD data or an associate variable,
`the ESCD runtime buffer is updated With the ESCD data or
`.
`.
`.
`.
`variable provided for the Write operation. The SMI code then
`?ashes the ROM image in the ESCD runtime buffer into the
`ESCD sector to save the ESCD data or variable provided by
`the Whte epetatleh
`
`24 Claims, 3 Drawing Sheets
`
`COFVROMlMAGEW
`ESWORlGINAlEUFFER
`MSDDWRITEBUFFER
`
`i - - - -- 202
`
`r’
`
`_,
`
`UPDATEESCD
`l
`WRITEBUFFER
`I
`L wmwosr
`
`COPY ESCD WRlTE
`BUFFERTO ESCD
`RUNHME BUFFER
`
`1
`
`

`

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`

`U.S. Patent
`
`Jun. 6, 2000
`
`Sheet 2 0f 3
`
`6,073,206
`
`100
`
`OSI
`APPLICATION
`
`1 04
`
`f1 06
`
`l '
`FLASH
`(ESCD SECTOR)
`ROM
`
`[- 106
`
`/-108
`
`FLASH ROM
`
`> ESCD ORIGINAL
`BUFFER
`
`f1 10
`
`1 14
`
`[1 1 2
`
`ESCD WRITE
`BUFFER
`
`POST
`CODE
`
`ESCD RUNTIME
`BUFFER
`
`3
`
`

`

`U.S. Patent
`
`Jun. 6,2000
`
`Sheet 3 of3
`
`6,073,206
`
`ESCD FLASH
`PROCESS
`
`COPY ROM IMAGE TO / 200
`ESCD ORIGINAL BUFFER
`& ESCD WRITE BUFFER
`
`___i___ 202
`
`UPDATE ESCD
`I
`WRITE BUFFER
`I
`L WITH POST
`
`r’
`|
`_,
`
`_ _ _ _ _ _ - - - - — — - — — POST OPERATIONS
`
`/ 204
`
`f 206
`
`COPY ESCD WRITE
`BUFFER TO ESCD
`RUNTIME BUFFER
`
`E
`COMPARE ESCD
`ORIGINAL BUFFER OR
`ESCD SECTOR WITH
`ESCD RUNTIME BUFFER
`
`208
`Y
`
`N
`
`SMI CODE FLASHES
`NEW IMAGE INTO
`ESCD SECTOR
`
`,- 214
`
`f 216
`
`UPDATE ESCD
`RUNTIME BUFFER
`
`E
`SMI CODE FLASHES
`NEW lMAGE INTO
`ESCD SECTOR
`
`____+
`FIG. 4
`
`4
`
`

`

`1
`METHOD FOR FLASHING ESCD AND
`VARIABLES INTO A ROM
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to read-only-memory
`(ROM) ?ashing, and more particularly to a method for
`?ashing Extended System Con?guration Data (ESCD) and
`variables into a ROM of a computer system.
`2. Description of the Related Art
`In order to support the automatic con?guration of Plug
`and Play devices on platforms that include a standard
`expansion bus, non-volatile storage such as CMOS RAM,
`ROM, or NVRAM is used to store information about system
`resources used by non-Plug and Play devices in a computer
`system. This con?guration information is typically stored in
`an Extended System Con?guration Data (ESCD) format.
`The ESCD format accommodates storage of con?guration
`information for Plug and Play devices and non-Plug and
`Play devices. ESCD generally alloWs Plug and Play System
`Basic Input Output Services (BIOS) code to more fully
`con?gure a computer system at poWer up by specifying the
`system resources assigned to devices that have been
`installed in the system. The portion of non-volatile storage
`used to store the ESCD may be only a subset of the total
`non-volatile storage available in a computer system.
`System BIOS code is used by the operating system to read
`or Write ESCD as the non-volatile storage storing ESCD has
`traditionally resided in the system BIOS memory space.
`Accordingly, only system BIOS has knoWn the location of
`the ESCD in the non-volatile storage and the proper method
`for accessing the non-volatile storage. If the non-volatile
`storage is memory-mapped, the physical base address of the
`memory mapped non-volatile storage alloWs a “caller,” such
`as an operating system, to construct a segment descriptor
`pointed to by a memory pointer knoWn as a segment
`selector. If a function to read or Write ESCD is called from
`a protected mode, the segment descriptor is created from a
`protected mode base segment address typically termed an
`ESCD Selector parameter. If a function to read or Write
`ESCD is called from real mode, a segment descriptor is
`created from a real mode base segment address typically
`termed a BIOS Selector parameter. A segment selector
`serves as a pointer to a segment descriptor for an ESCD area
`of non-volatile storage. In addition, a function to read or
`Write ESCD generates a pointer to the siZe of ESCD for
`determining an entry point into the ESCD. Afunction to read
`ESCD transfers ESCD from an ESCD area of non-volatile
`storage to a memory buffer typically having a pointer termed
`ESCD Buffer, and a function to Write ESCD transfers data
`from the memory buffer to an ESCD area of non-volatile
`storage. ESCD functions are further described in the
`Extended System Con?guration Data Speci?cation, Version
`1.02, published on Feb. 14, 1994, by Compaq Computer
`Corporation, Intel Corporation, and Phoenix Technologies,
`Ltd.
`ESCD may be updated during a PoWer-On-Self-Test
`(POST) or at runtime. For example, ESCD may be updated
`by POST if POST detects that a neW Plug and Play bootable
`device is added to the computer system. ESCD information
`may be used by POST to allocate system resources to all
`con?gurable devices that are knoWn to the system BIOS.
`System resources typically include Direct Memory Access
`(DMA) channels, Interrupt Request Lines (IRQ’s), Input/
`Output (I/O) addresses, and memory. ESCD also may be
`updated during runtime by system softWare in order to effect
`
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`con?guration of devices on the next boot. An ESCD inter
`face provides a mechanism for alloWing system softWare to
`lock system resources allocated to speci?c devices in the
`system and thereby avoid system resource con?icts.
`Updating ESCD in a conventional computer system has
`been dependent upon a segment selector from an operating
`system. The segment selector used by system BIOS to
`address an ESCD area of non-volatile storage is generated
`by the operating system. As a segment selector is exclusively
`con?gured for the memory map of the operating system, a
`segment selector loses meaning outside the context of the
`operating system memory map. A segment selector provided
`by an operating system also must be con?gured for the
`particular operating mode—real mode, 16-bit protected
`mode, or 32-bit protected mode—Whichever is applicable.
`The segment selector in one operating mode is therefore
`different from the segment selector for another operating
`mode. Further, the need for a segment selector from an
`operating system to update ESCD has required a different
`selector if an ESCD area is relocated. Another draWback of
`using a segment selector from an operating system to read or
`Write ESCD is the need to use a relatively sloW bus Within
`a computer system to reach the ESCD area of non-volatile
`storage.
`ESCD has typically resided in a portion of a ROM treated
`as an option ROM. Option ROM represents a designated
`area of ROM space Which an operating system preferably is
`programmed not to utiliZe. In certain operating modes,
`hoWever, availability of an option ROM is not guaranteed.
`For example, during runtime in a 32-bit protected mode, an
`operating system may not provide a segment selector to an
`option ROM, thereby preventing access to the option ROM
`during runtime. In addition, the siZe of the ROM space for
`Which an operating system provides a segment selector is
`limited.
`
`SUMMARY OF THE INVENTION
`
`Brie?y, a computer system according to the present inven
`tion provides a method of ?ashing Extended System Con
`?guration Data (ESCD) and variables stored With ESCD to
`a read-only-memory (ROM) using System Management
`Interrupt (SMI) code. An ESCD sector is de?ned in a
`read-only-memory for storing ESCD and associated vari
`ables. During PoWer-On-Self-Test (POST) code, a ROM
`image of the ESCD sector is copied to an ESCD original
`buffer and an ESCD Write buffer. The ESCD original buffer
`and ESCD Write buffer are areas of random access memory
`(RAM) used during POST for storing a ROM image of
`ESCD and associated variables. The ESCD Write buffer may
`be updated by POST code. FolloWing the POST operations,
`the contents of the ESCD Write buffer are copied to an ESCD
`runtime buffer. The ESCD runtime buffer is a RAM area to
`be used during runtime for storing ESCD data and associ
`ated variables. The contents of the ESCD original buffer or
`the ESCD sector are compared to the contents of the ESCD
`runtime buffer. If the contents of the ESCD runtime buffer
`differ from the contents of the compared buffer or sector,
`SMI code ?ashes the ROM image in the ESCD runtime
`buffer to the ESCD sector. If the ESCD runtime buffer is the
`same as the contents of the compared buffer or sector, a
`ROM ?ash is not performed. POST is then exited and the
`computer system is booted.
`During runtime, any Write to ESCD or an associated
`variable is detected. If a Write to ESCD or an associated
`variable is detected, the ESCD runtime buffer is updated
`With the ESCD or variable provided for the Write operation.
`
`5
`
`

`

`6,073,206
`
`3
`The SMI code then ?ashes the ROM image in the ESCD
`runtime buffer into the ESCD sector to save the ESCD or
`variable provided by the Write operation.
`This method of ?ashing ESCD and associated variables
`permits ESCD and associated variables to be ?ashed in any
`operating mode Whether real mode, 16-bit protected mode,
`or 32-bit protected mode. An operating mode-speci?c seg
`ment selector from an operating system for locating ESCD
`thus is no longer needed. Another advantage of this method
`of ?ashing ESCD and associated variables is the reduced
`POST execution time. This advantage is achieved by using
`the ESCD buffers to read a ROM image during late POST
`and runtime rather than reading a ROM image from the
`ESCD sector.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`A better understanding of the present invention can be
`obtained When the folloWing detailed description of the
`preferred embodiment is considered in conjunction With the
`folloWing draWings, in Which:
`FIG. 1 is a schematic diagram of a computer system
`including a ?ash ROM;
`FIG. 2 is a data ?oW diagram of an ESCD ?ash process
`in accordance With the present invention;
`FIG. 3 is a data ?oW diagram of an ESCD ?ash process
`using an ESCD original buffer, ESCD Write buffer, and
`ESCD runtime buffer in accordance With the present inven
`tion; and
`FIG. 4 is a ?oWchart of the ESCD ?ash process of FIG.
`3.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`Turning to FIG. 1, illustrated is a typical computer system
`S implemented according to the invention. While this system
`is illustrative of one embodiment, the techniques according
`to the invention can be implemented in a Wide variety of
`systems. The computer system S in the illustrated embodi
`ment is a PCI bus/ISA bus based machine, having a periph
`eral component interconnect (PCI) bus 10 and an industry
`standard architecture (ISA) bus 12. The PCI bus 10 is
`controlled by PCI controller circuitry located Within a
`memory/accelerated graphics port (AGP)/PCI controller 14.
`This controller 14 (the “host bridge”) couples the PCI bus 10
`to a processor socket 16 via a host bus, an AGP connector
`18, a memory subsystem 20, and an AGP 22. A second
`bridge circuit, a PCI/ISA bridge 24 (the “ISA bridge”)
`bridges betWeen the PCI bus 10 and the ISA bus 12.
`The host bridge 14 in the disclosed embodiment is a
`440LX Integrated Circuit by Intel Corporation, also knoWn
`as the PCI AGP Controller (PAC). The ISA bridge 24 is a
`PIIX4, also by Intel Corporation. The host bridge 14 and ISA
`bridge 24 provide capabilities other than bridging betWeen
`the processor socket 16 and the PCI bus 10, and the PCI bus
`10 and the ISAbus 12. Speci?cally, the disclosed host bridge
`14 includes interface circuitry for the AGP connector 18, the
`memory subsystem 20, and the AGP 22. The ISA bridge 24
`further includes an internal enhanced IDE controller for
`controlling up to four enhanced IDE drives 26, and a
`universal serial bus (USB) controller for controlling USB
`ports 28.
`The host bridge 14 is preferably coupled to the processor
`socket 16, Which is preferably designed to receive a Pentium
`II processor module 30, Which in turn includes a micropro
`cessor core 32 and a level tWo
`cache 34. The processor
`
`4
`socket 16 could be replaced With different processors other
`than the Pentium II Without detracting from the spirit of the
`invention.
`The host bridge 14, When the Intel 440LX North Bridge
`is employed, supports extended data out (EDO) dynamic
`random access memory (DRAM) and synchronous DRAM
`(SDRAM), a 64/72-bit data path memory, a maximum
`memory capacity of one gigabyte, dual inline memory
`module (DIMM) presence detect, eight roW address strobe
`(RAS) lines, error correcting code (ECC) With single and
`multiple bit error detection, read-around-Write With host for
`PCI reads, and 3.3 volt DRAMs. The host bridge 14 support
`up to 66 megahertZ DRAMs, Whereas the processor socket
`16 can support various integral and non-integral multiples of
`that speed.
`The ISA bridge 24 also includes enhanced poWer man
`agement. It supports a PCI bus at 30 or 33 megahertZ and an
`ISA bus 12 at 1A1 of the PCI bus frequency. PCI revision 2.1
`is supported With both positive and subtractive decode. The
`standard personal computer input/output (I/O) functions are
`supported, including a dynamic memory access (DMA)
`controller, tWo 82C59 interrupt controllers, an 8254 timer, a
`real time clock (RTC) With a 256 byte couple metal oxide
`semiconductor (CMOS) static RAM (SRAM), and chip
`selects for system read only memory (ROM), real time clock
`(RTC), keyboard controller, an external microcontroller, and
`tWo general purpose devices. The enhanced poWer manage
`ment Within the ISA bridge 24 includes ?ll clock control,
`device management, suspend and resume logic, advanced
`con?guration and poWer interface (ACPI), and system man
`agement bus (SMBus) control, Which implement the inter
`integrated circuit (I2C) protocol.
`The PCI bus 10 couples a variety of devices that generally
`take advantage of a high speed data path. This includes a
`small computer system interface (SCSI) controller 26, With
`both an internal port 38 and an external port 40. In the
`disclosed embodiment, the SCSI controller 26 is aAIC-7860
`SCSI controller. Also coupled to the PCI bus 10 is a netWork
`interface controller (NIC) 42, Which preferably supports the
`ThunderLanTN poWer management speci?cation by Texas
`Instruments. The NIC 42 is coupled through a physical layer
`44 and a ?lter 46 to an RJ-45 jack 48, and through a ?lter
`50 to a AUI jack 52.
`BetWeen the PCI Bus 10 and the ISA Bus 12, an ISA/PCI
`backplane 54 is provided Which include a number of PCI and
`ISA slots. This alloWs ISA cards or PCI cards to be installed
`into the system for added functionality.
`Further coupled to the ISA Bus 12 is an enhanced sound
`system chip (ESS) 56, Which provides sound management
`through an audio in port 58 and an audio out port 60. The
`ISA bus 12 also couples the ISA bridge 24 to a Super I/O
`chip 62, Which in the disclosed embodiment is a National
`Semiconductor Corporation PC87307VUL device. This
`Super I/O chip 62 provides a variety of input/output
`functionality, including a parallel port 64, an infrared port
`66, a keyboard controller for a keyboard 68, a mouse port for
`a mouse port 70, additional series ports 72, and a ?oppy disk
`drive controller for a ?oppy disk drive 74. These devices are
`coupled through connectors to the Super I/O 62.
`The ISA bus 12 is also coupled through bus transceivers
`76 to a ?ash ROM 78, Which can include both basic
`input/output system (BIOS) code for execution by the pro
`cessor 32, as Well as an additional code for execution by
`microcontrollers in a ROM-sharing arrangement. The ?ash
`ROM 78 includes an ESCD sector for storing ESCD and
`associated variables. Details concerning ESCD may be
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`obtained from the Extended System Con?guration Data
`Speci?cation, Version 1.02, published on Feb. 14, 1994 by
`Compaq Computer Corporation, Intel Corporation, and
`Phoenix Technologies, Ltd.
`The ISA bus 12 further couples the ISA bridge 24 to a
`security, poWer, ACPI, and miscellaneous application spe
`ci?c integrated circuit (ASIC) 80, Which provides a variety
`of miscellaneous functions for the system. The ASIC 80
`includes security features, system poWer control, light emit
`ting diode (LED) control, a PCI arbiter, remote Wake up
`logic, system fan control, hood lock control, ACPI registers
`and support, system temperature control, and various glue
`logic. Finally, a video display 82 can be coupled to the AGP
`connector 18 for display of data by the computer system S.
`Again, a Wide variety of systems could be used instead of the
`disclosed system S Without detracting from the spirit of the
`invention.
`Referring to FIG. 2, a data ?oW diagram of an ESCD ?ash
`process in accordance With the present invention is shoWn.
`An operating system or application 100 may initiate an
`update of the ESCD sector 106 so as to store data to ESCD
`or associated variables. The operating system 100 for
`example may call ROM BIOS code to be executed by the
`processor 32 for performing an update of the ESCD sector
`106 (FIGS. 2 & 3). In accordance With the present invention,
`an update related to the ESCD sector 106 is achieved by
`copying data to an ESCD runtime buffer 112 during runtime
`or POST (PoWer-On-Self-Test). POST is designed to
`identify, test, and con?gure the computer system S in
`preparation for starting the operating system. During late
`POST, data associated With the ESCD sector 106 may be
`copied to an ESCD Write buffer 110 (FIG. 3). The set of
`operations collectively termed the POST operations are of
`the conventional type knoWn in the art. During late POST,
`the contents of the ESCD Write buffer 110 may be copied to
`the ESCD runtime buffer 112. In the disclosed embodiment,
`data is copied a byte at a time. If the ESCD runtime buffer
`112 has been updated, runtime code 116 (FIG. 3) generates
`a softWare management interrupt (SMI) so as to pass the
`ROM image contained in the ESCD runtime buffer 112 to
`SMI code 104. In the disclosed embodiment, the SMI code
`104 is initially stored in the ?ash ROM 78 and copied to a
`volatile memory area during boot-up of the computer system
`S. The SMI code 104 ?ashes the ROM image to the ESCD
`sector 106 of the ?ash ROM 78. The SMI code 104 includes
`an algorithm for ?ashing the ESCD sector 106 Which is
`speci?c to the particular ?ash ROM 78. An algorithm for
`?ashing a ?ash ROM typically includes an erase sequence
`for erasing a ?ash ROM folloWed by a programming
`sequence for programming a ?ash ROM.
`Referring to FIG. 3, a data ?oW diagram of an ESCD ?ash
`process using an ESCD original buffer 108, the ESCD Write
`buffer 110, and an ESCD runtime buffer 112 in accordance
`With the present invention is shoWn. In accordance With the
`present invention, the ?ash ROM 78 includes the ESCD
`sector 106, POST code 114, SMI code 104 for ?ashing a
`ROM image into the ESCD sector 106, and code for
`executing the ESCD ?ash process. Referring to FIG. 4, a
`?oWchart of the ESCD ?ash process of FIG. 3 is shoWn.
`FolloWing boot-up of the computer system S, POST is
`initiated. Beginning at step 200, a ROM image of the ESCD
`sector 106 is copied to the ESCD original buffer 108 and the
`ESCD Write buffer 110. The ESCD original buffer 108
`serves to maintain the original ROM image of the ESCD
`sector 106. Next, in step 202, the ESCD Write buffer 110
`may or may not be updated by POST. Step 202 is shoWn in
`broken line to re?ect that the step is optional. If performed,
`step 202 is typically folloWed by a POST operation.
`
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`From either step 202 or 200, control proceeds to step 204
`of the POST operation Wherein the contents of the ESCD
`Write buffer 110 are copied to the ESCD runtime buffer 112
`during POST 114. Next, in step 206, either the ESCD
`original buffer 108 or the ESCD sector 106 is compared to
`the ESCD runtime buffer 112. The ESCD original buffer 108
`contains a ROM image of the ESCD sector 106. Either the
`ESCD original buffer 108, ESCD Write buffer 110, or the
`ESCD sector 106 may be used to determine if the ESCD
`sector 106 has been updated. Since the ESCD original buffer
`108 is a random access memory area, accessing the ESCD
`original buffer 108 is faster than accessing the ESCD sector
`106.
`Control then proceeds to step 208 Wherein it is determined
`if the ESCD runtime buffer 112 matches the compared buffer
`or sector. If the ESCD runtime buffer 112 does not match the
`compared buffer or sector, then control proceeds to step 210
`Wherein the SMI code 104 ?ashes the ROM image in the
`ESCD runtime buffer 112 into the ESCD sector 106. A
`mismatch betWeen the ESCD runtime buffer 112 and the
`compared buffer or sector indicates that the ESCD runtime
`buffer 112 has been updated. If the ESCD runtime buffer 112
`matches the compared buffer or sector, control proceeds to
`step 212. Amatch betWeen the ESCD runtime buffer 112 and
`the compared buffer or sector indicates that the ESCD
`runtime buffer 112 has not been updated.
`From step 210, control proceeds to step 212. FolloWing
`step 208 or 210, POST is exited and runtime begins. At step
`212, it is determined Whether there is a Write to ESCD data
`or associated variables. ESCD data and associated variables
`may change during runtime. If a Write to ESCD data or
`associated variables is detected, control proceeds from step
`212 to step 214. In step 214, the ESCD runtime buffer 112
`is updated With the data Written to ESCD or associated
`variables. The ESCD data or associated variables Written
`may be neW data or may be the same as previously stored
`data. Alternatively, it is contemplated that the ESCD runtime
`buffer 112 may be exclusively updated When a Write of neW
`ESCD data or associated variables is detected. From step
`214, control proceeds to step 216 Wherein the SMI code 104
`?ashes the ROM image in the ESCD runtime buffer 112 into
`the ESCD sector 106. This step is performed during a system
`management mode of the computer system S. From step
`216, control returns to step 212. In this Way, any Write to
`ESCD or associated variables during runtime results in
`?ashing a neW ROM image into the ESCD sector 106.
`The use of the ESCD Write buffer 110 and the ESCD
`runtime buffer 112 serves to isolate storage of ESCD and
`associated variables during POST from storage of ESCD
`and associated variables during runtime. The ESCD original
`buffer 108 and ESCD Write buffer 110 both serve as ESCD
`POST buffers. The ESCD original buffer 108 maintains the
`original ROM image of the ESCD sector 106, and the ESCD
`Write buffer 110 re?ects any updates to ESCD data and
`associated variables during POST. In the disclosed
`embodiment, the ESCD original buffer 108 and ESCD Write
`buffer 110 are random access memory areas existing during
`POST. Further, in the disclosed embodiment, the ESCD
`runtime buffer 112 is a random access memory area existing
`during late POST and runtime. It should be understood that
`the ESCD buffers and the ESCD sector described store both
`ESCD data and associated variables.
`In the disclosed embodiment, the associated variables
`include variables representing system features and oWner
`ship data. Speci?cally, the oWnership data variables may
`include an oWnership tag, a chassis serial number and
`manufacturing process numbers bytes. Use of an oWnership
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`tag, chassis serial number, and manufacturing process num
`ber bytes are conventional and known in the art. The
`ownership tag may be an 80-byte standard ASCI character
`string protected by an administrator passWord. In the dis
`closed embodiment, the speci?c oWnership tag used is, for
`example, “Property of
`,” the particular vendor of the
`system S. An oWnership tag is typically displayed during
`POST. Manufacturing process number bytes are used to
`track the last station of a manufacturing line Which the
`computer system has been through.
`In a conventional computer system, a segment selector
`from an operating system is used to locate ESCD. The
`segment selector provided by the operating system is con
`?gured for the particular operating mode—real mode, 16-bit
`protected mode, 32-bit protected mode—Whichever is appli
`cable. A segment selector in one operating mode is therefore
`different from a segment selector for another operating
`mode. Also, ESCD has typically resided in a portion of a
`ROM treated as an option ROM. In certain operating modes,
`hoWever, availability of an option ROM is not guaranteed.
`For example, during runtime in a 32-bit protected mode, an
`operating system may not provide a segment selector to an
`option ROM, thereby preventing access to the option ROM
`during runtime. In accordance With the ?ash process of the
`present invention, a ?ash may be performed in any operating
`mode since there is no operating system intervention. Using
`SMI code in accordance With the present invention thus
`provides for ?ashing a non-volatile memory independent of
`the operating mode of the computer system.
`Further, in a conventional computer system, updating
`ESCD has required accessing the non-volatile memory
`storing ESCD. The need to access a non-volatile memory
`each time ESCD is updated requires the transfer of ESCD
`across a relatively sloW bus coupled to the non-volatile
`memory. In accordance With the present invention, a ROM
`image is ?ashed from the ESCD runtime buffer 112. Access
`ing a random access memory area of the ESCD runtime
`buffer 112 as opposed to the ESCD sector 106 increases
`POST execution time since the ESCD runtime buffer 112
`may be accessed Without providing data across a relatively
`sloW bus.
`It should be understood that the ?ash process of the
`present invention may extend to areas of a non-volatile
`memory other than the ESCD sector. In accordance With the
`present invention, SMI code may be used to ?ash any area
`of the non-volatile memory. Further, it should be understood
`that a stack, pointers, and registers may be used in copying
`contents from one ESCD buffer to another ESCD buffer. It
`should also be understood that the ?ash process in accor
`dance With the present invention encompasses ?ashing any
`non-volatile memory and therefore is not limited to ?ashing
`a read-only-memory.
`The foregoing disclosure and description of the invention
`are illustrative and explanatory thereof, and various changes
`in the siZe, shape, materials, components, circuit elements,
`Wiring connections and contacts, as Well as in the details of
`the illustrated circuitry and construction and method of
`operation may be made Without departing from the spirit of
`the invention.
`What is claimed is:
`1. Amethod of ?ashing an extended system con?guration
`data (ESCD) storage area of a non-volatile memory of a
`computer system comprising the steps of:
`copying a non-volatile memory image of an ESCD data
`storage area for storing ESCD and associated variables
`of a non-volatile memory to a ?rst region of a poWer on
`self test (POST) buffer and a second region of the
`POST buffer;
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`copying contents of the second region of the POST buffer
`to an ESCD runtime buffer;
`comparing the contents of the ?rst region of the POST
`buffer or the ESCD data storage area of the non-volatile
`memory With the contents of the ESCD runtime buffer;
`and
`?ashing the non-volatile memory image in the ESCD
`runtime buffer into the ESCD data storage area during
`the system management mode of the computer system
`if the contents of the ESCD runtime buffer differ from
`the contents of the compared ?rst region of the POST
`buffer or the ESCD data storage area.
`2. The method of claim 1, further comprising the steps of:
`detecting an update to the ESCD runtime buffer during
`runtime; and
`?ashing the non-volatile image in the ESCD runtime
`buffer into the ESCD data storage area of the non
`volatile memory.
`3. The method of claim 1, further comprising the step of:
`updating the ?rst region of the POST buffer during POST
`before the step of copying the contents of the second
`region of the POST buffer to the ESCD runtime buffer.
`4. The method of claim 1, Wherein the non-volatile
`memory is a ?ash read-only memory.
`5. The method of claim 1, Wherein the POST buffer is an
`area of random access memory existing during POST.
`6. The method of claim 1, Wherein the ESCD runtime
`buffer is an area of random access memory existing during
`POST and runtime.
`7. The method of claim 1, Wherein the associated vari
`ables comprise variables representing system features or
`oWnership data.
`8. The method of claim 1, further comprising the step of:
`entering a system management mode of the computer
`system from a 16-bit protected mode of the computer
`system before the step of ?ashing the non-volatile
`image.
`9. The method of claim 1, further comprising the step of:
`entering a system management mode of the computer
`system from a 32-bit protected mode of the computer
`system before the step of ?ashing the non-volatile
`image.
`10. The method of claim 1, further comprising the step of:
`entering a system management mode of the computer
`system from a real mode of the computer system before
`the step of ?ashing the non-volatile image.
`11. A computer system for ?ashing an extended system
`con?guration data (ESCD) storage area of a non-volatile
`memory comprising:
`a non-volatile memory, comprising storage locations for:
`an ESCD data storage area for storing ESCD data and
`associated variables;
`a non-volatile memory BIOS storage area for storing
`BIOS code for generating an system management
`interrupt (SMI) ?ash for the ESCD data storage area
`of the non-volatil