(12) United States Patent
`Seo et al.
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006819602B2
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,819,602 B2
`Nov. 16, 2004
`
`(54) MULTIMODE DATA BUFFER AND METHOD
`FOR CONTROLLING PROPAGATION
`DELAY TIME
`
`(75)
`
`Inventors: Seong-young Seo, Suwon (KR);
`Jung-bae Lee, Yongin (KR); Byong-mo
`Moon, Seoul (KR)
`
`(73) Assignee: Samsung Electronics Co., Ltd.,
`Kyungki-Do (KR)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 77 days.
`
`(21) Appl. No.: 10/278,071
`
`(22) Filed:
`
`Oct. 23, 2002
`
`(65)
`
`Prior Publication Data
`
`US 2003/0210575 A1 Nov. 13, 2003
`
`Related U.S. Application Data
`(60) Provisional application No. 60/379,665, filed on May 10,
`2002.
`Int. Cl? .................................................. GllC 7/00
`(51)
`(52) U.S. Cl. .................. 365/193; 365/189.05; 365/191;
`365/194
`(58) Field of Search ............................ 365/189.05, 191,
`365/193, 194
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`6,279,073 B1 * 8/2001 McCracken eta!. ........ 711!105
`
`6,396,768 B2 *
`5!2002 Ooishi ........................ 365/233
`7/2002 Kim eta!.
`6,414,517 B1
`6,424,590 B1 *
`7/2002 Taruishi et a!. ........ 365/230.08
`6,452,849 B1 *
`9/2002 Iwamoto ..................... 365/201
`6,512,704 B1 *
`1!2003 Wu et a!.
`.............. 365/189.07
`2003/0090294 A1 * 5!2003 Chang .. ...... ...... .. ...... ... 326/93
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`KR
`
`0322915 A3
`2002046826
`
`7/1989
`6/2002
`
`* cited by examiner
`
`Primary Examiner-Van Thu Nguyen
`(74) Attorney, Agent, or Firm-Harness, Dickey & Pierce,
`P.L.C.
`
`(57)
`
`ABSTRACT
`
`A data buffer, such as a data strobe input buffer or a data
`input buffer, which may operate in multiple modes, such as
`a single mode (SM) and a dual mode (DM) and where the
`mode is selected by providing a signal, such as an external
`signal such as an address signal or an external command
`signal. A data buffer which can be used for a SM/DM
`dual-use and can improve a data setup/hold margin. A
`semiconductor memory device including one or more of the
`data buffers described above. A method for controlling
`propagation delay times which can improve a data setup/
`hold margin in a SM/DM dual-use data buffer.
`
`29 Claims, 13 Drawing Sheets
`
`21
`23
`r ------------ L------- -,
`r-- -·---- L----- ·----,
`I
`I
`t
`l
`CNT /CNTB
`:
`:
`1 /2~~2
`213
`l
`i 00 :
`r-__J,_--~~~~ ..--·----0--
`1\12
`
`1
`-
`
`OS
`
`231CNTB/CNT
`
`{DELAY
`
`DOS
`
`DQSB
`
`VREF
`
`L ______________________ J
`
`L-----------------~
`
`NVIDIA Corp.
`Exhibit 1103
`Page 001
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 1 of 13
`
`US 6,819,602 B2
`
`FIG. 1
`
`Prior .~~rt
`
`DO
`
`OQS
`
`DIN
`
`( SM mode I • OS
`
`( DM mode J
`
`- OS
`
`FIG. 2
`
`21
`r------------------~-------1
`I
`I
`I
`I
`
`l
`
`DOS
`
`OOSB
`
`VREf"
`
`213
`
`CNT/CNTB
`
`2ll
`
`I
`I
`'--00
`I
`I
`I
`I
`I
`I
`I
`I
`
`I • I
`
`I
`I
`
`NVIDIA Corp.
`Exhibit 1103
`Page 002
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 2 of 13
`
`US 6,819,602 B2
`
`FIG. 3A
`
`DQSB -----1
`
`C NT 8 -------4---------.
`
`VR EF -------4------l
`
`FIG. 3B
`
`CNT --.----[>~-- - CNTB
`
`FIG. 4
`
`CNT/CNTB
`
`MODE
`REGISTER SET
`
`COMMAND ADD
`
`NVIDIA Corp.
`Exhibit 1103
`Page 003
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 3 of 13
`
`US 6,819,602 B2
`
`FIG. 5A
`
`VDD
`
`VDD
`
`.;25i
`
`P-·-
`7 "1i 2
`
`714
`
`CNT
`
`VCCH
`
`710
`
`FIG. 5B
`
`VOLT AGE LEVEL
`
`T1
`
`T2
`
`NVIDIA Corp.
`Exhibit 1103
`Page 004
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 4 of 13
`
`US 6,819,602 B2
`
`FIG. 6
`
`voo
`
`1410aj 1420a 144·0a
`
`r------1 .j:;::.o-- CNT
`.....
`
`1430a
`
`GND
`
`FIG. 7
`
`21
`r ____________ L: ________ ,
`
`DOS D-r------.
`
`213
`r---~--~~o~o~~~.
`
`I
`I
`
`23
`r-- -·--- - L----- ·----,
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`~--os
`
`DQSB
`
`I
`I
`I L _____________________ _
`
`I'-J2
`
`·231CNTB/CNT
`
`~ }v22'3 ~
`
`L-----------------~
`
`NVIDIA Corp.
`Exhibit 1103
`Page 005
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 5 of 13
`
`US 6,819,602 B2
`
`FIG. 8
`
`Do----~----------~
`
`--t----OS
`
`231
`
`FIG. 9
`
`___,/
`
`DO
`
`DOS
`
`DIN
`
`~OS
`
`~OS
`
`NVIDIA Corp.
`Exhibit 1103
`Page 006
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 6 of 13
`
`US 6,819,602 B2
`
`FIG. 10
`
`DOS
`
`DOSS
`
`23
`""'
`Cdummy T
`V VREF
`vss
`
`21
`r-------------------~-------,
`I
`I
`I
`I
`:
`I
`I
`I
`
`213
`
`CNTB/CNT
`212
`
`I
`I
`I
`I
`1
`I
`I
`I
`I
`I
`I
`211
`I
`I
`I
`L------------------ ---------- J
`
`DO
`
`FIG. 11
`
`/ 31
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/CNTB
`33
`
`/32
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`CNT El/CNT
`34
`
`(
`
`.,____ __ DS
`
`DOS
`VREF
`
`DOSB
`
`NVIDIA Corp.
`Exhibit 1103
`Page 007
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 7 of 13
`
`US 6,819,602 B2
`
`FIG. 12
`
`.31
`
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/CNTB
`... 33
`
`.32
`
`CNTB/CI'JT
`
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`FIG. 13
`
`/.13o
`
`- DS
`
`-231
`
`/l~)a
`
`.31
`
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/CNTB
`,,33
`
`32
`
`CNTB/CNT
`
`DS
`
`,,..34
`
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`l Cdummy
`vss
`
`DOS
`VREF
`
`DQSB
`
`DOS
`VREF
`
`OQSB
`
`NVIDIA Corp.
`Exhibit 1103
`Page 008
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 8 of 13
`
`US 6,819,602 B2
`
`FIG. 14
`
`21
`r-- -- --- - ---- - -- - -- .L- ... ·- --- -,
`I
`
`CNT/CNTB
`
`I
`I
`I
`
`211
`L---------------------------J
`
`I
`I
`I
`
`DQ
`
`DQB
`
`VREF
`
`FIG. 15
`
`21
`r ____________ LC ________ l
`
`23
`r-- -·---- L----- ----,
`I
`I
`l
`:
`CNT/CNTB
`l / 23
`213
`I
`r----'---......,:~o~o~: ~-~ 2
`N2
`
`I
`
`I
`:-DIN
`
`DO
`
`I
`
`DOB
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`L----------------------~
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`L-----------------~
`
`231CNTB/CNT
`
`!~ ~2J3
`~
`
`NVIDIA Corp.
`Exhibit 1103
`Page 009
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 9 of 13
`
`US 6,819,602 B2
`
`FIG. 16
`
`DO
`
`008
`
`VREF
`
`Cdummy T
`r;
`vss
`
`21
`r-------------------L-------,
`
`213
`
`I
`I
`I
`:
`I
`I
`I
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`211
`I
`I
`L ___________________________ J
`
`FIG. 17
`
`/ 31
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`/32
`2nd
`01 FFERENTIAL
`AMPLIFIER
`
`CNT/CNTB
`33
`
`CN-1
`-13/CNT
`34
`
`DO
`VREF
`
`008
`
`DO
`
`·~ 11 (]
`
`/
`
`--DIN
`
`NVIDIA Corp.
`Exhibit 1103
`Page 010
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 10 of 13
`
`US 6,819,602 B2
`
`,. 110
`C.,
`
`/
`
`- DIN
`
`FIG. 18
`
`31
`
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/Cii~TB
`,.-33
`
`32
`
`CNTB/CNT
`
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`FIG. 19
`
`/1·1a
`
`31
`
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`CNT /CI'·-ITB
`,,. 33
`
`32
`
`CNTB/CNT
`
`DIN
`
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`l Cdummy
`vss
`
`DO
`VREF
`
`DQB
`
`DO
`VREF
`
`DQB
`
`NVIDIA Corp.
`Exhibit 1103
`Page 011
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 11 of 13
`
`US 6,819,602 B2
`
`FIG. 20
`
`,.. 1
`t.,
`./
`
`1 7
`r-··· ---- ..,.c ______ l
`170 I
`I
`I
`I
`DIN
`I
`I
`I
`~----~-r-
`I
`...J-.-. DINE
`I
`I
`I
`I
`I
`I
`I
`-r---· OINO
`I
`I
`I
`17b:
`1
`L --·-------------J
`
`1 1
`
`DATA
`INPUT BUFFER
`
`13
`
`OS
`DATA
`~~ STROBE SIGNAL t-----+---;--
`INPUT BUFFER
`
`DO
`
`DOS
`OQS8
`VREF
`
`CNT/CNTB
`
`15
`
`MODE
`REGISTER SET
`
`COMMAND ADD
`
`FIG. 21
`
`COMMAND 0
`
`DOS
`
`DQ
`
`-~
`
`NVIDIA Corp.
`Exhibit 1103
`Page 012
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 12 of 13
`
`US 6,819,602 B2
`
`FIG. 22
`
`~17
`
`DIN
`
`OS
`
`,.----+--------.------.>--·-
`
`.}' 17o
`
`22!~29o 2170
`
`DINE
`
`_.f 17b
`
`229b 217b
`DINO
`
`NVIDIA Corp.
`Exhibit 1103
`Page 013
`
`

`

`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 13 of 13
`
`US 6,819,602 B2
`
`17
`r-··-----L ______ -,
`I
`/ 17o :
`I
`I
`I
`---iO Q
`:
`-+--·DINE
`I
`I
`I
`I
`I
`:
`+--·DINO
`I
`I
`I
`1 7b I
`I
`_____________ J
`-·
`
`D
`
`0
`
`I
`I
`I
`
`r
`t
`r
`t
`
`FIG. 23
`
`DO
`008
`
`DQS
`DQSB
`VREF
`
`/ 11
`
`DATA
`INPUT BUFFER
`
`DIN
`
`r -
`
`/13
`
`DATA
`STROBE SIGNAL
`INPUT BUFFER
`
`OS
`
`CNT ...-
`
`/15
`
`MODE
`REGISTER SET
`
`COMMAND ADD
`
`NVIDIA Corp.
`Exhibit 1103
`Page 014
`
`

`

`US 6,819,602 B2
`
`1
`MULTIMODE DATA BUFFER AND METHOD
`FOR CONTROLLING PROPAGATION
`DELAY TIME
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`This U.S. nonprovisional application claims priority
`under 35 U.S.C. § 119 to U.S. Provisional Patent Applica(cid:173)
`tion No. 60/379,665 filed May 10, 2002, the entire contents
`of which are incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`5
`
`2
`(DM). However, since the gain of a differential amplifier in
`the single mode is different from the gain in the dual mode,
`the propagation delay time in the single mode is different
`from the propagation delay time in the dual mode.
`FIG. 1 illustrates waveforms produced in accordance with
`the prior art. As shown in FIG. 1, propagation delay time of
`the differential output signal (DS) in the SM mode is much
`greater than in the DM mode. Outputting the differential
`output signal (DS) at a different time in the SM mode and the
`10 DM mode degrades the uniformity of both the data setup
`time (tDS) and the data hold time (tDH) as illustrated in FIG.
`1. The difference in the propagation delay time may cause a
`difference in the setup/hold timing in each mode such that a
`data setup/hold margin is degraded.
`
`1. Field of the Invention
`The present invention relates to a semiconductor memory 15
`device, and more particularly, to a multimode data buffer and
`a method for controlling propagation time delay.
`2. Description of the Related Art
`To improve system performances, innovations in the
`design of semiconductor memory devices in general, and the
`design of dynamic random access memories (DRAMs) in
`particular, continue to focus on higher integration and higher
`speed operation. That is, DRAMs capable of processing
`more data at higher speed are desired. For higher speed
`operations, DRAMs synchronized with a system clock have
`been developed. This synchronous feature of DRAMs has
`increased data transmission speeds.
`However, since a data input/output operation in a syn(cid:173)
`chronous DRAM should be performed in a cycle of a system
`clock, there is a limit to increasing the bandwidth between
`the synchronous DRAM and a DRAM controller, that is, the
`amount of data which is input/output from a memory device
`in a unit time is limited. In order to increase data transmis(cid:173)
`sion speed, dual data rate (DDR) synchronous DRAMs in
`which data is input/output synchronized both with the rising 35
`edge and falling edge of a clock have been developed.
`In general, a DDR synchronous DRAM uses a data strobe
`signal when the DRAM receives data from a memory
`controller or sends data to the memory controller. For
`example, in a data receiving operation, the DDR synchro(cid:173)
`nous DRAM receives data with a data strobe signal from the
`memory controller. Also, in a data outputting operation, the
`DDR synchronous DRAM outputs data with a data strobe
`signal to the memory controller.
`In high speed semiconductor memory devices such as
`DDR synchronous DRAMs, a single mode (SM)-type input
`buffer, which compares a data strobe signal with a reference
`voltage, is used as a data strobe input buffer. However, in a
`DDR synchronous DRAM having an SM-type data strobe
`signal input buffer, a data setup/hold time margin may be
`degraded if noise is included in a data strobe signal or
`reference voltage.
`In order to compensate for this problem, a dual mode
`(DM)-type data strobe signal input buffer which compares a
`data strobe signal with the inverse signal of the data strobe
`signal instead of reference voltage has been introduced.
`Since an output signal is determined at the cross point of
`the two signals, that is, the data strobe signal and an inverse
`of the data strobe signal, in the DM-type data strobe signal 60
`input buffer, noise immunity improves.
`Also, more recently, in order to satisfy demands of a
`variety of users, an SM/DM dual-use data strobe signal input
`buffer has been developed. In an SM/DM dual-use data
`strobe signal input buffer, propagation delay time from an
`input terminal to an output terminal should be substantially
`the same both in the single mode (SM) and in the dual mode
`
`SUMMARY OF THE INVENTION
`Exemplary embodiments of the present invention are
`directed to a data buffer, which operates in a multiple modes,
`such as a data strobe input buffer or a data input buffer, each
`20 of which may operate a single mode (SM) and a dual mode
`(DM) and where a mode is selected by providing a signal,
`such as an external signal such as an address signal or an
`external command signal. The signal may be supplied by a
`number of sources, such as an internal mode register set
`25 (MRS), a fuse circuit, or a bonding pad circuit.
`Exemplary embodiments of the present invention are also
`directed to a data buffer which can be used for a SM/DM
`dual-use and can improve a data setup/hold margin.
`Exemplary embodiments of the present invention are also
`30 directed to a semiconductor memory device including one or
`more of the data buffers described above.
`In addition, exemplary embodiments of the present inven(cid:173)
`tion are directed to a method for controlling propagation
`delay time which can improve a data setup/hold margin in a
`SM/DM dual-use data buffer.
`Exemplary embodiments of the present invention are also
`directed to a data buffer including a differential amplifier
`circuit including at least two switches for passing an inverse
`40 data signal or a reference voltage, respectively, depending
`on a level of a control signal, and a differential amplifier for
`receiving a data signal, and either the inverse data signal or
`the reference voltage and outputting at least two different
`differentially amplified signals.
`In exemplary embodiments of the present invention, the
`data buffer is a data strobe input buffer, the inverse data
`signal is an inverse data strobe signal, and the data signal is
`a data strobe signal.
`In exemplary embodiments of the present invention, the
`50 data strobe input buffer is operable in both a single mode and
`a dual mode, wherein in said single mode, the reference
`voltage is applied to a first of the at least two switches and
`the level of the control signal is a first logic state and in said
`dual mode, the inverse data strobe signal is provided to a
`55 second of the at least two switches 212 and the level of the
`control signal is a second logic state.
`In exemplary embodiments of the present invention, the
`data strobe input buffer is part of a semiconductor memory
`device. In exemplary embodiments of the present invention,
`the semiconductor memory device also includes a control
`circuit for outputting the control signal to the data strobe
`input buffer.
`In exemplary embodiments of the present invention, the
`control circuit includes a mode register set for receiving an
`65 external command and an address and generating the control
`signal, wherein a level of the control signal determines a
`mode of the semiconductor memory device.
`
`45
`
`NVIDIA Corp.
`Exhibit 1103
`Page 015
`
`

`

`US 6,819,602 B2
`
`3
`In exemplary embodiments of the present invention, the
`control circuit includes a fuse circuit including a fuse,
`wherein a state of the fuse determines a level of the control
`signal.
`In exemplary embodiments of the present invention, the
`control circuit includes a bonding pad circuit, wherein a
`connection to Vee or ground determines a level of the
`control signal.
`In exemplary embodiments of the present invention, the
`differential amplifier unit includes a single differential
`amplifier.
`In exemplary embodiments of the present invention, the
`semiconductor memory device further includes a compen(cid:173)
`sating circuit for compensating one of the inverse data strobe
`signal, the reference voltage, or the data strobe signal or one 15
`of the at least two different differentially amplified signals so
`that each of at least two differential output signals have
`substantially the same delay time.
`In exemplary embodiments of the present invention, the
`compensating circuit includes a delay circuit for receiving
`the differentially amplified signal from said differential
`amplifier circuit, said delay circuit including a delay for
`delaying the differentially amplified signal, at least two
`additional switches for passing the differentially amplified
`signal or the delayed differentially amplified signal, as one
`of the at least two differential output signals, depending on
`the level of the control signal.
`In exemplary embodiments of the present invention, the
`compensating circuit includes a dummy load applied to one
`of the inverse data strobe signal, the reference voltage, or the 30
`data strobe signal.
`In exemplary embodiments of the present invention, the
`differential amplifier unit includes at least two differential
`amplifiers.
`In exemplary embodiments of the present invention, a 35
`gain of a first of the at least two differential amplifiers is
`substantially different from a gain of a second of the at least
`two differential amplifiers so that each of at least two
`differential output signals have substantially the same delay
`time.
`In exemplary embodiments of the present invention, a
`gain of a first of the at least two differential amplifiers is
`substantially the same as a gain of a second of the at least
`two differential amplifiers.
`In exemplary embodiments of the present invention, the 45
`semiconductor memory device further includes a compen(cid:173)
`sating circuit for compensating one of the inverse data strobe
`signal, the reference voltage, or the data strobe signal or one
`of the at least two different differentially amplified signals so
`that each of at least two differential output signals have 50
`substantially the same delay time.
`In exemplary embodiments of the present invention, the
`compensating circuit includes a delay circuit for receiving
`the differentially amplified signal from said differential
`amplifier circuit, said delay circuit including a delay for 55
`delaying the differentially amplified signal, at least two
`additional switches for passing the differentially amplified
`signal or the delayed differentially amplified signal, as one
`of the at least two differential output signals, depending on
`the level of the control signal.
`In exemplary embodiments of the present invention, the
`compensating circuit includes a dummy load applied to one
`of the inverse data strobe signal, the reference voltage, or the
`data strobe signal.
`In exemplary embodiments of the present invention, the 65
`semiconductor memory device further includes data input
`buffer for receiving a data signal and a reference voltage and
`
`4
`outputting a data input signal, a control circuit for outputting
`the control signal to the data strobe input buffer, and a data
`write circuit for receiving the data input signal from said
`data input buffer and the writing even number data of the
`5 data input signal into a first latch in response to a rising edge
`of the output data signal and writing odd number data of the
`data input signal into a second latch in response to a falling
`edge of the output data strobe signal.
`In exemplary embodiments of the present invention, the
`10 first latch includes a plurality of latches and a plurality of
`switches, arranged alternatively. In exemplary embodiments
`of the present invention, the plurality of switches are
`arranged to be triggered on the leading and falling edge of
`an inverse of the differential output signal.
`In exemplary embodiments of the present invention, a
`first switch receives the even number data of the output
`signal of the data input buffer and passes the even number
`data of the output signal to a first of the plurality of latches.
`In exemplary embodiments of the present invention, the
`20 second latch including a plurality of latches and a plurality
`of switches, arranged alternatively.
`In exemplary embodiments of the present invention, the
`plurality of switches are arranged to be triggered on the
`leading and falling edge of an inverse of the differential
`25 output signal.
`In exemplary embodiments of the present invention, a
`first switch receives the odd number data of the output signal
`of the data input buffer and passes the odd number data of
`the output signal to a first of the plurality of latches.
`In exemplary embodiments of the present invention, the
`data buffer is a data input buffer instead of, or in addition to,
`a data strobe buffer.
`In exemplary embodiments of the present invention, the
`semiconductor memory device further includes a data strobe
`input buffer for receiving an inverse data signal or a refer(cid:173)
`ence voltage, respectively, depending on a level of a control
`signal, and outputting at least two differential output signals,
`a control circuit for outputting the control signal to said data
`strobe input buffer, and a data write circuit for receiving the
`40 data input signal from the data input buffer and the writing
`even number data of the data input signal into a first latch in
`response to a rising edge of the output data signal and
`writing odd number data of the data input signal into a
`second latch in response to a falling edge of the output data
`strobe signal.
`Exemplary embodiments of the present invention are also
`directed to a method of controlling propagation delay time
`of a semiconductor memory, including receiving an inverse
`data signal or a reference voltage, respectively, depending
`on a level of a control signal, receiving a data signal and
`either the inverse data signal or the reference voltage, and
`amplifying and outputting at least two different differentially
`amplified signals.
`In exemplary embodiments of the method of the present
`invention, the inverse data signal is an inverse data strobe
`signal and the data signal is a data strobe signal.
`In exemplary embodiments of the method of the present
`invention, in a single mode, the reference voltage is received
`and a level of the control signal is a first logic state and in
`60 a dual mode, the inverse data strobe signal is received and
`the level of the control signal is a second logic state.
`In exemplary embodiments of the method of the present
`invention, the control signal is received from an external
`source.
`In exemplary embodiments of the method of the present
`invention, the method also includes receiving an external
`command and an address and generating the control signal,
`
`NVIDIA Corp.
`Exhibit 1103
`Page 016
`
`

`

`US 6,819,602 B2
`
`6
`data input signal into a second latch in response to a falling
`edge of the output data strobe signal.
`In exemplary embodiments of the method of the present
`invention, the first latch includes a plurality of latches and a
`5 plurality of switches, arranged alternatively.
`In exemplary embodiments of the method of the present
`invention, the plurality of switches are arranged to be
`triggered on the leading and falling edge of an inverse of the
`differential output signal.
`In exemplary embodiments of the method of the present
`invention, a first switch receives the even number data of the
`output signal and passes the even number data of the output
`signal to a first of the plurality of latches.
`In exemplary embodiments of the method of the present
`15 invention, the second latch includes a plurality of latches and
`a plurality of switches, arranged alternatively.
`In exemplary embodiments of the method of the present
`invention, the plurality of switches are arranged to be
`triggered on the leading and falling edge of an inverse of the
`20 differential output signal.
`In exemplary embodiments of the method of the present
`invention, a first switch receives the odd number data of the
`output signal and passes the odd number data of the output
`signal to a first of the plurality of latches.
`In exemplary embodiments of the method of the present
`invention, the data buffer is a data input buffer instead of, or
`in addition to, a data strobe buffer.
`In exemplary embodiments of the method of the present
`invention, the method further includes receiving a data
`30 signal and a reference voltage and outputting a data input
`signal, outputting the control signal, and receiving the data
`input signal and the writing even number data of the data
`input signal into a first latch in response to a rising edge of
`the output data signal and writing odd number data of the
`35 data input signal into a second latch in response to a falling
`edge of the output data strobe signal.
`
`25
`
`5
`wherein a level of the control signal determines an operation
`mode of the semiconductor memory.
`In exemplary embodiments of the method of the present
`invention, a state of a fuse determines a level of the control
`signal.
`In exemplary embodiments of the method of the present
`invention, a connection to Vee or ground via a bonding pad
`determines a level of the control signal.
`In exemplary embodiments of the method of the present
`invention, the amplifying is performed by a single differen- 10
`tial amplifier.
`In exemplary embodiments of the method of the present
`invention, the method further comprises compensating one
`of the inverse data strobe signal, the reference voltage, or the
`data strobe signal or one of the at least two different
`differentially amplified signals so that each of at least two
`differential output signals have substantially the same delay
`time.
`In exemplary embodiments of the method of the present
`invention, the compensating includes receiving the differ(cid:173)
`entially amplified signal and delaying the differentially
`amplified signal, and outputting the differentially amplified
`signal or the delayed differentially amplified signal, as one
`of the at least two differential output signals, depending on
`the level of the control signal.
`In exemplary embodiments of the method of the present
`invention, the compensating is performed with a dummy
`load applied to one of the inverse data strobe signal, the
`reference voltage, or the data strobe signal.
`In exemplary embodiments of the method of the present
`invention, the amplifying is performed by at least two
`differential amplifiers.
`In exemplary embodiments of the method of the present
`invention, a gain of a first of the at least two differential
`amplifiers is substantially different from a gain of a second
`of the at least two differential amplifiers so that each of at
`least two differential output signals have substantially the
`same delay time.
`In exemplary embodiments of the method of the present
`invention, a gain of a first of the at least two differential 40
`amplifiers is substantially the same as a gain of a second of
`the at least two differential amplifiers.
`In exemplary embodiments of the method of the present
`invention, the method further comprises compensating one
`of the inverse data strobe signal, the reference voltage, or the 45
`data strobe signal or one of the at least two different
`differentially amplified signals so that each of at least two
`differential output signals have substantially the same delay
`time.
`In exemplary embodiments of the method of the present 50
`invention, the compensating includes receiving the differ(cid:173)
`entially amplified signal, delaying the differentially ampli(cid:173)
`fied signal, and outputting the differentially amplified signal
`or the delayed differentially amplified signal, as one of the
`at least two differential output signals, depending on the 55
`level of the control signal.
`In exemplary embodiments of the method of the present
`invention, the compensating is performed with a dummy
`load applied to one of the inverse data strobe signal, the
`reference voltage, or the data strobe signal.
`In exemplary embodiments of the method of the present
`invention, the method further includes receiving a data
`signal and a reference voltage and outputting a data input
`signal, outputting the control signal, and receiving the data
`input signal and the writing even number data of the data 65
`input signal into a first latch in response to a rising edge of
`the output data signal and writing odd number data of the
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The present invention will become more apparent by
`describing in detail exemplary embodiments thereof with
`reference to the attached drawings in which:
`FIG. 1 illustrates waveforms produced in accordance with
`the prior art;
`FIG. 2 is a block diagram of a data strobe input buffer
`according to an exemplary embodiment of the present
`invention;
`FIG. 3A is a block diagram of the switches according to
`an exemplary embodiment of the present invention;
`FIG. 3B is a block diagram which illustrates the conver(cid:173)
`sion from the control signal (CNT) to the inverse control
`signal (CNTB) according to an exemplary embodiment of
`the present invention;
`FIG. 4 is a block diagram of a control circuit according to
`an exemplary embodiment of the present invention;
`FIG. SA is a block diagram of a control circuit according
`to another exemplary embodiment of the present invention;
`FIG. SB illustrates a time versus voltage level plot relative
`to VCCH for the exemplary circuit of FIG. SA;
`FIG. 6 is a block diagram of another control circuit
`according to another exemplary embodiment of the present
`invention;
`FIG. 7 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 8 is a block diagram of the switches according to an
`exemplary embodiment of the present invention;
`
`60
`
`NVIDIA Corp.
`Exhibit 1103
`Page 017
`
`

`

`US 6,819,602 B2
`
`7
`FIG. 9 illustrates waveforms produced in accordance with
`one or more exemplary embodiments of the present inven(cid:173)
`tion;
`FIG. 10 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 11 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 12 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 13 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 14 is a block diagram of a data input buffer according
`to an exemplary embodiment of the present invention;
`FIG. 1S is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 16 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 17 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 18 is a block diagram of a data input buffer according 25
`to another exemplary embodiment of the present invention;
`FIG. 19 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 20 is a block diagram of a semiconductor memory 30
`device according to an exemplary embodiment of the
`present invention;
`FIG. 21 illustrates the output of the data strobe signal
`(DQS) and the data signal (DQ) during DDR operation
`according to a semiconductor memory device according to
`an exemplary embodiment of the present invention;
`FIG. 22 is a block diagram of the latch circuit according
`to an exemplary embodiment of the present invention;
`FIG. 23 is a block diagram of a semiconductor memory
`device according to another exemplary embodiment of the 40
`present invention.
`
`35
`
`8
`If the control signal (CNT) is at a "low" logic level, for
`example, if the inverse control signal (CNTB) is at a "high"
`logic level, the switch 212 is turned on, and the switch 211
`is turned off. Accordingly, the differential amplifier 213
`5 differentially amplifies the data strobe signal (DQS) and the
`inverse data strobe signal (DQSB), and the differentially
`amplified signal (DO) is output. This is operation in the dual
`mode (DM).
`FIG. 3A is a block diagram of the switches 211 and 212
`10 according to an exemplary embodiment of the present
`invention, where each switch 211, 212 is implemented as a
`transmission gate. As illustrated, each transmission gate
`receives the control signal (CNT) and the inverse control
`signal (CNTB) and either the inverse data strobe signal
`(DQSB) or the reference voltage (VREF). As also
`15 illustrated, according to an exemplary embodiment of the
`present invention, the transmission gates are triggered by the
`leading edge of a pulse of the control signal (CNT) and the
`inverse control signal (CNTB). FIG. 3B is a block diagram
`which illustrates the conversion from the control signal
`20 (CNT) to the inverse control signal (CNTB) performed by
`an inverter gate.
`The data strobe input buffer 13 according to the exem-
`plary embodiments of the present invention described above
`may be incorporated into a semiconductor memory device,
`such as an SDRAM. The data strobe inp