EXHIBIT 1013
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`EXHIBIT 1013EXHIBIT 1013EXHIBIT 1013
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`UNITED STY.,. o~S DEPARTMENT OF COMMERCE
`Patent and Trademark Office
`Addre~: COMMISSIONER OF PATIENTS AND TRADEMARKS
`Washington, D.C. 20231
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`APPLICATION NO.
`i<,~f~:/~ ;1.2’ 7 ,;"2
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`I FILING DATE I
`r<’ ], IfZi-21’?G
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`FIRST NAMED INVENTOR
`f’,AI.~EF,.’Kt.’"
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`I A’ITORNEY DOCKET NO. I
`r;._.’:~.l 4-
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`l’.i
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`Pleaee find below and/or attached an Office communication concerning this application or
`pro©eeding.
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`Commissioner of Patents and Trademarks
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`Microsemi 1013
`Page 001 of 010
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`O81612,772
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`Examiner
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`1 Application No.
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`I Applicant(s)
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`I
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`Norbert Daberko
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`Office Action Summary
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`[] Responsive to communication(s) filed on
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`[] This action is FINAL.
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`Jean M, Corrielus
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`2307
`1 Group Art Unit
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`[] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is closed
`in accordance with the practice under Ex parte Quay/e, 1935 C.D. 11 ; 453 O.G. 213.
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`A shortened statutory period for response to this action is set to expire 3 month[s}, or thirty days, whichever
`is longer, from the mailing ~iate of this communicate’on, Failure to respond within the period for response will cause ’the
`application to become abandoned. (35 U.S,C, § 1331. Extensions of time may be obtained under the provisions of
`37 CFR 1,136(a],
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`Disposition of Claims
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`[] Claim(s) 1-25
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`Of the above, claim(s)
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`[] Claim(s)
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`[] Claim(s) 1-16 and 20-25
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`[] Claim(s) 17-19
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`[] Claims
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`Application Papers
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`is/ere pending in the application.
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`is/ere withdrawn from consideration.
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`is/are allowed,
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`islare rejected.
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`is/ere objected to.
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`are subject to restriction or election requirement.
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`[] See the attached Notice of Draftsperson’s Patent Drawing Review, PT0-948,
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`[] The drawing(s) filed on
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`is/are objected to by the Examiner.
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`[] The proposed drawing correction, flied on
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`is [] approved
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`[] disapproved,
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`[] The specification is objected to by the Examiner.
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`[] The oath or declaration is objected to by the Examiner,
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`Priority under 35 U.S,C. § 119
`[] Acknowledgement is made of a claim for foreign priority under 35 U.S.C. § 119(a}-(dL
`[] All [] Some* [] None of the CERTIFIED copies of ~e priority documents have been
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`[] received,
`[] received in Application No, (Series Code/Serial Numberl
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`[] received tn this national stage application from the lnternationat Bureau (PCT Rule 17,2(a)).
`~Cer~ified cop(as not received;
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`[] Acknowledgement is made of a claim for domestic priority under 35 U.S.C. § 119(e}.
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`Attachment(s)
`[] Notice of References Cited, PT0-892
`[] Information Disclosure Statement(s), PTO-1449, Paper No(s),
`[] interview Summary, PT0-413
`[] Notice of Dreftsperson’s Patent Drawing Review, PT0-948
`[] Notice of Informal Patent Application, PTO-152
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`4
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`PT0-326 (Rev. 9-95}
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`Office Action Summary
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`Part of Paper No. 5
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`-- SEE OFFICE ACTION ON THE FOLLOWING PAGES --
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`Microsemi 1013
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`Serial Number: 08/612,772:
`Art Unit: 2307:
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`DETAILED ACTION
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`-2-
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`The title of the invention is not descriptive. A new title is required that is clearly indicative
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`the invention to which the claims are directed.
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`2. The information disclosure statement flied on 3/7/96 complies with the provisions of
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`MPEP S 609. It has been placed in the ap!0Iication file, the information referred to therein has
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`been considered as to the merits.
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`Dmun’n~
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`3. This application has been filed with informal dra~4ngs which are acceptable for examination
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`p~rposes only. Formal drawings will be required when the application is allowed.
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`C~aim Rejections - 35 USC ~ 103
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`4. The following is a quotation of 35 U.S.C. 103 Ia) which forms the basis for al! obviousness
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`rejections set forth in this Office action:
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`(a) A patent may not be ol~tained though the invention is not identically d~sclosed or described as set forth in
`section 102 af tils title, ff the diffen~nces between the su~bject matter sought to be patented and the p~ior art ave
`such that tim su]~jeo~ matte~ as a whole wo~!d haw ~en obvious at the tla*e the invention was made to a person
`having ordina~ sl~fl in the art to which said su]~jec~ matter pertains. Patentability shall not be negatived by the
`manner in which the invention was made.
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`Serial Number: 08/612,772:
`Art Unit: 2307:
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`-3-
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`5. The factual inquiries set forth in Graham v. John Deere Co., 148 USPQ 459, that are
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`applied for establishing a background ~or determining obviousness under 35 U.S.C. 103(a) are
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`summarized as follows:
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`1.
`2.
`3.
`4.
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`Determining the scope and contents of the prior art.
`Ascertaining the differences between the prior ar~ and the claims at issue.
`Resolving the tevel of ordinary skill in the pertinent art.
`Considgring objective evidence present in Uae application indicating obviousness or
`LLYIO~OI/~ IlesS.
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`6. Claims 1-6, 10 and 20-21 are rejected under 35 U.S.C. 103(a) as being unpatentable over
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`Lasker et al. USP no. 5,586,291 (hereina~er "Lasker") in view of ~effrey et aL (Book entitled
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`"Data structure").
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`As to claims 1, Lasker disclosed a primary mirror non-volatile module (col.4, lines 50-55); Lasker
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`detail that a cache memory can include several non-volatile memory module in order to preserve
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`data integrity of the system in the event of a system po~er failure (col.3, lines 19-30); and move
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`the new data segment from the cache to a next available space (col.4, lines 26-32), Lasker"
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`described that by de-allocating the memory blocks of non-volatile memory immediately a~ter the
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`data written to disk, the data integrity van be improved; I.asker also detail all generations of data
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`are written from the write cache to read cache and the write operations are done in the same order
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`as which they are received (col.5, lines 2-12). However, Lasker did not exphcitly detail the steps
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`of ereatlng a logical link between the previous logical data segment and creating additional serial
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`and logical links.
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`Microsemi 1013
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`Serial Number: 08/612,772:
`Art Unit: 2307:
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`-4-
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`Jeffrey et al. disclosed a method for maintaining data elements in memory which are stored in a
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`llnked-llst (pages 56-57); Jeffrey et al. also detailed that a file allocatlon table is a linked list that
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`map the file to the sector allocated to a particular file and points to the next link. It is noted that
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`DOS system includes typically saves the file allocation table on the disk with which the table is
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`associated. It would have been obvious to one ha,cing skill in the art at the time of the invention
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`to have combined the teachings of Jeffrey ~,~t al. with the system of Lasker because such of
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`combination wo~d have allowed memory at-ray to operate more efficiently.
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`As to claims 2-4:
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`Jeffrey et al. disclosed a list that moves backwards as well as forwards (doYle linked list) from a
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`current data segment to other serially and logically linked data segments and points to at least one
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`data segment when it is the current data segment (pages t84-185). It is noted that linked
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`structures, like the double linked list usually have several pointers associated with them, these
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`pointers act as place markers maintaining contact w~th the beginning of a list, its end, the current
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`position, location of the next data segment.
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`Serial Number: 08/612,772:
`~Art Unit: 2307:
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`As to claims 5-6:
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`-5-
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`Stack is inherently well known in the computer technology, it uses to implement a linked list in
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`a data structure. It should ~ also noted that Pop and Push are two basic well known stack
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`operations; one skilled in the art in order to reverse a stack must pop each element (remove it from
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`the beginning) and p~h it (insert it at the beginning) onto another stack; so that the character can
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`then be popped from the second stack and printed in the order they are popped¯
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`As to’claim 10:
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`)’effrey et al. disclosed the steps of:
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`appending a header to new data segments when writing the new data segments to primary memory
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`by mo~ing th~ new data segment from the cache memory to the next available contiguous memory
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`space (pages 61-62); includlng in the header at least one address pointer so as to logically link the
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`header to other data segments (page 62)..
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`As to claims 20-21:
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`It is inherent that the file system is a portion of an operating system that translates requests for
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`file operations from an application into low-level or includes application program instructions wkich
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`execute f~nctions of the file system which are compatible with DOS. It is noted that a BIOS is
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`a set of routines that work closely with the hardware to support the transfer of information between
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`elements of the system, such as memory, disk ..etc. Therefore a file system is primarily
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`incorporated in the BIOS.
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`Serial Number: 08/612,772:
`Art Unit: 2307:
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`-6-
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`7. Cla~s 7-9, 11-16 and 22-25 are rejected under 35 U.S.C. i03(a) as being unpatenta~le
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`over Lasher in view of Jeffrey et al. as applied to claim 1 above, and fuxther in view of Ban USP
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`no. 5,404,485.
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`As to claims 7-9:
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`The limitations of these claims have been mentioned in the rejection of claim 1 above. However,
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`Lasker and Jeffrey did not explicitly detail the steps of selecting flash memory.
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`Ban disclosed the steps of selecting flash memory (fig. 1, item 12); NAND is inherently well known
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`logical operator uses in the flash memory; Ban also detailed the step of coupling a RAM to a flash
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`memory (fig.l, item 16) (it is noted that a RAM can be read and written by the
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`microprocessor and it is often used synonymously with the term physical memory or
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`primary memory to refer to the memory actually present in a computer system). It would
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`have been obvious to one having ordinary skill in the art at the time of the invention to have
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`incorporated the teachings of Ban into the system of Lasker and Jeffrey et al. because that would
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`have allowed flash memory to emulate random access memory. Also, because that wouJd have
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`allowed existing computer operation systems to provide all other required support in the same
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`manner provided by the standard random access memories.
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`As claim 13:
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`Ban disclosed the steps of including within the header an idenfitication field (it noted that a header
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`is an idenfication field stored the loglcal sector number, used by the operating system) (col.4, lines
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`38- 0).
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`Serial Number: 08/612,772:
`Art Unit: 2307:
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`AS to clah~s 11-12:
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`-7-
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`Ban di,~losed the steps of selecting a header fi:om the group (fig.3) and selecting a header-like det~
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`structure (fig.3).
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`As to c|aims I4-15:
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`Ban disclosed the steps of reserving a fixed amount memory (col.2, ~ines 61-64; col.4, l~nes 12-
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`31).
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`As to clahn 16:
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`Jeffrky disclosed the steps of creating at least one tree node including a next tree node address
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`pointer (page 61); creating at least one tree node including a next tree node address pointer (page
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`61).
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`As ~ clahns 22-25.’
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`Ban disclosed the steps of: creating a logical block (col.5, lines 5-12); creating a logical memory
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`block maps (eokS, lines 3-4, 17-35); creating a logical block control map including a physical
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`address (col.5, lines 36-51).
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`Microsemi 1013
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`Serial Number: 08/612,772:
`Art Unit: 2307:
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`-8-
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`8. Chinas 17-19 are obieeted to as being dependent upon a reiected base chim, but would be
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`allowable if rewritten in independent form including all of the limitations of the base claim and any
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`intervening claims.
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`Conclusion
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`9. The prior art made of record and not relied upon is considered pertinent to applicant’s
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`disclosure. (See PTO-892)
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`Any inquiry concerning this communication or early communication ~rom the
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`Examiner should directed to Jean Corrielus whose telephone number is (703) 306-3035. The
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`Examiner can normally be reached on the weekday~ f~om 7:00am to 3:00pro. If attempts to
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`reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Thomas G.
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`Black, can be reached on (703)305-9707. The fax phone number for this group is (7.03)308-
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`5357.
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`Any inquiry of a general nature or relating to thas apphcation should be directed to the
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`group receptionist whose telephone number ~s (703)305-9600.
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`)ean M. Corviel~s
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`Patent Examiner
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`June 18, 1997
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`Microsemi 1013
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`~N~, t!ce of References Cited
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`DOCUMENT NO.
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`DArE
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`5.404,~,85
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`5,200,959
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`5,341,330
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`5,551,020
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`5,454,103
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`5,602,987
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`5,586,291
`
`5,357,~-75
`
`5,581,736
`
`4,685,057
`
`5,263,160
`
`04104195
`
`04106t93
`
`09/23/94
`
`08127/96
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`09/26t95
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`02/11197
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`12117/96
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`10/t 8f94
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`12103t95
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`08t04f87
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`11116193
`
`U.S, PATENT DOCUMENTS
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`NAME
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`Ban
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`Gross et el.
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`Wells et
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`Flex et
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`Covers’ton et el.
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`Harari et
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`Leaker at el.
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`Hasbun et el.
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`Smith
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`Lemons et
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`Porter et el,
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`Page I o! 1
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`SUBCLASS
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`425
`
`21.6
`
`18 L.._~
`
`600
`
`182.08
`
`440
`
`2!8
`
`497.01
`
`200
`
`500
`
`395
`
`37!
`
`355
`
`395
`
`395
`
`395
`
`395
`
`365
`
`395
`
`395
`
`FOREIGN PATENT DOCUMENTS
`
`DArE
`
`CLASS
`
`A
`
`,S
`
`:D
`
`E
`
`F
`
`J
`
`K
`
`M
`
`N
`
`0
`
`P
`
`o
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`R
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`s
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`T
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`NON-PATENT DOCUMENTS
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`DOCUMENT {Ineludll~ Author, Tit~, Sex=roe, and Pe~l~ent Page=}
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`William Pugh, "Skip List: A Probabilistic alternative to balance trees", communication of the ACM vol.33,
`no.6, pp 668-676
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`I i Robert Sadgewick "Algorithms". Addison -Wesley publishing Co. pp 15-33
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`Jeffrey et el. "Data structures", Prentice-Hall, Inc, pp 84-65, 184-191
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`Alfred et at. "Data structure and algorithms" Addison-Wesley Publishing Co., pp. 53-69
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`DArE
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`08190
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`00188
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`00/89
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`00183
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`U. S. Patent and Trademark Office
`PT0-892 (Ray. 9-951
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`Notice of References Cited
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`Part of Paper No. 5
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`Microsemi 1013
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