By: Christopher Frerking (chris@ntknet.com)
`
`Reg. No. 42,557
`
`
`
`
`Paper No. __
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`AMERICAN MEGATRENDS, INC., MICRO-STAR INTERNATIONAL CO.,
`LTD, MSI COMPUTER CORP., GIGA-BYTE TECHNOLOGY CO., LTD., AND
`G.B.T., INC.
`
`
`
`Petitioners
`
`v.
`
`KINGLITE HOLDINGS LLC
`
`Patent Owner
`
`CASE IPR2015-01094
`U.S. Patent No. 6,401,202
`
`DECLARATION OF SHAHIN NAZARIAN, Ph.D.
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`I, Dr. Shahin Nazarian, do hereby declare under penalty of perjury as follows:
`
`
`
`1.
`
`I am an Associate Professor of Engineering Practice at the University of
`
`Southern California’s Ming Hsieh Department of Electrical Engineering, a position
`
`that I have held since January 2009. I currently teach classes in digital design
`
`(namely USC courses: EE101, EE109, and EE209), VLSI design (e.g., EE477L,
`
`EE577A, and EE577B), embedded system design and SoC (System-on-Chip)
`
`design (EE454), verification of VLSI systems (EE599), computer networks (EE450)
`
`and computer architecture (EE352, and EE357).
`
`2.
`
`I began my industrial experiences, as a design engineer in Tehran back in
`
`May 1993, with focus on logic design using microcontrollers. I continued to work
`
`in system level design and circuit design in various fields such as sonar, and
`
`wireless, using microprocessors and microcontrollers until May 2000, when I
`
`pursued my Ph.D. in electrical engineering with major focus on VLSI and CAD
`
`(Computer-Aided Design) design and verification, and minor in Computer Science,
`
`and received my degree at the University of Southern California, in September 2006.
`
`3.
`
`As a Ph.D. student I took several courses related to computer science and
`
`engineering, such computer architecture, operating systems, algorithm design,
`
`database systems, computer-aided design, digital system testing, security and
`
`cryptography, etc. I also have research and teaching experiences and more than 50
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`research papers on many related topics, such as cloud computing, algorithm design,
`
`data centers, task scheduling, timing and power optimization of computing systems,
`
`since 2009. I am a co-author of a recent research paper related scheduling and
`
`optimization which received a Best Paper Nomination (T. Cui, et al., “Optimal Co-
`
`Scheduling of HVAC Control and Battery Management for Energy-Efficient
`
`Buildings Considering State-of-Health Degradation,” ASP-DAC, Jan. 2016).
`
`4.
`
`As part of my Ph.D. program, I took a Ph.D. screening examination, where I
`
`had to pass written and oral exams related to Operating Systems (mainly the subjects
`
`of a the Operating Systems (CS402) course), Computer Architecture and
`
`Organization (mainly the subjects of EE457 and EE557), Computer Networks
`
`(EE450), Data Structure (mainly related to CS570 and CS585), Digital System
`
`Testing (EE658), Computer-Aided Design and Algorithm Design (mainly related to
`
`EE680 and CS570).
`
`5.
`
`I have more than nine years of industrial experience as a research scientist,
`
`software and hardware design engineer in a wide range of areas.
`
`6.
`
`Attached hereto as Exhibit A is my curriculum vitae, which sets forth my
`
`educational background, employment history, and publications. I have not
`
`previously offered testimony as an expert.
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`7.
`
`I have been retained by the patent owner, Kinglite Holdings LLC
`
`(“Kinglite”) as an independent expert consultant in this proceeding before the U.S.
`
`Patent and Trademark Office. I am being compensated for the time I spend on this
`
`matter, at the rate of $250 per hour, but no part of my compensation is dependent on
`
`the outcome of this proceeding.
`
`8.
`
`I understand that this proceeding involves the U.S. Patent No. 6,401,202 B1
`
`(“the ‘202 patent”). In addition to my own technical knowledge regarding the
`
`subject matter of the ‘202 patent, I have reviewed and relied upon various
`
`documents provided to me by counsel in formulating my opinions in this matter.
`
`Those documents are cited herein.
`
`9.
`
`I understand that the application for the ’202 patent was filed on June 18,
`
`1999, as U.S. Patent Application No. 09/336,110 (“the ’110 application”), and that
`
`the patent issued on June 4, 2002. I have therefore considered the state of the art and
`
`the prior art available as of June 18, 1999.
`
`10.
`
`I have been asked to consider the process of multi-tasking during BIOS
`
`boot-up represented in the ’202 patent and to compare this process to the prior art
`
`available as of June 18, 1999. My opinions are provided below.
`
`11.
`
`In computer science and architecture, a “task” is a basic unit of programming
`
`that an Operating System (OS) controls. Depending on how the OS defines a task in
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`its design, this unit of programming may be an entire program or each successive
`
`invocation of a program.
`
`12. To
`
`increase
`
`the
`
`performance
`
`of
`
`computing
`
`systems,
`
`multiple tasks (also processes, or threads) can be performed in parallel over a certain
`
`period of time by executing them concurrently. New tasks start and may interrupt an
`
`already started task before it has reached completion, instead of executing the tasks
`
`sequentially so each started task needs to reach its end before a new one is started.
`
`As a result, a computer executes segments of multiple tasks in an interleaved manner,
`
`while the tasks share common processing resources such as central processing
`
`units (CPUs) and main memory.
`
`13. All of today’s widely used OS platforms support multitasking, which allows
`
`multiple tasks to run concurrently, taking turns using the resources of the computer.
`
`However based on my understanding of the prior art, the concept was multitasking
`
`during boot-up, was first invented by the ‘202 patent in June 18, 1999.
`
`14. The concept of multitasking in the x86 architecture that AMIBIOS 8 was
`
`written for, is similar to other architectures (Ex 1011, 39). That is, tasks are not really
`
`executed concurrently. They can be time-sliced. Noting that a task may be one or
`
`more instructions in software, a simple example would be multitasking two three-
`
`instruction tasks,
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`15.
`
`In the x86 architecture all PCs and PS/2s supported by AMIBIOS 8, the input
`
`oscillator to the system timer circuit has a frequency of 1.19318 MHz. On each cycle,
`
`the timer chip decrements the values in a set of internal 16-bit counters, one for each
`
`of the timer's output channels. When the value in a counter reaches 0, the chip
`
`generates a single output pulse on the corresponding channel, resets the count, and
`
`starts counting down again.
`
`16. The timer pulse explained in the previous paragraph is called a timer tick. As
`
`long as the real time clock battery on a PC systems motherboard is active. This real
`
`time clock RTC system task pulses every 55ms or about 18.2 ticks per second,
`
`whether or not the PC system itself is powered up or powered down. Clearly this
`
`includes whether or not the CPU is active on the bus, and whether or not AMIBIOS
`
`8 is running.
`
`17. The tick pulse is not enabled or configured by AMIBIOS 8. The pulse duration
`
`is determined by the count register on the system timer. The timer chip decrements
`
`the counter 216 times between output pulses, so output pulses occur every “timer-
`
`frequency in MHz” divided by “64K limit of a 16-bit register.” That is
`
`1,193,180/65,536, or about 18.2 ticks per second. This time interval is not
`
`determined by any AMIBIOS 8 interrupt code and persists even when the system is
`
`off. Nor is it determined by any function in the CPU since the CPU is not powered
`
`by the real time clock battery Ex. 2004.
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`18. While the PC (and CPU) is powered off, this timer will increment registers
`
`stored in CMOS that represent seconds, minutes, hours, and so forth, as shows in the
`
`following depictions:
`
`Register Contents
` 0x00 Seconds
` 0x02 Minutes
` 0x04 Hours
` 0x06 Weekday
` 0x07 Day of Month
` 0x08 Month
` 0x09 Year
` 0x32 Century (maybe)
` 0x0A Status Register A
` 0x0B Status Register B
`
`
`
`
`
`
`
`
`
`TASK B
`
`
`TASK A
`
`
`
`19. Without multitasking, TASK A will run to completion before TASK B
`
`begins. If each task contains three instructions, TASK A would serially run its
`
`three instructions and then TASK B would run its three instructions. With
`
`multitasking, if TASK A and TASK B were 30 instructions each, this same drawing
`
`would depict a slice of time where either the three instructions from TASK A or the
`
`three instructions of TASK B could be executed next.
`
`20. This basic multitasking requires two things: 1) A time slicing mechanism
`
`that can segment TASK A and TASK B into manageable portions of a task; and 2)
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`A monitor program that knows what tasks may be run at this particular time slice
`
`and makes the decision how and when to choose one instead of the other. Ex.
`
`2007 at 101-110 (discussing time slicing and monitoring system events of virtual
`
`machines); Ex. 2008 at 1497-1506 (finding algorithms to determine which tasks to
`
`schedule next).
`
`21. Time slicing is done in x86 architecture by a specific hardware interrupt. A
`
`hardware interrupt can be looked at as kind of a panic button initiated by a device
`
`that will demand the CPUs attention, such as RTC. Independent of the CPU, RTC
`
`will always execute the timer control tasks to CMOS. These housekeeping routines
`
`in CMOS are how a PC can maintain a calendar date many years after being
`
`plugged in.
`
`22. The RTC-based interrupt is called the tick timer. Whenever the BIOS is
`
`initialized, it recognizes the timer tick pulse on the system bus, and registers it as
`
`an interrupt. By registering an interrupt, the AMIBIOS 8 can assign an interrupt
`
`service routine to that interrupt. AMIBIOS 8 teaches this ISR must execute
`
`housekeeping (copy CMOS kept time/date). This housekeeping task is always
`
`scheduled and must always complete before a successive timer tick.
`
`23. This standard timer is not generated by AMIBIOS 8. Rather, an interrupt
`
`service routine is triggered by the timer pulse every 55ms. Ex 1001 at 12:1-5. The
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`interrupt service routine that AMIBIOS 8 describes will always execute timer
`
`control tasks (clock housekeeping), then, with the INT 1Ch software interrupt
`
`AMIBIOS 8 may create a timer to run a first task, such as an animation frame or
`
`disk shutdown.
`
`24.
`
`It should be noted the INT 1Ch is the only way taught by AMIBIOS 8 to run
`
`a first task between successive ticks. The Petitioner points to the 08H INT itself
`
`teaching all the timer elements of the ‘202 patent claims. However a timer in the
`
`‘202 claims must have an interrupt disable code. AMIBIOS 8 does not teach any
`
`way to disable the 08H INT.
`
`25. Petitioners also point to the INT 08 clock housekeeping tasks as a “first
`
`task.” However, a first task in the ‘202 patent claims can be disabled. AMIBIOS 8
`
`teaches that these tasks must always complete between successive INT 08
`
`intervals. Furthermore, these housekeeping tasks are performed very quickly. In
`
`fact, similar real time housekeeping tasks are performed 1024 times a second by
`
`the CMOS RTC.
`
`26. The CPU is on the same bus as the CMOS RTC. As the CPU is powered up
`
`and initialized, the BIOS recognizes this tick timer as a hardware interrupt with
`
`certain controls. In order for this tick timer interrupt to be a periodic interval timer
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`for time-slicing mechanisms, as described in the ‘202 patent claims, or for any
`
`non-mandatory task, it must be configured to generate a software interrupt.
`
`27. BIOS can use the INT 1Ch periodic interval timer controls in the tick timer
`
`to set a cadence for a time slicing mechanism. As Dr. Sartori recognizes, without
`
`that control, the standard timer cannot be used for time slicing, because AMIBIOS
`
`8 teaches that is the method to start a task between INT 08H interrupts Ex. 2006 at
`
`35:19-26 and 36: 1-6 Not only is the INT 1Ch the only configurable control of the
`
`tick timer taught by AMIBIOS 8, it is the method AMIBIOS 8 teaches to enable or
`
`configure a cadence, e.g., to configure the interrupt generator. As shown below,
`
`AMIBIOS 8 teaches the periodic interval timer INT 1Ch can be configured by
`
`BIOS to enable or configure interrupt signals at predetermined interrupt times as a
`
`time slicing mechanism. The timer-tick has the highest priority of any of the
`
`hardware interrupts, so any tasks in the corresponding interrupt 08h and 1Ch are
`
`not interruptible and take precedence over all other system software. Ex. 2004 at
`
`page 5.
`
`28. Likewise, the standard timer of the ‘202 patent claims must use the same
`
`periodic interval timer INT 1Ch to configure an appropriate time slicing
`
`mechanism. As shown in Figure 6 of the ‘202 patent, this mechanism occurs before
`
`any first task. Ex. 1001 at Fig. 6
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`29. The second requirement for multitasking is a process that will monitor the
`
`tasks that are available to run once a time slice occurs, and to make a decision
`
`regarding which among multiple tasks to run.
`
`30. As Dr. Sartori recognizes, AMIBIOS 8 did not invent the system timer
`
`interrupt. Ex1010,¶ 58. It merely describes this well-known x86 architectural
`
`element. The hardware interrupt itself has a preset interval of 18.2 times a second
`
`that occurs whether or not the CPU is powered up. This predetermined tick time is
`
`unalterable and cannot be configured. The only way to configure or enable this tick
`
`timer with a cadence for a predetermined time interval is by using the periodic
`
`interval timer INT 1Ch.
`
`31. Mr. Sartori describes the teachings on page 89 of the AMIBIOS as a process
`
`that can supply a timer function like updating the dates, or, attention due to an
`
`external event that has to happen at a certain cadence, number of milliseconds. Ex.
`
`2006 at 53:7-18. As described in AMBIOS, the system timer calls INT 08h 18.2
`
`times per second. Ex. 1003 at 340. It is important to note that this predetermined
`
`time (18.2 times per second) is fixed and not shown to be configurable anywhere in
`
`AMIBIOS.
`
`32.
`
`In AMIBIOS, the Petitioners erroneously use this 18.2 times a second of the
`
`system timer as the “configured” time interval element. As stated, this is a
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`predetermined time interval of the x86 architecture system timer. This time
`
`interval is configurable only to some multiple of this 18.2 times a second. In other
`
`words, in my opinion, AMIBIOS does not explain specifically how set to a
`
`predetermined time cadence.
`
`33. Motor Wait Time is the length of time a floppy drive can be inactive before
`
`the drive motor is shut off. This value ranges from 0 to 255 in increments of 1.
`
`The timer ticks approximately 18.2 times per second. The Motor Wait Time value
`
`can be calculated as follows: TIME = Selected timer tick value divided by 18.2.
`
`Ex. 1003 at 30.
`
`34. From the teachings of AMIBIOS, a person or ordinary skill may understand
`
`how to configure an interrupt controller with signals at predetermined interrupt
`
`times using the INT 1Ch period interrupt timer. AMIBIOS, however, is silent on
`
`every other claim element, and, particularly, does not describe any time-slicing
`
`process that monitors which, if any, tasks are available to run once an interval
`
`occurs. AMIBIOS also says nothing about making a decision regarding whether to
`
`perform/continue a second task before the next successive interrupt (tick), or if a
`
`normal second task is performing, and not completed a decision to check for
`
`interrupts to ensure that no tick is missed as shown in figure 6 645 and decision
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`blocks 630 and 645. Ex. 1001 at Fig. 6. Missing a timer tick may cause a system
`
`crash. Ex. 2003 at page 2, Ex. 2004 at page 5.
`
`35. The petitioners also cite to the AMIBIOS date-keeping system tasks that a
`
`system timer always performs as a first task. However AMIBIOS shows these tasks
`
`as not alterable, mandatory and uninterruptable. That is they cannot be reordered
`
`or have any other tasks substituted for them. Consequently, these are tasks that
`
`always occur, and they cannot be multitasked or interleaved with other tasks.
`
`36. A process that configures the interrupt generator using periodic interval
`
`timer INT 1Ch can also monitor and run tasks of its own, e.g., an animation, since
`
`it can run application programs based upon a particular cadence. So, while a “task”
`
`may include setting up a timer, according to the Board’s construction, the “first
`
`task” in AMIBIOS does not occur until scheduled by the INT 1Ch.
`
`37.
`
`In sum, a person of ordinary skill in the art reading AMIBIOS, in my
`
`opinion, may learn how to access the system timer through the INT 1Ch interrupt
`
`to set up a timer cadence, and how to schedule a first task using that interrupt.
`
`That person would not learn about a monitoring program, or that multiple tasks can
`
`be run in a multitasking manner.
`
`38. The Pearce reference configures a predetermined time interval for an
`
`interrupt by setting a cadence in the system timer. As stated above with regard to
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`AMIBIOS, this is the only method available in BIOS to configure a timer. Unlike
`
`AMIBIOS, Pearce also describes a process that will monitor a data structure used
`
`as a signal that indicates which XBIOS tasks are available to run once the system
`
`enters system management mode (SMM), and once a time slice occurs.
`
`39. SMM is intended to be used for advanced power management features and
`
`other functions independent of the operating system. SMM performs such
`
`functions in a way that is completely independent of the operating system
`
`environment, or the operating mode of the microprocessor. See Ex. 2005 at page 2.
`
`In other words, the SMI Handler has complete control of system and the
`
`interrupted application program will be suspended until it completes.
`
`40. Pearce’s monitor and signal exist to allow communication from an operating
`
`system application and SMM BIOS functions. It does not make any determination
`
`during SMM whether to run one task or another - only whether to run additional
`
`tasks. Pearce’s’ monitor merely determines if there is an XBIOS task flagged.
`
`There is no determination whether to run a task if the XBIOS task is flagged.
`
`There is no determination as between a first and second task whether to interleave
`
`or reorder such tasks, or whether to run one task instead of the other.
`
`
`
`
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`
`
`I hereby acknowledge that any willful false statement made in this declaration
`
`is punishable under 18 U.S.C. 1001 by fine or imprisonment, or both, and may
`
`jeopardize any proceeding in which this declaration is presented.
`
`
`
`
`
`
`
`
`
`
`
`
`
`Date: February 8, 2016
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`By:
`
`Shahin Nazarian
`
`
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`
`
`
`
`Exhibit A
`
`
`Exhibit A
`
`
`
`EXHIBIT 2002
`
`IPR2015-01094
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`
`
`SHAHIN NAZARIAN
`
`Associate Professor of Engineering Practice
`Department of Electrical Engineering
`Viterbi School of Engineering
`University of Southern California
`3740 McClintock Ave
`Los Angeles, CA
`Office: (626) 200 7893
`Mobile: (213) 740 4653
`Email: shahin@usc.edu
`URL: http://ee.usc.edu/faculty_staff/faculty_directory/nazarian.htm
`
`
`EDUCATION
`
`Ph.D. in Electrical Engineering, University of Southern California, Los Angeles, CA
`Minor: Computer Science
`
`MSCENG in Computer Engineering, University of Southern California, Los Angeles, CA
`5/04
`Emphasis: VLSI/ASIC design
`
`M.Sc. in Electrical Engineering – Electronics, University of Tehran (UT), Tehran
`
`9/06
`
`
`6/99
`
`
`3/96
`
`
`B.Sc. in Electrical Engineering – Electronics, Tehran Polytechnic, Tehran
`
`
`
`
`
`
`
`WORK EXPERIENCE
`
`1/09 – Present
`
`University of Southern California, Los Angeles, CA
`Associate Professor of Engineering Practice
`- Teaching undergraduate/graduate courses in Computer/Electrical Engineering: Verification of VLSI System
`(EE599-Special Topics), VLSI System Design (EE577A and B), MOS VLSI Design (EE477L), Foundations of
`Digital System Design (EE209), Introduction to Embedded Systems (EE109), Logic Design (EE101),
`Computer Networks (EE450), Introduction
`to SoC (EE499-Special Topics-currently: EE454), Basic
`Organization of Computer Systems (EE357), and Computer Organization and Architecture (EE352)
`- Advising Directed Research (EE590) students, currently on the topics of low power design, power
`optimization, signal integrity analysis and optimization, green technology design, MOS VLSI/CAD, smart grid,
`near/sub-threshold CMOS, memory design, neuromorphic computing
`- Supervising graduate students during their internship who are registered for ENGR596
`- A member of the CENG Ph.D. screening exam committee: designing the written exams (for Computer
`Networks, EE450) and oral exams (for CAD/VLSI courses EE477L, EE577A/EE658/EE680)
`- Designing the placements exams for EE450 (Computer Networks)
`- Writing recommendation letters for undergraduate/graduate USC students for their industrial and academic
`applications, and also helping them with their resume and interview preparation
`- Reviewer for IEEE Trans. on Computer Aided Design (TCAD), IEEE Trans. on Very Large Scale Integration
`(TVLSI), Journal of Lower Power Electronics (JOLPE), and Journal of Circuits, Systems and Signal
`Processing, Design and Test
`- Reviewer for different design automation conferences, including Design Automation Conf., International
`Conference on Computer Aided Design, and Design Automation and Test in Europe, International
`Symposium on Low Power Electronic and Design
`
`
`
`
`
`
`
`
`
`1
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`Quandary Peak Research, Beverly Hills, CA
`Senior Research Scientist in Electrical and Computer Engineering
`- Worked as an expert on various cases related to operating systems, power management,
`firmware, computer architecture, wearable technologies, memory interfaces.
`
`
`2/15 – Present
`
`
`
`
`Magma Design Automation, San Jose, CA
`Senior Member of Technical Staff
`- Was involved in various projects in the Signal Integrity and Timer groups, such as multi-model multi corner timing
`analysis, on-chip variation consideration, as well as crosstalk delay and slew correlation issues
`- Was also involved in Current Source Model(CSM)-based timing tool development and also the main person to
`develop the first generation of CSM noise tool in Magma. (Tcl, C++, Hspice, Purifty)
`
`
`5/06 – 1/09
`
`
`
`
`
`Magma Design Automation, San Jose, CA
`R&D Design Engineer (Intern)
`- Designed and developed new crosstalk-aware gate delay modeling techniques (Perl, C, Matlab, Hspice)
`- Designed and developed methodologies to enhance the accuracy of Magma’s static and statistical static timing &
`crosstalk noise analysis tools (Tcl, C++, Hspice)
`
`
`5/04-8/04
`
`
`
`Lucent Technologies & Bell Labs Innovations, Holmdel, NJ
`Design Engineer (Intern) in Test Group
`- Developed an IEEE P1500 (SECT - Standard for Embedded Core Test) Wrapper with parallel access for
`Design for Testability (DFT) verification & System-on-Chip (SoC) testing (VHDL)
`- Evaluated
`IEEE1532 standard and compared
`it with 1149.1-based programming methods
`
`
`
`6/03-8/03
`
`
`
`
`
`Pars Mfg. Co., Tehran
`Project Manager in Telecom. R&D Center
`- Supervised the “WLL (Wireless Local Loop) systems installation and maintenance in rural areas” project
`
`6/98-5/00
`
`
`
`Engineering Research Center, Tehran
`R&D Design Engineer
`- Designed and implemented (using MCS-family microcontrollers) the control/computing system of an
`underwater data logger for data conversion and acquisition of several sensors, transducers in Sonar (SOund
`NAvigation and Ranging) systems (Assembly, Protel)
`
`3/96-6/98
`
`Takta Co. (Electronic Research & Production Co.), Tehran
`Design Engineer in Electronics Lab.
`- Designed and implemented (using MCS-48 family µcontrollers) an automatic switch of a TV transmitter to
`keep the system active in the occurrence of any system failure (Assembly, Pspice)
`
`5/93-9/93, 5/94-9/94, 3/95-12/95
`
`
`
`
`
`2
`
`
`
`
`
`
`
`
`
`
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
`TECHNICAL SKILLS
`
` I have about 9 years of industrial experience and more than 15 years of academic experience in the following
`areas:
`o Software analysis (C/C++, Perl, Python, Verilog, SystemVerilog, SystemC)
`o System level design, embedded system design, and design of digital components of computers and
`servers
`o Algorithm design and optimization for dynamic and leakage power in SoC (System-on-Chip) and NoC
`(Network-on-chip), and computer systems
`o Signal integrity analysis of power delivery networks for servers, and SoCs, e.g., placement of server
`chassis components to minimize noise and power consumption
`o High performance, Lower power memory design including DDR2, DDR3 DRAMs, and various SRAM
`architectures
`o Thermal analysis and cooling system modeling of digital systems
`o Design of computing systems using CMOS alternatives, such as FinFET technologies
`o Teaching logic, VLSI, computer architecture, computer networks, and embedded system design and
`verification courses (such as EE101, 209, 109, 499/454, , 450, 357, 352, 477, 577A/B, 599 of USC)
`that directly focus on hardware and software components of servers
`
`
`
`RESEARCH GRANT PROPOSALS DRAFTED
`
`
`
` Algorithms and Design Methodologies for Extreme Low-Power Zetta-Scale Networks-on-Chip Architectures.
`Collaboration with Professor Paul Bogdan. Submitted to NSF in Jan. 2015
` Static Timing Analysis and Signoff Techniques for Deeply-Scaled circuits. Collaboration with Professor
`Pedram. Submitted NSF in 2012. Result: rejected
` Static Timing Analysis and Circuit Optimization: A signal Waveform-based Approach. Collaboration with
`Professor Pedram. Submitted to IBM in August 2011. Result: rejected
` “Development of multi-technology modules for learning logic design in EE 101” S. Nazarian, B. Zafar, M.
`Redekopp, S.K. Gupta, FUND FOR INNOVATIVE UNDERGRADUATE TEACHING (FIUT), accepted in April
`2011
` Collaborated with my colleague (also my former Ph.D. advisor) Professor Massoud Pedram in writing a
`proposal entitled “Statistical Static Timing and Power Analysis and Circuit Optimization: A Current Source
`Model-Based Approach “ funded by Semiconductor Research Corporation (SRC) for $100K/year 2006-2009
` Collaborated with Professor Nourani (my advisor on first Master’s degree) in writing a research proposal for
`TxTEC (Texas Telecommunications Engineering Consortium) Scholarship on “Energy efficient VLSI
`architectures for communications and signal processing,” accepted for $12000 in 2000
`
`HONORS AND AWARDS
`
` Best Paper Nomination, ASPDAC Conference, 2016
` Recipient of the first inaugural Dean’s Award for Teaching Excellence, Viterbi School of Engineering, April
`2014
` Travel grant to attend BUPT to give a talk on my teaching style to faculty and students, May 31-June 6, 2014
` Travel grant awarded by Viterbi School to attend NETI-2 conference (Advanced National Effective Teaching
`Institute), Montreal, Canada, July 14-15, 2014
` USC Center For Excellence In Teaching Innovative undergraduate teaching award, 2011
` Research Corporation (SRC) research grant ($100k per year 2006 to 2009) on proposal (written jointly with
`Professor Massoud Pedram) entitled “Statistical Static Timing & Power Analysis & Circuit Optimization,” 2006
` Best Paper Award nomination, International Symposium on VLSI Design, Automation and Test Conference
`(VLSI-DAT), April 2006
` Recipient of Ph.D graduate award from Association of Professors and Scholars of Iranian Heritage (APSIH),
`2006.
`
`
`
`3
`
`EXHIBIT 2002
`IPR2015-01094
`
`

`
` International academic achievement award, USC, 2006
`
` Mentorship award of Young Student Support Program (YSSP), Design Automation Conf., San Diego, 2004
` Outstanding leadership award, USC, 2004
` TxTEC (Texas Telecommunications Engineering Consortium) scholarship recipient on “Energy efficient VLSI
`architectures for communications and signal processing,” written jointly with Professor Nourani, 2000
` Ranked 10th amongst about 5000 Electrical Engineers in the nationwide M.S. entrance exam, Iran, 1996
` Outstanding intern award for the work in Takta Research Co., Tehran, 1994
` Entrance Fellowship, Amirkabir University of Technology (Tehran Polytechnic), 1990
` Ranked the 27th amongst more than 200000 in the nationwide B.S. entrance exam, Iran, 1990
` Ranked the 3rd amongst more than 200000 in the Math category of the nationwide B.S. entrance exam, Iran
`1990
`
`JOURNAL PUBLICATIONS
`
`
`
`1. T. Cui, Y. Wang, S. Nazarian, and M. Pedram. “A Learning-Based Profit Maximization Algorithm for Utility
`Companies in an Oligopolistic Energy Market with Dynamic Prices and Intelligent Users”, AIMS Energy 22-
`38, 2016.
`2. W. Lee, Y. Wang, T. Cui, S. Nazarian, and M. Pedram "Temperature Effect Inversion Aware Dynamic
`Thermal Management for FinFET Circuits", IEEE T. on CAD (under review)
`3. S. Nazarian, D. Das, “An Efficient Current-Based Logic Cell Model for Crosstalk Delay Analysis,” International
`Journal of Electronics, pp. 439-467, Volume 100, Issue 4, 2013
`4. S. Nazarian, H. Fatemi, M. Pedram, “Sequential and combinational logic cell delay calculation based on a
`current source model,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 92-103,
`Volume 19, Issue 1, Jan 2011
`5. S. Nazarian, M. Pedram, “Analysis of coupled interconnects in VDSM technologies,” International Journal of
`Electronics, pp. 903-937, Volume 95, Issue 9, 2008
`6. M. Pedram, S. Nazarian, “Thermal modeling, analysis, and management in VLSI circuits: Principles and
`Methods,” Proc. of IEEE Special Issue on Thermal Analysis of ULSI, pp. 1487-1501, Aug. 2006
`
`CONFERENCE PUBLICATIONS
`
`7. T. Cui, J. Li, A. Shafaei Bejestan, S. Nazarian, and M. Pedram, “An Efficient Timing Analysis Model for 6T
`FinFET SRAM using Current-Based Method,” To appear in Proc. of Int’l Symp. on Quality Electronic Design,
`Mar. 2016.
`8. J. Li, X. Lin, S. Nazarian, and M. Pedram. “Negotiation-based resource provisioning and task scheduling
`algorithm for cloud systems,” To appear in Proc. of Int’l Symp. on Quality Electronic Design, Mar. 2016.
`9. T. Cui, S. Chen, Y. Wang, Q. Zhu, “Optimal Co-Scheduling of HVAC Control and Battery Management for
`Energy-Efficient Buildings Considering State-of-Heath Degradation,” To appear in ASP-DAC, Jan. 2016,
`(Best Paper Nomination)
`10. L. Wang, A. Shafaei, S. Chen, Y. Wang, S. Nazarian, and M. Pedram. “10nm Gate-Length Junctionless Gate-
`All-Around (JL-GAA) FETs Based 8T SRAM Design Under Process Variation Using a Cross-Layer
`Simulation,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Oct. 2015.
`11. W. Lee, D. Shin, Y. Wang, S. Nazarain, and M. Pedram. “Design and Optimization of a Reconfigurable Power
`Delivery Network for Large-Area, DVS-Enabled OLED Displays,” to appear in Proc. of the Int’l Symp. on Low
`Power Electronics and Design, July 2015.
`12. T. Cui, S. Chen, Y. Wang, S. Nazarian and M. Pedram. “Optimal Control of PEVs for Energy Cost
`Minimization and Frequency Regulation in the Smart Grid Accounting for Battery State-of-Health
`Degradation,” To appear in Proc. of Design Automation Conf., Jun. 2015
`13. T. Cui, Y. Wang, S. Nazarian, and M. Pedram. “Layout Characterization and Power Density Analysis for
`Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells,” To appear in Proc. of ACM Great Lakes
`Symp. on VLSI, May 2015
`14. J. Li, Q. Xie, Y. Wang, S. Nazarian, and M. Pedram. “Leakage power reduction for deeply-scaled FinFET
`circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique,” Proc. of
`Design Automation and Test in Europe, Mar. 2015
`15. C. Guan, Y. Wang, X. Lin, S. Nazarian, and M.