VWGoA - Ex. 1010
`Volkswagen Group of America, Inc. - Petitioner
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`EP 0 631 378 A1
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`Technical Field
`
`This invention relates to digital data receivers
`and. more particularly. to a receiver for detecting
`high-frequency burst-mode packet data superim-
`posed on a lower frequency signal.
`
`Background ot the Invention
`
`One form of optical communications with in-
`creasing commercial
`importance utilizes passive
`sharing of an optical fiber among several optoelec-
`tronic sources and detectors {referred to hereinafter
`as "optical busing").
`One specific example of optical busing is the
`"Passive Optical Network" (PON) illustrated in FIG.
`1. Here, several
`terminal units {Optical Network
`Units - ONU) are linked by one or more passive
`optical couplers (POO) and optical fibers to a ser-
`vice provider Optical Subscriber Unit {OSU} that
`may in turn be the gateway to an external network.
`Data is transmitted within the network by either or
`both oi time division multiplexing and wavelength
`division multiplexing.
`In one currently favored implementation of a
`PON. the OSU is allocated a transmit mode 110 of
`approximately half of each cycle to transmit
`in-
`formation while the ONUs ”listen" in a receive
`
`mode. In the second half of each cycle. the ONUs
`are allocated individual time slots in which to trans-
`mit data 120 while the OSU in turn listens. The
`
`data burst signals transmitted by each ONU during
`one of these time slots [T1 - TN) are referred to as
`a "packet".
`Our US. patents 5,025,456, issued on June 18,
`1991. and 5,371,763, issued on December 6, 1994,
`and our U.S. patent application identified by Serial
`No. 07976039. filed on November 13, 1992,
`re-
`solve several problems faced by electronic receiver
`circuits operating in
`such "burst-mode" packet
`communication systems.
`Our US. patent '456 describes a fundamental
`technique for dynamically establishing a
`logic
`threshold voltage centered between the extremes
`of burst~mode data signals, thus solving one well-
`known problem. The US. patent '783 introduces a
`precision peak detector reset technique for solving
`the problem of handling closely spaced data pack-
`ets of widely varying amplitude. The U.S. patent
`application Serial No. 07:976039 describes a tech-
`nique for canceling out low-frequency signals due
`to background light on the optical bus. thus solving
`another problem.
`In certain packet communication applications. it
`may be advantageous to superimpose on the bus
`the combination of a low-frequency signal channel
`along with the high-frequency packet data. For
`example, this low-frequency signal channel might
`
`be used for distance ranging or for communicating
`audio or terminal status information.
`
`An additional difficulty is that the burst-mode
`packet data may have spectral energy in the same
`frequency band as the low-frequency signal. Yet.
`none of these communication channels is permitted
`to interfere with the proper detection of any other
`channet
`
`Thus. there is a need for a burst-mode packet
`data receiver which can properly detect the low-
`frequency signal channel along with the high-fre-
`quency packet data.
`
`Summary of the Invention
`
`invention. a
`In accordance with the present
`digital burst-mode packet data receiver receives
`high-speed burst-mode packet data signals com-
`bined with a lower frequency data signal. The re-
`ceiver includes a first detector for detecting the
`received high-speed burst-mode packet data which
`is reset during the time period between consecu-
`tive bursts of the high-speed packet data signal. A
`second detector samples the lower frequency data
`signal during a predetermined portion of the time
`period between consecutive bursts of
`the high-
`speed packet data.
`More particularly. the present invention solves
`the prior art receiver problems by providing:
`|. Independent detection of both a high-speed
`packet data signal and a low-frequency data
`signal which are superimposed on an optical
`bus at the same optical wavelength.
`ll. Low-frequency data detection means which is
`insensitive to spectral components of the high-
`speed packet data signal that may extend into
`the frequency band of the low-frequency data.
`111. High-speed packet data signal detection
`means which is insensitive to the low-frequency
`data signal and to any other background light on
`the optical bus.
`IV. Low-frequency detection means which does
`not
`interfere with the high-speed packet data
`path--by.
`tor example,
`imposing special con-
`ditions on packet length. packet spacing. or bit
`protocol within the packet.
`
`Brief Description of the Drawing
`
`FIG. 1 illustrates an example of optical busing in
`a Passive Optical Network [PONl
`in which the
`present invention may be utilized:
`FIG. 2 shows a block diagram of a packet re-
`ceiver in accordance with the present invention;
`FIG. 3 shows an illustrative received burst-mode
`
`packet data signal superimposed on a low-fre-
`quency signal and the signals detected there-
`from by our receiver;
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`FIG. 4 shows a table describing the data and
`reset modes of the present invention; and
`FIG. 5 depicts another receiver embodiment for
`performing packet data and low-frequency data
`detection.
`
`Detailed Description
`
`there is shown a
`with reference to FIG. 1.
`Passive Optical Network (PON) in which a receiver.
`in accordance with the present invention. may be
`utilized.
`In FIG. 1. each burst-mode data packet in
`time slots T1 - TN would originate, respectively.
`from one of 0NU«1 through ONU-N. The burst«
`mode data packet
`in time slots T1 and T2 are.
`illustratively, shown in FIG. 3 as each having the
`same number of data bits and different amplitudes
`P1 and P2, respectively. These burst-mode data
`packets are shown superimposed on a tow-fre-
`quency signal 305 which also has to be detected
`by the packet receiver of the present invention.
`A packet receiver of the present invention must
`solve several problems to be effective in the PON
`shown in FIG. 1. First, the receiver must dynam-
`ically establish an effective logic threshold voltage
`centered between the extremes of the data signal
`swing. Ideally. this data threshold will be substan-
`tially established during the first bit of an input data
`burst. Second, because the bus is time-shared by
`many different ONU transmitters which may have
`widely varying power levels. the receiver electron-
`ics must be able to handle a wide range of packet
`amplitudes. separated by only a few bit periods in
`time. Third. because of various causes, there may
`be background optical signals on the bus at much
`lawer frequencies than the data signal. These low-
`frequency signals can prevent proper detection of
`the high-speed data under certain conditions. The
`receiver must be able to prevent
`these low-tre-
`quency signals from interfering with proper detec-
`tion of the data signal.
`With reference to FIG. 2. we describe the op-
`eration of the present invention as illustratively im-
`plemented in a packet receiver of OSU of FIG. 1.
`The packet receiver of the present invention may.
`illustratively, be used for reception and resolution
`of burst-mode data in a packet format having a
`predetermined number of bits per packet. as would
`be used in an Asynchronous Transfer Mode (ATM)
`application. for example.
`The core of our packet receiver circuit of FtG.
`2 includes the burst-mode receiver architecture of
`
`our US. patent 5.025.456, consisting of differential
`IIO Transimpedance Amplifier A1
`. Peak Detector
`PD. and Output Amplifier As.
`input signals
`With reference to FIG. 2. optical
`representing the data bits of the burst-mode packet
`data
`signal
`are
`received
`and converted
`by
`
`f1”. Tran-
`Photodiode PD1 into Photocurrent Signal
`simpedance Amplifier A1 converts the currents into
`a differential output voltage.
`The differential Output voltage of Amplifier A1
`is Vat Vo' =I1NZT, where 21- is the transimpedance
`(feedback resistor) between the positive input and
`negative output of A1
`. One of A1
`'3 differential
`outputs. and therefore one-half of the net output
`swing. is sampled by the Peak Detector and stored
`on Capacitor CPD . This half-amplitude reference
`level.
`
`f Zav 1%
`
`. establishes the "instantaneous logic threshold"
`V1151: and is appiied to the complementary {nega-
`tive} input of A1 during normal "data mode" opera-
`tion. The instantaneous logic threshold V351: is de-
`termined at the beginning of each signal burst. The
`logic threshold V35;
`is set equal to the half-am-
`plitude point of the peak input signal. and subse-
`quent signal amplification by Al
`is referenced to
`this
`level. Threshold V1151: determination is very
`rapid, and ideally is compieted by the conclusion
`of the first bit in the signal burst.
`Variations of signal amplitude from packet to
`packet are accommodated using an externally pro-
`vided RESET input signal to identify the interval
`between packets. as in our previously referenced
`patent 5.371.763. Resetting after
`receiving each
`packet data burst ensures that the packet receiver
`can detect a smaller amplitude P2 data packet
`(e.g..
`in T2) which immediately follows a larger
`amplitude P1 data packet {e.g.. in T1}. This RESET
`input signal is an interpacket signal produced by an
`external circuit that keeps track of timing during a
`received packet and is able to predetermine the
`end of the packet. The RESET input signal causes
`a Threshold Reset circuit to generate a Reset En-
`able signal which causes Reset Discharge circuit to
`discharge Capacitor CPD using discharge current
`tors »
`The Reset Discharge circuit discharges the
`stored peak amplitude signal on Capacitor CPD to a
`non~zero DC voltage , ng . that is substantially
`equal
`to the baseline DC voltage stored by the
`Peak Detector circuit during the absence of a re-
`ceived input signal. This DC voltage Vase) is estab-
`lished using a Precision Reference circuit. The
`Reset Discharge circuit may inciude both coarse
`and fine Reset circuits {not shown) which are en-
`abled by the RESET signal. A coarse Reset circuit
`discharges the Detector circuit at a high rate until
`the stored voltage is within a predetermined volt-
`age of the baseline DC voltage. after which it
`is
`shutoff. A fine Reset circuit discharges the Detec-
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`EP 0 631 378 A1
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`for circuit at a low discharge rate until the baseline
`DC voltage is reached.
`The Precision Reference circuit establishes a
`
`reference voltage View which is equivalent to a
`baseline voltage V35; generated when no input
`current (m is received from Photodetector PD1. The
`Precision Reference circuit
`is
`implemented as a
`"clone" of A: and Peak Detector. except that no
`Photodetector P01 is used.
`
`The novel capabilities of our packet receiver.
`shown in FIG. 2. stem from its incorporation of very
`high—speed Sampling and Hold circuit SH1 and
`Selector (analog multiplexer) circuitry S1.
`The Sample and Hold circuit SH1 may be
`implemented in a well-known manner. For example.
`see the article entitled "Fully Bipolar. 120-M Sam-
`plei's
`tO-b Track and Hold Circuit," written by
`Messrs. Vorenkamp and Verdaasdank and pub-
`
`lished in IEEE Journal of Solid-State Circuits, Vol.
`27. No. 7, July 1992.
`By means of
`the Sampting and Hold circuit
`SH1. enabled by a sample control input signal (320
`of FIG. 3] having timing information derived from
`the RESET signal. our packet
`receiver has the
`capability of detecting the amplitude of a low-
`frequency light signal (305 of FIG. 3} component of
`the receiver
`input
`(300 of FIG. 3} in the brief
`interval T0 between packets. This amplitude in-
`formation is provided at a special
`low-frequency
`data or "sampled" output
`(340 of FIG. 3). Our
`packet receiver thus provisionally satisfies the pur-
`pose of requirement I above. by producing both a
`high-speed packet data output (330 of FIG. 3) and
`a low-frequency sampled data output (340 of FIG.
`3).
`
`By sampling the received input signal (300 of
`FIG. 3] during the "quiet“ interval (i.e.. 320 occurs
`during TQ interludes) between packets. we can
`assure that
`there is no high-speed data signal
`present. This provisionally resolves requirement I|
`above.
`
`After the low-frequency signal has been sam-
`pled in the quiet interval TQ between packets. this
`value is held by Sample and Hold circuit SH1 and
`converted to
`an
`equivalent differential
`current
`“coup of FIG. 2) which is subtracted from the
`received input signal during the subsequent high-
`speed data packet intervals (e.g., T1. T2 of FIG. 3].
`Recall that amplifier A: has a transimpedance of 2-,-
`(i.e., 5V0 =l.-*ZT ). The background light compensa-
`tion circuit has an equivalent transconductance that
`is approximately
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`the inverse characteristic of A1
`Le.
`level compensator" linearly converts the voltage
`stored in SH1 to a differential output current. (COMP
`. according to this inverse characteristic.
`It thus
`effectively cancels the low-frequency signal (305 of
`FIG. 3) at all times (T1 - TN} as well as any other
`background light that may be present. except for
`the quiet interval TQ between packets, so that it
`does not interfere with burst-mode detection of the
`
`high-speed packet data during times T1 - TN. This
`resolves requirement lll above.
`Data packet protocols ensure that there must
`be a "quiet" interval TQ between data packets.
`That is because (1) there must be a timing cushion
`to prevent adjacent packets (e.g., T1. T2)
`from
`interfering with one another, and (2) a RESET time
`is required to discharge the burst-mode Peak De-
`tector. in preparation for receipt of the next packet.
`Consequently. sampling during the quiet
`interval
`TO {using the sample signal] does not violate re-
`quirement IV above by interfering with the packet
`data protocols. However. during the RESET input
`signal. the output Amplifier As should be disabled
`(by Reset Disable signal] while the Peak Detector
`is being discharged. That is necessary because it
`would otherwise have undetermined outputs during
`the reset operation.
`To ensure stable voltage levels within the cir-
`cuit, we normally must wait until
`the end of the
`Peak Detector RESET operation before we can
`begin the interpacket sampling operation described
`above. That requires that RESET signal and Sam—
`pling signal operations be performed sequentially.
`which will necessarily increase the required time to
`complete these operations.
`In accordance with the invention, an analog
`multiplexer (i.e. Selector 81 of FIG. 2} is used to
`isolate the Peak Detector from the input Amplifier
`.41 during the RESETiSampie operations, so that
`resetting of the Peak Detector can proceed simulta-
`neously with low-frequency sampling. This allows a
`considerable reduction in the required total time.
`The following paragraphs review the operation
`of our packet receiver circuit of FIG. 2 during the
`DATA and RESET modes.
`
`DATA Mode
`
`With reference to the table shown in FIG. 4.
`during the DATA mode. the RESET signal
`is in a
`negative state. Hence. the Dark Level Compensator
`and Output Amplifier A3 are enabled, the Selector
`St
`selects the Peak Detector output Veg;
`,
`the
`Discharge circuit is disabled. the Sample and Hold
`circuit SH1 is in the hold mode and the sample
`output is constant.
`At the beginning of a data burst. one-half of the
`peak value of Amplifier A:
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`output is stored on Peak Detector Capacitor CPD .
`and is routed through the high-speed Selector St
`(an analog, unity gain multiplexer) back to the
`negative input of Amplifier A1 . This half-amplitude
`signal becomes an effective logic threshold at Am-
`plifier A1 's input, and subsequent data signals are
`defined as either logic ONE or ZERO. depending
`on whether they are above or below this threshold.
`The differential signal from Amplifier A1
`is then
`further amplified by output Amplifier As and ap-
`pears across outputs O and {—3.
`
`RESET Mode
`
`With joint reference to FIGS. 2 and 4. at the
`conclusion of a data packet during the quiet inter-
`val TQ. a RESET signal is delivered to the packet
`receiver. The RESET signal causes several actions
`to occur: {a} the receiver‘s high-speed packet data
`output Amplifier A3 is disabled.
`i.e.. clamped to a
`low (logic ZERO} state (this ensures that that out-
`put does not suffer spurious logic transitions during
`RESET);
`(b)
`the
`high-speed Selector
`S1
`is
`switched so that it provides a fixed DC reference
`Vase;
`to the negative input of A1
`:
`(c) the Peak
`Detector Capacitor CPD discharge control circuitry
`is activated; and (d) the Dark Level Compensator
`circuit is disabled or turned off.
`In the RESET mode.
`the Peak Detector Ca-
`
`pacitor CPD is discharged to prepare the circuit for
`the next packet. At about the same time. a pulse
`may be delivered to the Sample and Hold circuit
`SH1. This activates the Sample and Hold circuit
`SH1. which measures and stores the differential
`output of Amplifier A1 at this time. Amplifier A1 's
`output voltage during the interval between packets
`will be related to low-frequency information as well
`as background light. This signal is delivered to the
`Sample BufferlAmp A1 to provide an external volt-
`age (sampled outputs S and S ) proportional to the
`light present between packets.
`the
`At
`the conclusion of the RESET signal.
`Dark Level Compensator is again enabled and con-
`verts the Sample and Hold signal (from 3H1) into a
`compensatory differential input current icoup . This
`compensatory differential current (coup exactly can-
`cels the photocurrent due to the low-frequency
`signal and also that due to background light.
`Note that although the implementation we have
`described utilizes a current input.
`it does not pre-
`clude the use of a voltage input (e.g.. Vs of 190 in
`FIG. 2} using well-known techniques in the art for
`converting current input Transimpedance Amplifier
`A1 into a voltage amplifier. One example of how
`this could be implemented is shown in FIG. 2 using
`a voltage input source V3 and input impedance Zm
`connected to the positive input of Amplifier A1 and
`a reference voltage V359 connected through an
`
`input impedance 2m to the negative input of Am-
`plifier A1 (see 191).
`Also note that although the detailed implemen-
`tation we have described. in Fla. 2, uses an analog
`Selector 81 in the peak detector feedback loop to
`reduce the required packet spacing. as described
`above. it would be a straight forward proposition to
`utilize instead separate amplifier chains (for
`the
`Sampled output and Packet Data output} along with
`a voltage input burst-mode amplifier to accomplish
`substantially the same purpose. as illustrated in
`FIG. 5.
`
`There. the Packet Data output is generated via
`transimpedance Amplifier Ac . voltage Amplifier Am
`. and output Amplifier A3 . The Sampled output is
`generated by transimpedance Amplifier A0 . Sam-
`ple and Hold circuit SHIA and Buffer Amplifier A“
`. After the low-frequency signal has been sampled
`in the quiet interval TO between packets, this value
`is held by Sample and Hold circuit SH1A and
`converted to an equivalent differential
`current
`(locum of FIG. 5) by the "dark level compensator"
`which is subtracted from the received input signal
`during the subsequent high-speed data packet in-
`tervals (e.g.. T1. T2 of FIG. 3).
`It thus effectively
`cancels the low-frequency signal (305 of FIG. 3} at
`all times (T1 -TN} as well as any other background
`light
`that may be present, except for the quiet
`interval TO between packets. so that it does not
`interfere with burst-mode detection of
`the high-
`speed packet data during times T1 — TN. By sub-
`tracting compensation current loom from the input
`to Amplifier A” . we can eliminate dark currents
`from the receiver. Optionally. compensation current
`looms (shown by dotted lines} can be used to
`eliminate dark currents at the input to Amplifier A0 .
`The implementation and operation of the compara-
`ble circuits of FIG. 5 are essentially the same as
`the similar circuits described for FIG. 2.
`
`In the disclosed embodiment. the analog circuit
`blocks are actually either well-known ECL gates. or
`simple modifications of ECL gates. The ECL gate
`consists of a differential pair with current source
`load. followed by an emitter follower stage. These
`circuits. while offering limited gain. are inherently
`very fast. The input Amplifier A1 , output Amplifier
`A3 . Peak Detectors. Buffer Amplifier. and Precision
`Reference may be implemented using circuits
`which are described in more detail
`in our article
`
`entitled "DC-IGbls Burst-Mode Compatible Receiv-
`er for Optical Bus Applications." by Yusuke Ota, et
`
`al.. Journal of Lightwave Technology. Vol. 10, No.
`2. February 1992.
`While the disclosed embodiment of the present
`invention is implemented used bipolar integrated
`embodiment circuit technology. it should be noted
`that other circuit
`technologies could be utilized.
`including FET.
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`The circuit can be implemented using, for ex-
`ample, silicon. gallium arsenide or other appro-
`priate semiconductor materials. Moreover, it is con-
`templated that other welt-known circuits can be
`used to implement
`the amplifier circuit functions
`shown in FIGS. 2 and 5 without departing from the
`teaching of the present invention.
`Although the present
`invention has been de-
`scribed ior use with optical signals.
`it should be
`understood that the present invention can be uti-
`lized in non-optical signals as well.
`
`Claims
`
`1.
`
`A digital burst-mode packet data receiver (FIG.
`2)
`for simultaneously receiving a high-speed
`burst-mode packet data signal and a lower
`frequency data signal. CHARACTERIZED IN
`THAT
`
`first means {PD} for detecting the high-
`speed burst-mode packet data.
`first
`the
`means
`for
`resetting (RESET)
`means for detecting during a time period be-
`tween consecutive bursts of
`the high-speed
`packet data signal. and
`second means {SI-ll} for detecting the low-
`er frequency data signal during a predeter-
`mined portion of the time period between con-
`secutive bursts of the high-speed packet data
`without
`interference
`from said high-speed
`burst-mode packet data signal.
`
`2. The receiver of claim 1 CHARACTERIZED IN
`THAT
`
`said first means for detecting is reset in
`response to a received reset signal ocwrring
`during the time period between consecutive
`bursts of
`the high-speed packet data signal
`and
`
`said second means for detecting is en-
`abled during said predetermined portion, de-
`fined by a received sample signal occurring in
`the absence of said received reset signal.
`
`3. The receiver of claim 1 CHARACTERIZED IN
`
`THAT said first means for detecting includes
`a DC-coupled differential
`input amplifier
`circuit having first
`input means for receiving
`said packet data bursts. second input means
`for
`receiving a reference signal. and output
`means for outputting a data output signal and
`detector means for detecting and storing a
`peak amplitude of said data output signal and
`for generating said reference signal at an out-
`put port.
`
`4. The receiver of claim 3 CHAFIACTEFlIZED IN
`THAT
`
`said second means for detecting utilizes a
`signal path that
`is independent of said DC-
`coupled differential input amplifier circuit.
`
`The receiver of claim 3 CHARACTERIZED IN
`
`THAT said resetting means includes
`selector means. responsive to a reset sig-
`nal, occurring during the time period between
`consecutive bursts of the high-speed packet
`data. for
`a) disconnecting said peak amplitude detec-
`tor means output port
`from said second
`input means of said input amplifier circuit
`and discharging said peak amplitude signal
`stored by said peak amplitude detector
`means, and
`b) connecting a precision reference voltage
`as said reference signal
`to said second in-
`put means of said input amplifier circuit.
`
`The receiver of claim 1 CHARACTERIZED IN
`
`THAT said second means for detecting in-
`cludes
`
`detector means for generating said lower
`frequency data signal by sampling said data
`output signal
`in response to both an inter-
`packet reset signal and a sample control input
`signal.
`
`7.
`
`The receiver of claim 6 CHARACTERlZED IN
`THAT
`said detector means includes means for
`
`subtracting said lower frequency data signal
`from the high-speed burst-mode packet data
`signal when said reset and sample control sig-
`nals are absent.
`
`The receiver of claim 1 CHARACTERIZED IN
`THAT
`
`said first means for detecting detects elec-
`trical current changes in the received high-
`speed packet data signal and
`said second means for detecting detects
`electrical current changes in the received lower
`frequency data signal.
`
`The receiver of claim 1 CHARACTERIZED IN
`THAT
`
`said first means for detecting detects elec-
`trical voltage changes in the received high-
`speed packet data signal and
`said second means for detecting detects
`electrical voltage changes in the received low-
`er frequency data signal.
`
`10.
`
`receiving
`A digital packet data receiver for
`bursts of digital packet data. CHARACTER-
`IZED BY
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`input amplifier
`a DC-coupled differential
`circuit having first
`input means for receiving
`said digital packet bursts, second input means
`for
`receiving a reference signal, and output
`means for outputting a data output signal;
`first detector means for detecting and stor-
`ing a peak amplitude of said data output signal
`and for generating said reference signal at an
`output port;
`second detector means for generating a
`sample data output signal of said data output
`signal in response to both an inter-packet reset
`signal and a sample control input signal; and
`selector means. responsive to said reset
`signal, for
`a) disconnecting said first detector means
`output port from said second input means
`of said input amplifier circuit and discharg-
`ing said peak amplitude signal stored by
`said first detector means. and
`b) connecting a precision reference voltage
`as said reference signal to said second in-
`put means of said input amplifier circuit.
`
`11.
`
`The receiver of claim 10 CHAHACTERIZED IN
`THAT
`
`said first detector means is discharged to
`a non-zero DC voltage substantially equal to an
`initial DC voltage which is stored by said first
`detector means during an absence of a re-
`ceived signal to said receiver.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
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`EP 0 681 378 A1
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`EP 0 681 378 A1
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`EP 0 681 378 A1
`
`FIC.4
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`- DATA MODE
`
`DARK LEVEL
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`
`OUTPUT AMR A3
`
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`
`DISABLED
`
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`
`13
`
`11
`
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`EP 0 681 378 A1
`
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`.0)
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`3:2” PM“
`
`EUROPEAN SEARCH REPORT
`
`"W“”W
`
`DOCUMENTS CONSIDERED TO BE RELEVANT
`m— m
`dnhnd -w.—
`«an.
`
`US - A ~ 5 3?1 763
`(UTA)
`* Fig. 6: abstract *
`
`EP — A — 0 597 633
`(AMERICAN TELEPHONE AND
`TELEGRAPH}
`* Fig. 6; abstract *
`
`US — A — 5 025 456
`IOTA)
`* Fig. 11: abstract *
`
`EP — A — 0 593 947
`(ALCATEL SEL}
`* Fig. 1; abstract *
`
`DE - A - 4 036 411
`(STANDARD ELEKTRIK LORENZ)
`* Fig. 2; column 2.
`
`JOURNAL OF LIGHTWARE
`TECHNOLOGY. vol. 10. no. 2.
`February 1992
`ROBERT G. SWARTZ et al.
`"DC-le/S Burst-Mode
`Compatible Receiver for
`Optical Bus Applications"
`pages 244—249
`* Fig.
`1
`*
`
`
`
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