EXHIBIT C
`
`Micron Technology, Inc. at al., Petitioners - Ex. 1047
`Micron Technology, inc. and Micron Memory Japan. Inc. v. Massachusetts Institute of Technology
`|PR2015-01037
`1
`
`
`
`Micron Technology, Inc. at al., Petitioners - Ex. 1047
`Micron Technology, inc. and Micron Memory Japan. Inc. v. Massachusetts Institute of Technology
`|PR2015-01037
`1
`
`
`
`I
`
`Construction Analysis
`
`I
`
`Sémsung KM44C4000]-7
`16 Megabit DRAM
`
`Report Number: - SCA 93116001
`
`
`
`INTEGRATED BIRGUIT ENGINEERING
`
`
`
`
`
`
`17350 N. Hartlord Drive
`Scottsdale. AZ 85255
`Phone: 602-515-9780
`Fax: 602-51 5-9781
`e-mail: ioe@ice-corp.com
`Intemetz http://wwwnice-corp.com
`
`
`
`INDEX TO TEXT
`
`TITLE
`
`PAGE
`
`INTRODUCTION
`
`MAJOR FINDINGS
`
`TECHNOLOGY DESCRIPTION
`
`Assembly
`
`Die Process and Design
`
`ANALYSIS RESULTS I
`
`Assembly
`
`ANALYSIS RESULTS II
`
`Die Process and Design
`
`ANALYSIS PROCEDURE
`
`TABLES
`
`Overall Evaluation
`
`Package Markings
`
`Wirebond Strength
`
`Die Material Analysis (EDX and WDX)
`
`Horizontal Dimensions
`
`Vertical Dimensions
`
`1
`
`1
`
`2
`
`2 - 3
`
`4
`
`5 - 7
`
`8
`
`I--uu—II—-RD59¢}
`
`1 1
`
`12
`
`
`
`INTRODUCTION
`
`This report describes a construction analysis of the Samsung KM44C4000J—7 16-megabit
`
`CMOS Dynamic RAM. Four samples molded in 24-pin plastic SOJ packages and date
`
`coded 9313 were supplied for the analysis. Analysis of the packaging and assembly is
`
`included.
`
`MAJOR FINDINGS
`
`Questionable ltems:1
`
`- Silicon nodules occupied up to 75 percent2 of metal 2 line widths (Figure 16).
`
`Special Features:
`
`- Twin—well process with sub—micron geometries (0.3 micron poly 1 and 0.5 micron
`
`metal 1).
`
`- Two levels of metal, four levels of poly.
`
`* Metal 1 contacts were completely filled with aluminum (aluminum reflow).
`
`1Tt"te.s'e items presentpossibie quality or reliability concerns. Ntey should be discussed
`with the manufacturer to determine theirpossible impact on the intended application.
`
`2The seriousness depends on design margins.
`
`
`
`TECHNOLOGY DESCRIPTION
`
`Assembly:
`
`- 24-pin (28 pin format) plastic small-outline I-lead package (SOJ).
`
`-
`
`Iron-nickel (FeNi) leadframe.
`
`- External leads were coated with tin—lead (SnPb) solder.
`
`-
`
`Internal 1eadfi'ame plating consisted of spot-plated silver (Ag) over a thin copper
`
`(Cu) flash. No plating was present on top of the header.
`
`- Lead-locking provisions (anchors) were present at all pins.
`
`° A dimpled header was employed.
`
`° All pins were connected.
`
`- Die attach was by silver (Ag)-epoxy.
`
`* Dicing was by the sawn method.
`
`- Wirebonding was by the thermosonic ball bond method using 1.3 mil 0.D. gold wire.
`
`Die Process and Design:
`
`- Fabrication process: Selective oxidation CMOS process with twin wells in a P(?)
`substrate.
`
`- Die coat: A patterned (to clear bond pads) polyimide die coat was present to protect
`
`against alpha particle-induced leakage.
`
`- Overlay passivation: A layer of silicon-nitride over two layers of silicon-dioxide.
`
`The second layer of silicon-dioxide was multilayered.
`
`
`
`TECHNOLOGY DEHSCRIPTION (continued)
`
`- Metallization: Two levels of metal conductors were used Metal 2 consisted of
`
`aluminum only. Metal 1 consisted of aluminum with a titanium-nitride cap and
`
`barrier. Both metal levels were defined using a dry—etch technique.
`
`-
`
`Interlevel dielectric: Three layers of silicon-dioxide plus a filler glass (SOG) between
`
`interlevel glasses 2 and 3.
`
`-
`
`intermediate glass: Two layers of boron- and phosphorus-doped glass in addition to
`
`the various densified oxides. Intermediate glass layers (between poly 3 and
`
`polycide, and polycide and metal 1) had been reflowed prior to deposition of
`
`subsequent layers and contact cut definition.
`
`- Polysilicon: Four levels of dry-etched polysilicon were used. Poly 4 employed a
`
`tungsten silicide (polycide) and was used for the bit lines in the cell array and
`
`interconnect in the decode areas. Poly 3 (sheet) was used for the common passive
`
`capacitor plate and poly 2 was used for the individual active capacitor plates in the
`
`cell array. Poly 1 was used for all the gates on the die.
`
`° Diffusions: Standard N+ and P+ implanted sourcefdrain diffusions formed N- and
`
`P-channel transistors. Transistors were formed using an LDD process with oxide
`
`sidewall spacers.
`
`- Wells: Twin wells in an I’ substrate.
`
`* Memory cells: The memory cell used an NMOS DRAM cell design consisting of a
`
`select gate and a stacked capacitor. Polycide formed the bit lines. Poly 1 formed the
`
`word lines and was “piggybacked" by metal 1. Stacked capacitors were formed by
`
`poly 2 pads covered by a poly 3 sheet separated by a thin oxide/nitride dielectric.
`
`- Fuses: Redundancy was implemented using polycide fuses. Laser blown fuses
`
`were noted on all samples. Oxide cuts were present above fuse locations and were
`
`then covered by the overlay passivation- No separate guardbands were found
`
`around the fuses.
`
`
`
`ANALYSIS RESULTS I
`
`Assembly
`
`Figures 1 - 7
`
`Questionable Itemsl: None.
`
`General Items:
`
`- Devices were packaged in 24-pin (28 pin fomiat) plastic SOJS.
`
`- Overall package quality: Normal. No serious defects were found on the external or
`
`internal portions of the packages- Some small voids were noted in the plastic
`
`packaging material; however, overall package integrity was normal. Small gaps
`
`were present at the lead exits. Although they did not penetrate far into the package
`
`the internal plating was relatively close to the edge of the package. This could be
`
`monitored to ensure silver does not become exposed (and subject to dendrite
`
`growth).
`
`- Wirebonding: Thermosonic ball bond method using 1.3 mil O.D. gold wire. No
`
`bond lifts occurred and bond pull strengths were good (see page 10). Normal
`
`intermetallic was present at ball bonds. Wire spacing and bond placement was good.
`
`- Die attach: A silver—epoxy compound was used. Die attach quality was good with
`
`no voids observed.
`
`- Die dicing: Die separation was by sawing (90+ percent) with normal quality
`
`workmanship.
`
`Iflzese items present possible quality or reliability concerns. They should be discussed
`with the manufacturer to determine theirpossibie impact on the intended application.
`
`
`
`ANALYSIS RESULTS I;
`
`Die Process and DesigI_I
`
`Figures 8 - 39
`
`Questionable Itemszl
`
`- Silicon nodules occupied up to 75 percent of metal 2 line widths (Figure 16).
`
`Special Features:
`
`- Twin-well process with sub—micron geometries (0.3 micron poly 1 and 0.5 micron
`
`metal 1).
`
`° Two levels of metal, four levels of poly.
`
`- Metal 1 contacts were completely filled with a.lurninurn(aluminum reflow).
`
`General Items:
`
`- Fabrication process: Selective oxidation CMOS process employing twin-wells in an
`
`N substrate.
`
`- Design and layout: Die layout was clean and efficient. Alignment was good at all
`
`levels.
`
`v Die coat: A patterned (to clear bond pads) polyimide die coat was present to protect
`
`against alpha particle-induced leakage. Coverage was good.
`
`° Die surface defects: No damage, process defects, or contamination was found.
`
`* Overlay passivation: A layer of silicon-nitride over two layers of silicon—dioxide.
`
`Overlay integrity test indicated defect-free passivation. Edge seal was good.
`
`IThese items present possible quality or reliability concerns. They should be discussed
`with the manufacturer to detennine theirpossible impact on the intended application.
`
`
`
`ANALYSIS RESULTS II (continued)
`
`° Metallization: Metal 2 consisted of silicon-doped aluminum only. Metal 1 consisted
`
`of undoped aluminum with a titanium-nitride cap and barrier.
`
`- Metal patterning: Both metal layers were defined by dry-etch techniques. Definition
`
`was Very good and no significant overetch was present.
`
`0 Metal defects: Some notches were noted in the metal 2 (Figure 15). N0 notches
`
`occupied more than 30 percent of the line width and the entire metal thickness. The
`
`condition present is not of real concern but should possibly be monitored. Silicon
`
`nodules noted following removal of metal 2 occupied up to 75 percent of the
`
`line width. Silicon nodules of 50 percent or greater will lead to current
`
`crowding, which may lead to electromigration and is thus of concern. N0
`
`silicon nodules were noted on the barrier following the removal of aluminum 1.
`
`- Metal step coverage: Metal 2 thinning up to 65 percent was noted at vias. MIL-
`
`STD-883D allows up to '.+'0 percent thinning for contacts of this size- The metal 1
`
`cap was not present in vias (metal 2-to-metal 1), thus was removed during via cuts.
`
`All metal 1 contacts were completely filled with aluminum providing a very good
`
`current path. Integrity of the metal 1 barrier was good.
`
`* Contacts: Contact cuts were probably defined by a two-step process (dry etch
`
`followed by wet etch). No over-etching of the contacts was present.
`
`-
`
`Interlevel dielectric: The dielectric between metal 1 and metal 2 consisted of three
`
`layers of silicon-dioxide.
`
`lnterlevel oxides 2 and 3 were separated by a filler (SOG)
`
`glass. No problems were found.
`
`-
`
`Intermediate glass: Two layers of boron- and phosphorus-doped glass in addition to
`
`the various densified oxides. Glass layer 2 (between polycide and metal 1) and 1
`
`(between poly 3 and polyeide) had been reflowed prior to deposition of subsequent
`
`layers and contact cuts.
`
`
`
`ANALYSIS RESULTS II (continued)
`
`- Polysilicon: Four levels ofpolysilicon were used. Poly 4 employed a tungsten silicide
`
`(polycide) and was used to form the bit lines in the array and as interconnect in the decode
`
`areas. Poly 3 (sheet) was used to form the common passive plate of the capacitors and poly
`
`2 was used to form the individual active capacitor plates. Poly 1 formed all gates on the die.
`
`Definition of all poly layers was by a dry-etch technique of good quality. No stringers or
`
`spurs were noted
`
`*
`
`Isolation: Local oxide (LOCOS). No problems were present at the birdsbeak or elsewhere.
`
`- Diffusions: Standard implanted N+ and P+ diffusions were used for sources and drains.
`
`No problems were found. Oxide sidewall spacers were used to reduce internal capacitance
`
`and hot-carrier effects (LDD process).
`
`- Wells: Twin-wells were employed. Definition was normal.
`
`- Epi: No epi layer was employed. No defects were found in the substrate silicon.
`
`° Fuses: Redundancy was implemented by laser blowing polycide fiises. Blown fuses were
`
`present on all samples. Oxide cuts were present above fuse locations and were covered by
`
`the passivation.
`
`- Memory cells: A stacked capacitor DRAM cell design was employed. Cell pitch was 1.4 x
`
`2.8 microns (3-9 micronsz). Polycide formed the bit lines, poly 3 and poly 2 formed the
`
`capacitor plates, and poly 1 formed the word lines and was "piggybacked" by metal 1. Poly
`
`3 underlaps the poly 2 capacitor plates for increased area (Figure 38).
`
`Special Features:
`
`- Samples 1 and 2 were subjected to ESD sensitivity tests. Results revealed that all
`
`pin combinations passed i4000V.
`
`- Samples 3 and 4 were subjected to latch-up sensitivity tests. Pins were tested from -
`
`200ma to 200ma. Tests revealed no pins latched-up on either sample.
`
`10
`
`
`
`PROCEDURE
`
`The devices were subjected to the following analysis procedures.
`
`External inspection
`
`ESD sensitivity
`
`Latch-up sensitivity
`
`X-ray
`
`Package section and material (EDX)
`
`Decapsulation
`
`Internal optical inspection
`
`SEM inspection of assembly features and passivation
`
`Passivation integrity test
`
`Wirepull test
`
`Passivation removal
`
`SEM inspection ofmetal 2
`
`Metal 2 removal and inspect for silicon nodules and vias
`
`Delayer to metal 1 and inspect
`
`‘Metal 1 removal and inspect barrier
`
`Delayer to polyisubstmte and inspect poly structures and die surface
`
`Die sectioning (90° for SEM)*
`
`Measure horizontal dimensions
`
`Measure vertical dimensions
`
`Die material analysis (EDX and WDX)
`
`*Deiineation ofcross sections is by silicon etch unless otherwise indicated.
`
`11
`
`
`
`OVERALL QUALITY EVALUATION: Overall Rating: Normal
`
`DETAIL OF EVALUATION
`
`Package integrity
`
`Package markings
`
`Die placement
`
`Die attach quality
`
`Wire spacing
`
`Wirebond placement
`
`Wirebond quality
`
`Dicing quality
`
`Wirebond method
`
`Die attach method
`
`Dicing method
`
`Die Surface integrity:
`
`Tool marks (absence)
`
`Particles (absence)
`
`Contamination (absence)
`
`Process defects (absence)
`
`General workmanship
`
`Passivation integrity
`
`Metal definition
`
`Metal integtity
`
`Contact coverage
`
`Contact registration
`
`N
`
`G
`
`G
`
`G
`
`G
`
`G
`
`G
`
`G
`
`Thermosonic ball bonds using 1.3
`
`mil gold wire-
`
`Silver-epoxy
`
`Sawing (90+ percent)
`
`G
`
`G
`
`G
`
`G
`
`G
`
`G
`
`G
`
`NP1
`
`G
`
`G
`
`1Silicon nodules occupied up to 75 percent ofmetal 2 fine widtks.
`
`G = Good, P = Poor, N = Normal, NP = Norman’/Poor
`
`12
`
`
`
`PACKAGE MARKINGS
`
`TP
`
`(Logo) KOREA
`3 13
`KM44C4000.T-7
`
`BOTTOM
`
`4YL
`C03ZAA
`
`WIREBOND STRENGTH
`
`Wire material: 1.3 mil O.D. gold
`
`Die pad material: aluminum
`
`Material at package lands: silver
`
`# of wires tested:
`
`Bond lifts:
`
`Force to break - high:
`
`- low:
`
`- avg.:
`
`- std. dcv.:
`
`13
`
`0
`
`18.0g
`
`1 1.0g
`
`14.5g
`
`2.4
`
`DIE MATERIAL ANALYSIS IEDX and WDXL
`
`Passivation:
`
`Metal 2:
`
`Silicon-nitride over two layers of silicon-
`dioxide.
`
`Silicon-dopcd aluminum.
`
`Interlevel dielectric:
`
`Three levels of silicon-dioxide with a filler
`
`Metal 1:
`
`Intermediate glass:
`
`glass between layers 2 and 3.
`
`Undoped aluminum with a titanium-nitride
`cap and barrier.
`_
`,
`
`CVD glass containing an average of 5.2 wt.
`percent boron and 3.9 wt. percent
`phosphonls over various densified oxides.
`
`Polycide:
`
`Tungsten silicide.
`
`13
`
`
`
`HORIZONTAL DIMENSIONS
`
`Die size:
`
`Die area:
`
`Min pad size:
`
`Min pad window:
`
`Min pad space:
`
`Min metal 2 width:
`
`Min metal 2 space:
`
`Min metall width:
`
`Min metal 1 space:
`
`Min via (metal 2-to—meta1 1):
`
`Min contact:
`
`Min polycide width:
`
`Min polycide space:
`
`Min poly 2 space:
`
`Min poly 1 width:
`
`Min poly 1 space:
`
`Min gate length (N-channel):
`
`(P-channel):
`
`Cell pitch:
`
`Cell size:
`
`5.8 x 16.6 mm (230 x 656 mils)
`
`97 mm2 (150,880 milsz)
`
`0.11 x 0.12 mm (4.5 x 4.7 mils)
`
`0.1 x 0.11 mm (3.8 x 4.2 mils)
`
`0.12 mm (4.7 mils)
`
`1.3 microns
`
`1.2 microns
`
`0.5 micron
`
`0.7 micron
`
`1.2 microns
`
`0.? micron
`
`0.5 micron
`
`0.65 micron
`
`0.5 micron
`
`0.3 micron
`
`0.5 micron
`
`0.5 micron
`
`0.8 micron
`
`3.64 microns2
`
`1.4 x 2.6 microns
`
`-11-
`
`14
`
`
`
`VERTICAL DIMENSIONS
`
`Die thickness:
`
`MYILS;
`
`Die Coat:
`
`Passivation 3:
`
`Passivation 2:
`
`Passivation 1:
`
`Metal 2 - aluminum:
`
`Interlevel dielectric - glass 3:
`
`- glass 2:
`
`- glass 1:
`
`Metal 1 - cap:
`- aluminum:
`
`- barrier:
`
`Intermediate glass 2:
`
`Polycide - silicide:
`
`- poly 4:
`
`Intermediate glass 1:
`
`Oxide on poly 3:
`
`Poly 3:
`
`Capacitor dielccn-ic:
`
`Poly 2:
`
`Interpoly oxide - total:
`- nitride:
`
`Poly 1:
`
`Local oxide (under poly 1):
`Oxide on N+:
`
`Oxide on P+:
`
`N+ sourcefdrain:
`
`P+ sourcefdrain:
`
`N- wel1:*
`
`13.5 mils (0.3 mm)
`
`9.5 microns
`
`0.55 micron
`
`0.3 micron
`
`0.1 micron
`
`0.9 micron
`
`0.4 micron
`
`0.4 micron
`
`0.08 micron (approx.)
`
`0.04 micron (approx.)
`0.55 micron
`
`0.15 micron
`
`0.5 micron
`
`0.2 micron
`
`0.05 micron (approx)
`0.2 micron
`
`0.1 micron
`
`0.1 micron
`
`150 A (approx)
`0.15 micron
`
`0.35 micron
`
`0.04 micron (approx.)
`0.2 micron
`
`0.3 micron
`
`0.08 micron (approx)
`
`0.06 micron (approx.)
`0.2 micron
`
`0.3 micron
`
`4.5 microns
`
`*1: was not possible to detennine well and substrate polarity with cerraimy.
`
`-12-
`
`15
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