`
`
`
`MICROOHIP
`
`MANUFACTURING 3
`
`
`
`Stanley Wolf PM}.
`
`LATTICE PRESS
`
`Sunset Beach, California
`
`IPR2015—01087
`
`MIT EXHIBIT 2023
`
`Micron V. MIT
`
`

`

`
`
`This publication is based on sources and information believed to be reliable, but the authors
`and LATTICE PRESS disclaim any warranty or liability based on or relating to the contents of
`this publication.
`
`Published by:
`
`LATTICE PRESS
`Post Office Box 340
`Sunset Beach, California 90742, U.S.A.
`
`http://www.latticepress.com
`
`Cover design by: LATTICE PRESS Graphic Arts Department
`Cover image: Lam’s 2300 Excelan® dielectric etch system. shown against a SEM taken following an in—
`situ photoresist strip and dual~damascene etch. Courtesy of Lam Research Corporation.
`
`Copyright © 2004 by LATTICE PRESS.
`All rights reserved. No part of this book may be reproduced or transmitted in any form or by any
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`retrieval system without written permission from the publisher, except for the inclusion of brief quota»
`tions in a review. Requests for permission or further information should be addressed to the Permissions
`Department, LATTICE PRESS.
`
` DISCLAIMER
`
`Library of Congress Cataloging in Publication Data
`Wolf, Stanley, 1943 —
`
`MICROCHIP MANUFACTURING
`
`Includes Bibliographical references and Index
`1. Integrated circuits — Very large scale
`integration — Design and construction. 2. Silicon.
`3. Metal-oxide semiconductors. 4. Silicon technology.
`
`I. Title
`
`ISBN 0~96l672l—8—8
`
`Printed in the United States of America
`
`Printing (last digit): 9 8 7 6 5 4 3 2 l
`
`
`
`

`

` MICROCHIP MANUFACTURING
`
`LOCOS
`Gate Oxide
`Field Oxide
`.v
`
` Wan—mm...“—9».ng
`
`
`
`
`
`Fig. (4-22 The silicon wafer surface after: (a) etching back the
`pad—oxide to bare silicon; and (b) growing the gate—oxide.
`
`performed sequentially using the same implanter,
`along with the NMOSFET VT-adjust implant.
`
`14.2.5 Galawflxltle Growth
`
`In the next step, the gate-oxide is formed. The growth
`of the gate-oxide is critical. A defect-free, very-thin
`(6-20—nm), high-quality oxide without contamination
`is essential for proper device operation. The gate—
`oxide is grown only on the exposed active-regions
`(following a careful cleaning of the wafer surface just
`prior to an oxide growth-process in dry—02).
`Since the drain—current
`in an MOS transistor is
`inversely proportional
`to the gate—oxide thickness
`
`Polysilicon Film (Deposit Undoped by CVD, Then
`Heavily Dope with Phosphorus,
`
`by Diffusion or ion-Implantation)
`
`
`
`Fig. “~23 A layer of undoped—polysilicon is next blanket~
`deposited using LPCVD. Diffusion or ion—implantation is
`used to heavily-dope the polySi layer with phosphorus.
`
`
`
`(for a given set of terminal voltages), the gate-oxide
`is normally made as thin as possible (commensurate
`with oxide—breakdown and reliability considerations).
`For the 0.35-1.0—ym generations of CMOS, the gate»
`oxide used is lO—ZO-nm thick.
`(See Chap. 13 for
`details on thin gate—oxide growth.) The wafer after
`this gate-oxide growth process is shown in Fig. 4-22.
`
`14.2.6 Pulvsilicon-Denositinn anti Patterning
`
`Once the gate—oxidation step is completed, a heav-
`ily n—doped polysilicon—gate structure is fabricated.
`Polysilicon is the preferred gate material for several
`reasons. First, it can withstand the high—temperature
`steps required to form the source/drain junctions.
`Second,
`the poly/SiO2 interface is well understood
`and electrically stable. The gate—formation procedure
`begins with the deposition of a O.4—«O.5~]4m—thick,
`undoped polysilicon-film by LPCVD (Fig. 4—23, see
`also Chap. 16). This layer is then doped with phos-
`phorus by ion-implantation or chemical—doping, pro—
`ducing a film with a sheet resistance of 20—30~Q/sq.
`The
`gate-structure
`(and
`polysilicon-intercon—
`neat—structures) are then patterned using Mask #6.
`Following exposure and development of the resist,
`the polysilicon—film is dry—etched (Fig. 4~24). This is
`also a critical etch—step for several reasons. First, due
`to the self-aligned nature of silicon-gate technology,
`
`MASK #6
`Gate
`Oxide
`
`Polysmcon Gates
`
`\
`
`
`
`
`
`
`
`Fig. [#24 Photoresist is applied, and Mask #6 is used to
`define the gates of the MOSFETs in the polysilicon—film. An
`anistoropic polySi dry—etch—step defines their gatelength.
`Following this etch, the resist is stripped.
`
`
`
`

`

`CHAPTER 4
`OVERVIEW OF CMOS PROCESS INTEGRATION
`
`
`
`the channel-length of the device depends on the width
`of the polysilicon-line. Hence, the gate~length dimen-
`sion must be precisely maintained across the entire
`wafer (and from wafer—t0~wafer). If the gate-length
`is too long, the drain—current of the MOSFETs will
`decrease, slowing-down the performance of the IC. If
`the gate—length is too short, the source and drain may
`punch—through. In addition, the profile of the etched
`poly~gate structure should be vertical. This prevents
`variation of channel-lengths (due to penetration of the
`ions of the thinner regions of the gate sidewalls during
`formation of the source/drain regions by ion-implan—
`tation). Finally, to achieve the above goals, an aniso—
`tropic polysilicon-etchuprocess must be employed.
`This process, however,
`requires overetching to
`remove the locally thicker regions of polysilicon that
`exist wherever it crosses steps on the wafer surface
`(see Fig. 22-13). During this overetch—time, areas of
`the thin gate—oxide are exposed to the etchants. Thus,
`it is necessary to use a polysilicon etch-process that is
`highly—selective with respect to Si02 (see Chap. 22).
`
`(4.3.7 Formation of Source/Drain Regions
`
`The next step in the processmflow is the formation
`of source and drain (S/D) regions of the MOSFETs.
`Such regions are paths of current-flow in the silicon
`
`MASK#73i§i‘§§§%
`tlrirléiliréa
`
`
`
`
`Fig. 4-25 Photoresist is applied, and Mask #7 is used to
`cover the regions where PMOSFETS exist. A shallow arse—
`nic—implant provides the doping for the Zightly—doped—drain
`(LDD) regions of the NMOSFETS.
`
`
`
`
`
`Fig. 4*26 Photoresist is applied, and Mask #8 is used to
`cover the regions where NMOSFETS exist. A shallow
`boron—implant provides the doping for the lightly—doped—
`drain (LDD) regions of the PMOSFETs.
`
`between the metal interconnect—lines and the channel
`
`of the transistor. As such, it is important that they have
`the lowest possible resistance. In addition, submicron—
`MOSFETs require S/D junctions to be as shallow as
`possible to suppress such short-channel effects as
`punchthrough (see Ref. 2). To obtain low resistivity,
`the S/D regions are doped as heavily as possible (typi—
`cally using ion~implantation, with a dose on the order
`of ~1015 cm"3). The NMOS S/D regions are doped
`with arsenic because it has a high-solubility, low-dif—
`fusivity, and a shallow projected—range at the low ion—
`.
`.
`.,
`+
`implantation energies that are used. Boron or BF2 are
`used to dope the PMOSFET S/D regions. However,
`boron has a higher~diffusivity in Si than does arse“
`nic. Hence, shallow S/D—junctions in PMOSFETS are
`harder to achieve than in NMOSFETs.
`
`gate—lengths
`processes,
`submicron—CMOS
`In
`become so small
`that
`lightly—doped—drain (LDD)
`structures must be used to minimize hot—electron
`
`effects, especially in NMOS devices. Thus, proce—
`dures are integrated into the CMOS process-flow to
`fabricate such LDD—structures. If LDD—structures are
`
`needed for both PMOS and NMOS devices, two more
`masking—layers are needed.
`The LDD—structures are formed in the follow—
`
`
`
`
`

`

` MlCROCHIP MANUFACTURING
`
`Poly-Gate Sidewall~Spacers
`formed by Anistropic Etching
`\
`
`
`
`is etched—back
`(4-28 The deposited dielectric—layer
`Fig.
`anisotroppically, leaving sidewall—spacers along the edges
`of the polysilicon gate—structures.
`
`used to define the areas where heavily—doped PMOS
`source/drain regions will be located (Figure 4—30).
`These are formed with a heavy-dose boron implant—
`step (dose = 1x1015—3x1015 B—ions/cm2 at 50—keV).
`In the final step of the active—device formation
`process, a furnace anneal (typically at ~900°C for 30
`min, or a rapid—thermal—anneal [RTA] for ~l min at
`lOOO~lOSO°C) is carried out. This thermal-step acti-
`vates all the implants, anneals the implant—damage,
`and drives the junctions to their final depths.
`
`54.2.3 Formatian at TiSiz Saliuidfi
`After stripping the thin-oxide on the active—Si regions
`and cleaning the wafer surface (to ensure that no
`
`
`
`Fig. 4-29 After applying resist, Mask #9 is used to cover the
`regions with PMOSFETS. A phosphorus—implant is used to
`form the n+—source/drain regions of the NMOSFETS.
`
`
`
`
`
`ing way. Resist is spun on, and Mask #7 is used to
`protect all the devices except the NMOS-transistors
`(Fig. 4—25). The lightly—doped regions of the NMOS
`source and drain are created with an ion—implant step.
`Arsenic at a dose of approximately 3x1013—3x1014
`cm’3 dopant—ions is implanted at low—energy (3050—
`keV). The implant—process causes the edge of these
`implanted ions to be automatically aligned to the edge
`of the gate (i.e., it is a self—aligned process).
`The resist is stripped and a new layer of resist
`is spun~on, and Mask #8 is used to protect all the
`devices except the NMOS transistors (Fig. 4—26). The
`lightly—doped regions of the PMOS source and drain
`are created with an ion-implant step. Boron at a dose
`of between 3x1013—3x1014/cm2 ions is implanted at
`low-energy (30—50—keV), and the resist is stripped.
`A conformal layer of dielectric material (usually
`SiO2 or silicon—nitride) is then deposited over the
`entire wafer (Fig. 4-27). An anisotropic—etch process
`is used to clear the oxide in the flat areas while leav-
`ing spacers on the sidewalls of the poly gates (Fig.
`4-28). These spacers cover and protect the regions
`beneath them from the subsequent high~d0se implants
`that form the rest of the S/D regions.
`A photoresist layer and Mask #9 is used to define
`the areas where the heavily-doped regions of the
`NMOS source and drain will be located.
`(Figure
`4—29). These are formed with a heavy—dose arsenic
`implant-step (dose 2 2x1015—4x1015 As~ions/cm2 at
`40—80~keV). A photoresist layer and Mask #10 is then
`
`Spacer Dielectric—Film, Deposited by CVD
`
`
`
`
`
`
`
`Fig. 4-27 A conformal layer of Si02 or SiN is deposited by
`CVD in preparation for the sidewall—spacer formation.
`
`
`
`

`

`CHAPTER 4
`
`
`
`OVERVIEW OF CMOS PROCESS INTEGRATION
`
`
`
`
`
`$213. #132 A thin—layer of titanium (Ti) is blanket—deposited
`over the wafer—surface by sputtering.
`
`Ti-etch—step, the wafer is heated to 8000C for about
`1—minute in NZ (to reduce the resistivity of the TiSiZ»
`layer to its final value of ~1 Q/sq). Figure 4-34 shows
`the details of the Ti—salicide formation process.5a6
`
`
`fltfifl mama.
`mfi
`
`
`ififlfifiizfi
`
`Following formation of the source and drain regions
`and the Ti—salicide structure, a doped dielectric-film is
`deposited by CVD. This layer is known as an interlevel
`dielectric (ILD). Contact-windows are opened in this
`dielectricwlayer to allow electrical connections to be
`made between Metalvl and the following structures:
`
`
`
`W and emit: Ti, Quip Ream
`andm arm a» Fem ramming
`
`
`
`
`
`
`
`
`
`14-3fi After applying resist, Mask #10 is used to cover
`,
`..
`the regions with NMOSFETs. A boron—implant is then used
`to form the p+—source/drain regions of the PMOSFETs.
`
`native—oxide exists on the exposed silicon of the
`active regions and on the polysilicon-gates, Fig.
`4~31), a thin-layer of titanium (Ti) is deposited by
`sputtering (50—100—nm thick, Fig. 4—32). The next
`step makes use of two chemical reactions. The wafers
`are first heated to 600°C in an N2~ambient for a short
`time (about l-min). At this temperature, the Ti reacts
`with Si where they are in contact to form TiSiZ. TiSi2
`forms a low—resistance~contact to silicon, and it is also
`an excellent conductor. The wafer is then immersed in
`
`a solution of NH4OH2H202:HZO (1:125) to selectively
`remove the unreacted Ti (i.e., on regions of the wafer
`covered with SiOg), but the TiSiZ remains in regions
`over Si where it had reacted (Fig. 4—33). After this
`
`
`
`
`
`
`
`
`
`
`
`
`
`.
`
`
`Embawayflxide{mm all Wrwna 1’01me
`
`.
`
`.
`
`/
`
`,.
`
`l
`
`
`
`
`
`
`
`. am An etch—step is used to remove the thin—oxide
`layer that covers the source/drain and gate«poly regions of
`l MOSFETs, in preparation for salicide formation.
`
`HE. $4.33 A lower—temperature anneal—step (600°C, 1—min
`RTP in N2) converts the Ti to TiSi2 on regions where Ti is
`contact with Si. Elsewhere, Ti does not react, and can there—
`fore be selectively removed with a wet—etch step. A second,
`higher—temperature anneal—step (800°C, 1—min RTP in N2)
`converts the TiSiZ to its final, lower~resistance form.
`
`

`

`
`
`
`
`Deposited oxide
`
`Oxide
`spacer
`
`(c)
`Self—a1 igned
`metal
`silicide (salicide)
`
`W.~MME<«,.W..WWW‘W. WWWa....mvw
`
`
`
`MICROCHIP MANUFACTURING
`
`
`
`
`
`
`Deposit Inter-Level-Dielectric (ILD) Layer by CVD,
`Then Planarize thiskfiyer with Oxide-CMP Process
`CVD-Oxide "
`
`
`
`Fig. [4-35 A conformal interlevel—dielectric layer (typically
`CVD—SiOz) is deposited. Then chemical—mechanical pol—
`ishing (CMP) is used to planarize the steps of the ILD.
`
`is either phosphorus (P ~ in which case the material is
`referred to as phosphosilicate glass or PSG), or both P
`and B (borophasphosilicate glass or BPSG).
`The doped CVD SiOTlayer plays several roles in
`the fabrication and operating aspects of the circuit.
`First, it acts as an insulating-layer between polySi and
`Metal—1. Second, it reduces the parasitic~capacitance
`between Metal—l and the substrate. Third, adding P
`to the glass makes the layer an excellent getter of Na
`ions (contamination by Na can destabilize the VT of
`a MOSFET). The PSG (or BPSG) binds otherwise
`mobile Na—atoms in the doped—glass layer, preventing
`them from reaching the gate-oxide and altering VT.
`Note that the surface of the wafer after the ILD
`
`deposition is highly nonplanar. For the sake of reduc~
`ing potential problems with metal discontinuities, it
`would be preferable not to deposit the metal directly
`on such rough topography. To avoid having to do this,
`a variety of techniques were developed to planarize
`(or flatten) this topography, including BPSG~refl0w
`(see Chap. 16).
`However,
`the method that provides the highest
`level of planarity is chemical-mechanical polishing
`(CMP), and is described here (see also Chap. 23).
`The ILD—layer is deposited thicker than the largest
`steps present on the wafer surface (that is, thicker
`than ~l pm). The wafer is then placed face—down in a
`CMP-tool, and its upper-surface is polished-flat using
`
`Reduced sheet resistance
`
`~~ Reduced gate 10
`SID resistance
`
`
`
`Reduced contact resistance
`
`‘r‘ Reduced diode leakage
`
`Fig. 4-314 Process sequence used to form tianium-salicide;
`(a) Form the standard MOSFET structure up to source and
`drain; (b) Form sidewall—spacers; (c) Deposit Ti—film and
`react to form TiSi2 in regions where Ti is in contact with Si;
`(d) Selectively remove unreacted Ti film; (e) a perspective
`drawing of the final salicide—structure.
`
`1) source/drain contact regions: 2) gate contacts; 3)
`substrate—contact regions; and 4) well—contact regions.
`A CVD—process is used to deposit this doped SiOp;
`film (about l—nm thick), onto the wafers (see Chap.
`16 for details of this process). The dopant in the Si02
`
`
`
`

`

`OVERVIEW OF CMOS PROCESS INT
`EGRATIONWmM
`
`
`
`
`
`CHAPTER 4
`M Mmmmwmmmmmmwwnwflmmm
`
`a-high"pH silica-slurry. This CMP—process results in a
`
`structure that is shown in Fig. 4-35.
`, Contact~openings are next created by a lithogra—
`
`- phy~and~etch step (Fig. 4-36). After applying resist,
`
`Mas/C #1] is used to define contact-patterns in a photo~
`
`_. resistwfilm. A dry-etch process is then used to open the
`
`icontactuwindows through the ILD to the underlying
`{pblySi and the source/drain regions in the silicon.
`
`
`:
`‘ This contact—opening step can be critical, as the
`
`Contact size and its alignment to underlying patterns
`
`limit the minimum-size of the device. The source/
`drain regions must also be large enough for the con—
`
`tact to fit, with an allowance for alignment tolerance.
`
`If the contact opening exposes a part of the substrate,
`
`the drain or source will be shorted to it. Likewise, if
`the contact»0pening overlaps the both the source/drain
`
`and the gate, a short will be created between them.
`
`
`4.2.19 Metal—1 napusittan amt Patterning
`
`After the contacts have been opened, the metallization
`
`layer is deposited. Because the metal—layer is highly
`
`conductive, it is used whenever possible to intercon-
`
`nect circuit~elements and to carry large amounts of
`
`supply—current. Metal interconnect~lines must have
`
`sufficient thickness, width, and step—coverage to keep
`the current—density in each line below the level that
`
`MASK #11
`Mask and Etch Contact Holes in ILD
`
`
`
`
`
`
`
`
`
`
`
`
`
`Deposit TiN-liner by PVD, and W-
`
`Fig. 4‘37 To form the tungsten—contact holes, an adhe-
`sion—layer of titanium—nitride (TiN) is first blanket—
`sputter—
`deposited onto the wafer. Then a CVD
`—pr0cess is used to
`blanket—deposit a film of tun
`gsten. This W—film completely
`fills the contact-holes.
`
`could produce electromigration failure (see Ref. 2). In
`addition, the space between adjacent metal—lines must
`be large enough so that the lines never touch, even
`under worst-case process variations.
`The metallization—structure is formed using two
`separate processes: 1) W—plug formation; and 2) main
`interconnect—Zine formation, using an Aeru film. In
`the W~plug formation~process a thin barrier/glue
`layer of Ti/TiN is first blanket~dep0sited by sputter—
`ing (a few tens—of—nm thick). It provides good adhe—
`sion to the SiO2 and other underlying materials, as
`well as serving as an effective barrier-layer between
`the upper and lower metal-layers. The next step is
`deposition of a blanket-W layer by CVD, as shown
`in Fig. 4—37. CMP is then used to planarize the wafer
`surface, and to remove the W and Ti/TiN everywhere
`but in the contact-holes. Thus, W—plugs are formed, as
`shown in Fig. 488.
`lines are formed from
`The main—interconnect
`A1:Cu—alloy films that are deposited next by sputter-
`
`
`ing. A resist—layer and Mask #12 are used to define
` * Fifi. (93$ After applying resist, Mask #1] is used to pat—
`these main interconnect~line patterns (Fig. 4—39),
`
`- tern the contact~opening regions. A dry—etch step is used to
`which are then formed using a dry~etching process
`
`anisotropically etch the ILD layer to allow connections to
`(Fig. 4—40). Note that Cu is replacing AlzCu in some
`
`* be made to the silicon~substrate (and polysilicon layers).
`of the most advanced IC~technologies, because of its
`
`higher~conductivity and better electromigration resis—
`
`
`
`
`
`
`

`

`W:
`MICROCHIP MANUFACTURING
`
`Farm weptuge by Using CMP toWe the
`Wefilm and the TiN film an the Tap IUD gimme
`
`fig” «4&3? The W and TiN that is deposited on the top sur—
`face of the ILD is removed by a CMP process, leaving just
`W—plugs.
`
`tance (see Chap. 24). Figure 4—41 shows a SEM of
`A12Cu—interconnect—lines (Metal-1) and Wuplugs.
`If a single—level of metal is used in the CMOS pro—
`cess, a sintering-step occurs after the metal has been
`patterned. This step brings the metal and the n+ and
`p+ regions in the silicon into intimate contact. Such
`intimate contact between the metal and the heavily—
`doped Si regions establishes low—resistance ohmic
`contacts. The annealing—process also exposes the
`wafer to a 375—5000C temperature in an H2, or N2
`+ H2 (5%) ambient for about 30 minutes. This step
`also serves as the annealing-process for reducing the
`
`
`
`mm #121
`
`AM?“ Alla}? Film Welt El:
`
`
`
`Etch AM)“ NEW Film mid Stripm
`
`
`
`this. 5%“ng The AlzCu Metal—l lines are created by using an
`anisotropic Al dry-etch process. The resist then stripped.
`
`interface-trap-density in the gate-oxide that was intro—
`duced by earlier processing steps (see Chap. 13).
`
`ills»
`tflgfitfi
`
`
`Emil
`Ffifififilfifi,
`
`Most modern ULSI technologies use more than one
`level of wiring on the wafer surface. This is because
`in complex circuits it is usually very difficult to com-
`pletely interconnect all the devices in the circuit with—
`out using multiple interconnect—levels. The processes
`used to deposit and define each level are similar to
`those we described for Metal—l. Here we show a two—
`
`
`
`interconnect—structure
`tilalllEl A SEM of a Metal—1
`illlll.
`formed with W—plugs and AlzCu interconnect—lines. Note
`that the ILD has been removed to make it possible to see
`the W—plugs. Photograph courtesy of ChipWorks.
`
`
`
`
`fifl. ‘Elr'flfig An Al:Cu alloy film is sputter deposited onto the
`wafer. Photoresist is applied and Mask #12 is used to define
`the Metal—l lines that be formed from the AlzCu film.
`
`
`
`

`

`My:
`
`OVERVIEW OF CMOS PROCESS FINTEGRATION
`CHAPTER 4
`
`
`MASK #13 & MASK #14
`
`Form IMD, Metal-2,
`and Passivation
`
`Passivation Layer
`
`
`
`Fig. [4-42 Metal-2 is formed with the same steps as those
`shown in Figs. 4—35 to 4—40. Mask #13 is used to define
`the Via—holes between Metal-l and Metal-2. Mask #14 is
`
`used to define Metal-2. A final passivation—layer (typically
`CVD-oxide, or CVD—nitride — or both) covers the chip.
`
`level-metal interconnect structure, but the faceplate of
`the chapter shows a cross-sectional drawing of an IC
`with 6-levels of metal.
`
`To create the second interconnect—level, an inter—
`metal dielectric (IMD) must first be deposited. It elec—
`trically isolates the Metal-l layer from the Metal-2
`layer. Next, vias must be opened in this IMD-layer so
`that electrical connections can be established between
`
`Metal-2 and Metal-l at desired locations (Mask #13).
`
` '
`
`Fig. 4-43 SEM of an IBM circuit showing a two-level—metal
`interconnect structure formed with W—plugs and Al~lines.
`Photograph courtesy of Chip Works.
`
`W—plugs and an Aeru-layer and a lithographic—step
`using Mask #14 are used to form the Metal-2 inter-
`
`connect—structures (Fig. 4-42). Figure 443 shows a
`SEM of a two—level-metal structure formed using Al—
`lines and W—plu gs.
`As noted above, more advanced ICs now use more
`
`interconnects. Figure 4—44
`than 2—levels of metal
`shows a SEM of a four-level interconnect—structure.
`
`More details about fabricating such multilevel inter—
`connect—structures are found in Chap. 24 and Ref. 3.
`
`4.2.12 Passivation Laver and Pat! Mask
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`Finally, a passivation (or overcoat) layer, such as
`CVD-PSG or plasma«enhanced—CVD silicon—nitride
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` Probing
`pad
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`Bonding centric:
`mask pattern
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`Fig. 14-35 Passivation layer SEM. Courtesy of ChipWorks.
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`(or both), is put down onto the wafer surface (Fig.
`4—45). This layer seals the device structures on the
`wafer, protecting them from contaminants and mois-
`ture. It also serves as a scratch-protection layer.
`Openings are etched into this layer so that a set of
`special metallization—patterns under the passivation
`layer is exposed. These metal-patterns are normally
`located in the periphery of the circuit and are called
`bonding-pads (Fig. 4-46). Bonding-pads are typically
`about
`lOOXlOO-ptm in size and are separated by a
`space of 50 to lOO—Mm. Wires are connected (bonded)
`to the metal of the bonding-pads and are then bonded
`to the chip—package.
`In this way connections are
`established from the chip to the package-leads (see
`Chap. 27 for details on chip—bonding).
`The bond-pad openings are created by patterning
`the passivation-layer with Mask #15. If a PSG-layer is
`used, the phosphorus (2—6—wt%) in the glass not only
`causes it to act as a getter for Na, but also prevents the
`film from cracking. Care must be taken to ensure that
`not more than 6%—phosphorus is incorporated into
`the PSG, as this can cause corrosion of the underly—
`ing metal if moisture enters the circuit—package (see
`Chap. 22). When silicon-nitride is used, care must be
`taken to ensure that the deposited nitride-film exhibits
`low—stress (either tensile or compressive), so it will
`not crack. Cracking would compromise the sealing
`capability of the final passivation—film.
`54.3 SHALLQWJRENEH ISBLAHEEN {STD
`Despite advances made to decrease bird’s beak
`penetration in LOCOS isolation, such techniques
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`Bonding Pads
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`Bonding contact
`W1
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`Passivation
`layer
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`Bio2
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`Fig. 4-“ (a) Drawing, and (b) SEM of bonding—pads.
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`eventually became inadequate for deep—submicron
`lC—technologies. The successor to LOCOS in CMOS
`is shallow-trench isolation (STI).7=8 Note that STI is
`not only is a different type of isolation—structure but it
`is also formed prior to the well—structures. In addition,
`STI provides a planar surface for further processing.
`The sequence of steps for forming STl—structures
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