Construction Analysis
`
`Motorola PC603R
`Microprocessor
`
`Report Number: SCA 9709-551
`
`e m i c o nductorIn
`
`dustr y
`
`®
`
`S
`
`i n c e 1964
`
`bal S
`
`rvingtheGlo
`
`e
`
`S
`
`17350 N. Hartford Drive
`Scottsdale, AZ 85255
`Phone: 602-515-9780
`Fax: 602-515-9781
`e-mail: ice@ice-corp.com
`Internet: http://www.ice-corp.com
`
`IPR2015-01087 - Ex. 1033
`Micron Technology, Inc., et al., Petitioners
`1
`
`

`

` INDEX TO TEXT
`
` TITLE
`
`INTRODUCTION
`MAJOR FINDINGS
`
`TECHNOLOGY DESCRIPTION
`Assembly
`Die Process
`
`ANALYSIS RESULTS
`Die Process and Design
`
`ANALYSIS PROCEDURE
`
`TABLES
`Overall Evaluation
`Package Markings
`Die Material Analysis
`Horizontal Dimensions
`Vertical Dimensions
`
` PAGE
`
` 1
` 1
`
` 2
`2 - 3
`
`4 - 7
`
`8
`
`9
`10
`10
`11
` 12
`
`- i -
`
`2
`
`

`

` INTRODUCTION
`
`This report describes a construction analysis of the Motorola PC603R Microprocessor.
`Two engineering samples were supplied for the analysis. The devices were received in
`256-pin Ball Grid Array (BGA) packages date coded 9713.
`
` MAJOR FINDINGS
`
`Questionable Items:1
`
`• Significant misalignment of metal 2 and 4 to the underlying plugs was noted
`(Figures 19 and 29)
`
`Special Features:
`
`• Six metal, P-epi, BiCMOS process.
`
`• Metal 1 (tungsten) was defined by a damascene process. Stacked vias were
`employed.
`
`• Chemical-mechanical-planarization (CMP).
`
`• Oxide-filled shallow-trench isolation.
`
`• Titanium silicided diffusion structures.
`
`• Aggressive design rule features (0.2 micron gates).
`
`1These items present possible quality or reliability concerns. They should be discussed
`with the manufacturer to determine their possible impact on the intended application.
`
`- 1 -
`
`3
`
`

`

` TECHNOLOGY DESCRIPTION
`
` Assembly:
`
`• The devices were packaged in 256-pin (255 actual pins) Ball Grid Arrays (BGAs).
`The die was mounted surface down on the ceramic substrate (C4 flip-chip
`assembly).
`
`• A blue colored underfill was present between the die surface and the ceramic
`substrate.
`
`• Solder balls were employed for all connections to die metallization (C4 flip-chip
`process). There appeared to be space for standard bond pads around the die
`perimeter although used for protection diodes (?) in this case (see Figure 6).
`
`• Sawn dicing (full depth).
`
` Die Process:
`
`• Fabrication process: Oxide-filled shallow-trench isolation, BiCMOS process
`employing twin-wells in an apparent P-epi on a P substrate.
`
`• Die coat: A thin patterned polyimide die coat was present over the entire die.
`
`• Final passivation: A layer of nitride over a layer of glass.
`
`• Metallization: Six levels of metal defined by standard dry-etch techniques (except
`M1). Metal 1 (tungsten) was defined by a damascene process. Metals 2 - 6
`consisted of aluminum. Metal 6 did not employ a cap or barrier metal. Metals 2 - 5
`employed titanium-nitride caps and barriers. Tungsten plugs were employed for
`vias under metals 2 - 5. Metal 6 used standard vias. All tungsten plugs and
`tungsten metal 1 were lined with titanium-nitride. Stacked vias were employed at all
`levels. Elongated vias (M6 - M3) and contacts (M1) were also present.
`
`- 2 -
`
`4
`
`

`

` TECHNOLOGY DESCRIPTION (continued)
`
`•
`
`Interlevel dielectrics: Interlevel dielectric 5 (between M5 and M6) consisted of two
`layers of glass. The first layer was subjected to an etchback. Interlevel dielectrics 2 -
`4 used the same dielectric structure. A very thin glass was deposited first, followed
`by three separate layers of glass. The third layer of glass was planarized by CMP
`which left the surface very planar. The fourth layer appeared to have been similarly
`planarized during tungsten plug CMP. Interlevel dielectric 1 (between M1 and M2)
`consisted of a single thick layer of glass which had also been subjected to CMP.
`
`• Pre-metal glass: A thin layer of glass over a thick layer of glass and a thin nitride.
`This dielectric was also planarized by CMP.
`
`• Polysilicon: A single layer of dry-etched polycide (poly and titanium-silicide). This
`layer was used to form all gates on the die. Nitride sidewall spacers were used to
`provide the LDD spacing.
`
`• Diffusions: Implanted N+ and P+ diffusions formed the sources/drains of
`transistors. Titanium was sintered into the diffusions (salicide process).
`
`•
`
`Isolation: Field oxide consisted of oxide-filled shallow-trench isolation. It was very
`planar with the diffused silicon surfaces. A small step was noted on top of the
`trench oxide at well boundaries.
`
`• Wells: Twin-wells in a P-epi on a P substrate.
`
`• SRAM: On-chip cache memory cell arrays were employed. The memory cells used a 6T
`CMOS SRAM cell design. Metal 3 formed the bit lines and metal 2 distributed GND and
`Vcc throughout the cells and was used as “piggyback” word lines and cell interconnect.
`Metal 1 also provided cell interconnect. Polycide formed the select and storage gates. Cell
`pitch was 3.5 x 5.1 microns (17.8 microns2).
`
`• There appeared to be bipolar devices on the die; however, we could not verify them
`in cross-section due to our inability to see them before complete delayering.
`
`• No redundancy fuses were found.
`
`- 3 -
`
`5
`
`

`

` ANALYSIS RESULTS
`
` Die Process and Design :
`Questionable Items:1
`• Significant misalignment of metal 2 and 4 to the underlying plugs was noted
`(Figures 19 and 29)
`
` Figures 1 - 46
`
`Special Features:
`• Six metal, P-epi, BiCMOS process.
`
`• Metal 1 (tungsten) was defined by a damascene process. Stacked vias were
`employed.
`
`• Chemical-mechanical-planarization (CMP).
`
`• Oxide-filled shallow-trench isolation.
`
`• Titanium silicided diffusion structures.
`
`• Aggressive design rule features (0.2 micron).
`
`General items:
`• Fabrication process: Oxide filled shallow-trench isolation, BiCMOS process
`employing twin-wells in an apparent P-epi on a P substrate. No problems were
`found in the process.
`
`• Design implementation: Die layout was clean and efficient. Alignment was
`adequate at most levels; however, alignment of metals 2 and 4 to their respective
`underlying plugs was poor. Plug coverage was only 35-to-40 percent at some metal
`2 and 4 vias. Some isolated metal 6 vias were noted on the die (see Figure 6).
`
`1These items present possible quality or reliability concerns. They should be discussed
`with the manufacturer to determine their possible impact on the intended application.
`
`- 4 -
`
`6
`
`

`

` ANALYSIS RESULTS (continued)
`• Surface defects: No toolmarks, masking defects, or contamination areas were found.
`
`• Die coat: A patterned polyimide die coat was present over the entire die surface.
`
`• Final passivation: A layer of nitride over a layer of glass. Coverage was good. Edge seal was
`also good as the passivation extended to the scribe lane to seal the metallization. A cutout was
`present in the passivation and ILD 5 around the die perimeter to prevent cracks from radiating
`over the circuitry.
`
`• Metallization: Six levels of metal interconnect. Metals 2 - 6 consisted of aluminum. Metals 2 - 5
`employed titanium-nitride caps and barriers. Metal 6 did not employ a cap or barrier metal.
`Tungsten plugs were employed with metals 2 - 5. All plugs were lined with titanium-nitride
`underneath and over top. Standard vias were employed under metal 6. Metal 1 consisted of
`tungsten defined by a damascene process. The metal 1 tungsten was also lined with titanium-
`nitride.
`
`• Metal patterning: All aluminum metal levels were defined by a dry etch of good quality. Metal
`lines were only widened at metal 6 via connections.
`
`• Metal defects: None (excluding misalignment). No voiding, notching or cracking of the metal
`layers was found. No silicon nodules were found following removal of the metal layers.
`
`• Metal step coverage: Metal 6 thinned up to 75 percent at vias. Although the thinning exceeds
`MIL-STDs (70 percent) it is not considered a reliability concern. No metal thinning was present
`at the connections to the tungsten via plugs or metal 1. The absence of thinning is due to the good
`control of plug height and the planarization technique employed.
`
`• Vias and contacts: All via and contact cuts were defined by a dry etch of good quality. Again
`there was significant misalignment of metal 2 and 4 to their respective plugs. This misalignment
`reduced metal spacing to adjacent plugs (see Figure 32). Some tungsten plugs “spilled over” one
`edge of the metal. IBM uses this “borderless” contact technique for improved contact resistance.
`Vias and contacts were placed directly over one another (stacked vias). No problems were noted.
`
`- 5 -
`
`7
`
`

`

` ANALYSIS RESULTS (continued)
`•
`Interlevel dielectrics: Interlevel dielectric 5 (between M5 and M6 ) consisted of two layers
`of glass. The first layer was subjected to an etchback. Interlevel dielectrics 2 - 4 consisted
`of the same type of oxide structure. A very thin glass was deposited first, followed by three
`separate layers of glass. The third and fourth layers of glass were subjected to CMP which
`left the surface very planar. No CMP was performed on ILD 5 (under M6). Interlevel
`dielectric 1 (between M2 and M1) consisted of a single thick layer of glass which had also
`been subjected to CMP. No problems were found with any of these layers.
`
`• Pre-metal glass: A thin layer of silicon-dioxide over a thick layer of glass and a thin nitride.
`This layer was also planarized by chemical-mechanical-planarization. No problems were
`found.
`
`• Polysilicon: A single level of polycide (poly and titanium-silicide) was used. It formed all
`gates and word lines in the array. Definition was by dry etch of good quality. Nitride
`sidewall spacers were used throughout and left in place. No problems were found.
`
`•
`
`Isolation: The device used oxide-filled shallow-trench isolation which was quite planar with
`the silicon surface. A small step was noted on top of the trench oxide at well boundaries.
`No problems were present.
`
`• Diffusions: Implanted N+ and P+ diffusions were used for sources and drains. Titanium
`was sintered into the diffusions (salicide process) to reduce series resistance. An LDD
`process was used employing nitride sidewall spacers.
`
`• Wells: Twin-wells were used in a P-epi on a P substrate. Definition was normal. We
`could not delineate the P-well in cross-section.
`
`• Buried contacts: Direct poly to diffusion contacts were not used.
`
`• SRAM: As mentioned, on-chip cache memory cell arrays were employed on the device.
`The SRAM cell array used a 6T CMOS SRAM cell design. Metal 3 formed the bit lines.
`Metal 2 distributed GND and Vcc throughout the cells and was used as “piggyback” word
`lines and cell interconnect. Metal 1 also provided cell interconnect. Polycide formed the
`word lines/select and storage gates. Cell pitch was 3.5 x 5.1 microns.
`
`- 6 -
`
`8
`
`

`

` ANALYSIS RESULTS (continued)
`
`• There appeared to also be bipolar devices on the die as observed from the surface.
`Since they could only be seen once the die was delayered we were unsuccessful in
`obtaining a cross section through one of these devices to observe the sectional
`structure.
`
`• No redundancy fuses were noted.
`
`- 7 -
`
`9
`
`

`

` PROCEDURE
`
`The devices were subjected to the following analysis procedures:
`
`External inspection
`
`X-ray
`
`Die optical inspection
`
`Delayer to metal 6 and inspect
`
`Aluminum removal (metal 6)
`
`Delayer to metal 5 and inspect
`
`Aluminum removal (metal 5) and inspect tungsten plugs
`
`Delayer to metal 4 and inspect
`
`Aluminum removal (metal 4) and inspect tungsten plugs
`
`Delayer to metal 3 and inspect
`
`Aluminum removal (metal 3) and inspect tungsten plugs
`
`Delayer to metal 2 and inspect
`
`Aluminum removal (metal 2) and inspect tungsten plugs
`
`Delayer to metal 1 and inspect
`
`Tungsten removal (metal 1)
`
`Delayer to polycide/substrate and inspect
`Die sectioning (90(cid:176) for SEM)
`
`Measure horizontal dimensions
`
`Measure vertical dimensions
`
`Die material analysis
`
`- 8 -
`
`10
`
`

`

` OVERALL QUALITY EVALUATION : Overall Rating: Normal.
`
` DETAIL OF EVALUATION
`
`Package integrity
`Package markings
`Die placement
`Solder ball placement
`Solder ball interconnect quality
`Dicing quality
`Die attach quality
`Die attach method
`Dicing method
`
`Die surface integrity:
`Toolmarks (absence)
`Particles (absence)
`Contamination (absence)
`Process defects (absence)
`General workmanship
`Passivation integrity
`Metal definition
`Metal integrity
`
`Metal registration
`
`Contact coverage
`Via/contact registration
`Etch control (depth)
`
`G
`G
`G
`G
`G
`N
`G
`C4 solder ball interconnect technique
`Sawn
`
`G
`G
`G
`G
`G
`G
`G
`N
`
`NP1
`
`NP1
`N
`N
`
`1Misalignment of M2 and M4 to underlying plugs.
`
`G = Good, P = Poor, N = Normal, NP = Normal/Poor
`
`- 9 -
`
`11
`
`

`

` PACKAGE MARKINGS
`
` TOP
`
`(Logo) XPC603RRX250LA
`70H92D DTC9713B
`S23687 W001
`
` DIE MATERIAL ANALYSIS
`
`Final passivation:
`
`Single layer of nitride over a single layer of glass.
`
`Metallization 6:
`
`Aluminum.
`
`Interlevel dielectric 5:
`
`Two layers of glass.
`
`Metallization 2 - 5:
`
`Aluminum with titanium-nitride caps and barriers.
`
`Interlevel dielectrics 2 - 4:
`
`A thin layer of glass followed by three layers of
`glass.
`
`Interlevel dielectric 1:
`
`Thick layer of glass.
`
`Metallization 1:
`
`Tungsten (damascene process) with titanium-nitride
`liner.
`
`Vias (M2 - M5):
`
`Tungsten (lined with titanium-nitride).
`
`Pre-metal glass:
`
`Thin layer of glass over a thick layer of silicon-
`dioxide and a thin nitride.
`
`Polycide:
`
`Titanium-silicide on polysilicon.
`
`Salicide on diffusions:
`
`Titanium-silicide.
`
`- 10 -
`
`12
`
`

`

` HORIZONTAL DIMENSIONS
`
`Die size:
`
`5.8 x 7.7 mm (229 x 302 mils)
`
`Die area:
`Min pad size:
`Min pad window:
`Min metal 6 width:
`Min metal 6 space:
`Min metal 5 width:
`Min metal 5 space:
`Min metal 4 width:
`Min metal 4 space:
`Min metal 3 width:
`Min metal 3 space:
`Min metal 2 width:
`Min metal 2 space:
`Min metal 1 width:
`Min metal 1 space:
`Min via (M6-to-M5):
`Min via (M5-to-M4):
`Min via (M4-to-M3):
`Min via (M3-to-M2):
`Min via (M2-to-M1):
`Min contact:
`Min polycide width:
`Min polycide space:
`Min gate length* - (N-channel):
` - (P-channel):
`
`SRAM cell size:
`SRAM cell pitch:
`
`*Physical gate length
`
`44.6 mm2 (69,158 mils2)
`0.08 mm (3 mils) octagon
`0.06 mm (2.5 mils) diameter
`1.6 micron
`1.9 micron
`0.65 micron
`0.5 micron
`0.65 micron
`0.5 micron
`0.65 micron
`0.5 micron
`0.45 micron
`0.5 micron
`0.45 micron
`0.4 micron
`1 micron
`0.7 micron
`0.7 micron
`0.7 micron
`0.45 micron
`0.45 micron
`0.2 micron
`0.5 micron
`
`0.2 micron
`0.2 micron
`
`17.8 microns2
`3.5 x 5.1 microns
`
`- 11 -
`
`13
`
`

`

`
`
`VERTICAL DIMENSIONS
`
`0.7 mm (28 mils)
`
`Die thickness:
`
`
`
`Layers:
`
`Passivation 2:
`Passivation 1 :
`Metal 6:
`Interlevel dielectric 5 - glass 2:
` - glass 1
`
`Metal 5 - cap:
`- aluminum:
`- barrier:
`- plugs:
`Interlevel dielectric 4 - glass 4:
` - glass 3:
` - glass 2:
` - glass 1:
`
`Metal 4 - cap:
`- aluminum:
`- barrier:
`- plugs:
`Interlevel dielectric 3 - glass 4:
` - glass 3:
` - glass 2:
` - glass 1:
`
`Metal 3 - cap:
`- aluminum:
`- barrier:
`- plugs:
`Interlevel dielectric 2 - glass 4:
` - glass 3:
` - glass 2:
` - glass 1:
`
`Metal 2 - cap:
`- aluminum:
`- barrier:
`- plugs:
`Interlevel dielectric 1:
`Metal 1:
`Nitride layer:
`Pre-metal glass - glass 2:
` - glass 1:
`Polycide - silicide:
`- poly:
`Trench oxide:
`N+ S/D:
`P+ S/D:
`P-well:
`N-epi:
`
`0.7 micron
`0.35 micron
`1.8 microns
`0.35 micron
`0.7 micron (average)
`0.1 micron
`0.6 micron
`0.03 micron (approximate)
`1.3 micron
`0.35 micron
`0.5 micron
`0.35 micron (average)
`0.07 micron (approximate)
`0.1 micron
`0.55 micron
`0.03 micron (approximate)
`0.9 micron
`0.3 micron
`0.25 micron
`0.35 micron (average)
`0.07 micron (approximate)
`0.1 micron
`0.6 micron
`0.03 micron (approximate)
`1.2 micron
`0.35 micron
`0.45 micron
`0.35 micron (average)
`0.07 micron (approximate)
`0.1 micron
`0.55 micron
`0.03 micron
`0.8 micron
`0.8 micron
`0.8 - 0.95 micron
`0.05 micron
`0.15 micron
`0.55 - 0.8 micron
`0.03 micron (approximate)
`0.15 micron
`0.6 micron
`0.2 micron
`0.15 micron
`0.8 micron (approximate)
`1.8 micron
`
`
`
`- 12 -
`
`14
`
`

`

` INDEX TO FIGURES
`
`ASSEMBLY
`
`Figure 1
`
`DIE LAYOUT AND IDENTIFICATION
`
`Figures 2 - 6
`
`PHYSICAL DIE STRUCTURES
`
`Figures 7 - 46
`
`COLOR DRAWING OF DIE STRUCTURE
`
`Figure 43
`
`MEMORY CELL
`
`Figures 44 - 46
`
`- ii -
`
`15
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Figure 1. Package photographs and x-ray view of the Motorola PC603R
`Microprocessor. Mag. 2.8x.
`
`16
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`ARTIFACTS
`
`Figure 2. Whole die photograph of the Motorola PC603R Microprocessor. Mag. 28x.
`
`17
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Figure 3. Die markings from the surface. Mag. 320x.
`
`18
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Figure 4. Optical views of the die corners. Mag. 100x.
`
`19
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`METALS 1-6
`
`CUTOUT
`
`14243
`
`SUBSTRATE
`
`Mag. 2700x
`
`METAL 6
`
`PASSIVATION 2
`
`METAL 5
`
`METAL 4
`
`METAL 3
`
`METAL 2
`
`METAL 1
`
`Mag. 6750x
`
`Figure 5. SEM section views of the edge seal structure.
`
`20
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Mag. 200x
`
`ISOLATED VIAS
`
`Mag. 800x
`
`Figure 6. Optical views of layout features.
`
`21
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Figure 7. SEM section views of general device structure.
`
`N+
`
`Mag. 9000x
`
`TRENCH OXIDE
`
`Mag. 7000x
`
`TRENCH OXIDE
`
`METAL1
`
`M2 PLUG
`
`M3 PLUG
`
`METAL3
`
`M4 PLUG
`
`METAL4
`
`M5 PLUG
`
`METAL5
`
`METAL1
`
`METAL2
`
`METAL2
`
`METAL3
`
`Mag. 6750x
`
`METAL5
`
`N+ S/D
`
`METAL4
`
`METAL6
`
`PASSIVATION 2
`
`M2 PLUG
`
`METAL1
`
`M3 PLUG
`
`METAL3
`
`M4 PLUG
`
`METAL2
`
`METAL4
`
`POLYGATES
`
`M5 PLUG
`
`METAL5
`
`PASSIVATION 1
`
`METAL6
`
`PASSIVATION 2
`
`22
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`PASSIVATION 2
`
`PASSIVATION 1
`
`METAL 6
`
`ILD 5
`
`METAL 5
`
`M5 PLUG
`
`METAL 4
`
`ILD 3
`
`METAL 3
`
`ILD 2
`
`ILD 4
`
`M3 PLUG
`
`METAL 2
`
`METAL 1
`
`M2 PLUG
`
`ILD 1
`
`PRE-METAL
`GLASS
`
`POLY GATE
`
`N+ S/D
`
`TRENCH OXIDE
`
`Figure 7a. Detailed SEM section view of general device structure. Mag. 14,300x.
`
`23
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`PASSIVATION 2
`
`METAL 6
`
`PASSIVATION 1
`
`METAL 3
`
`Mag. 6500x
`
`METAL 2
`
`POLY GATES
`
`METAL 1
`
`TRENCH OXIDE
`
`METAL 3
`
`M3 PLUG
`
`METAL 2
`
`M2 PLUG
`
`ILD 2
`
`METAL 1
`
`ILD 1
`
`Mag. 13,000x
`
`POLY GATES
`
`TRENCH OXIDE
`
`METAL 3
`
`M3 PLUG
`
`ILD 2
`
`METAL 2
`
`M2 PLUG
`
`METAL 1
`
`Mag. 13,000x
`
`ILD 1
`
`POLY GATES
`
`Figure 8. Glass etch section views illustrating general structure.
`
`24
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`PASSIVATION 2
`
`METAL 6
`
`Mag. 8000x
`
`ILD 5
`
`METAL 5
`
`ILD 4
`
`METAL 4
`
`PASSIVATION 2
`
`PASSIVATION 1
`
`METAL 6
`
`ILD 5
`
`Mag. 16,000x
`
`Figure 9. SEM section views of metal 6 line profiles.
`
`VIA (M6-M5)
`
`METAL 6
`
`Figure 10. Topological SEM view of metal 6 patterning. Mag. 3000x, 0°.
`
`25
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Mag. 2500x
`
`METAL 6
`
`Mag. 12,400x
`
`METAL 6
`
`METAL 5
`
`METAL 5
`
`Mag. 12,000x
`
`Figure 11. SEM views of general metal 6 integrity. 55°.
`
`26
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`PASSIVATION 2
`
`METAL 6
`
`ILD 5
`
`METAL 5
`
`ILD 4
`
`METAL 4
`
`M5 PLUG
`
`Mag. 8000x
`
`M4 PLUG
`
`METAL 3
`
`PASSIVATION 2
`
`METAL 6
`
`VOID
`
`Mag. 17,600x
`
`75% THINNING
`
`METAL 5
`
`ILD 5
`
`PASSIVATION 1
`
`VOID
`
`METAL 6
`
`Mag. 17,600x
`
`METAL 5
`
`Figure 12. SEM section views of metal 6-to-metal 5 vias.
`
`27
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`ILD 5
`
`DELINEATION
`ARTIFACTS
`
`ILD 4
`
`METAL 5
`
`Mag. 17,600x
`
`METAL 4
`
`ILD 5
`
`CAP
`
`ALUMINUM 5
`
`BARRIER
`
`Mag. 52,000x
`
`Figure 13. SEM section views of metal 5 line profiles.
`
`VIA (M5-M4)
`
`METAL 5
`
`Figure 14. Topological SEM view of metal 5 patterning. Mag. 10,000x, 0°.
`
`28
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Mag. 9000x
`
`METAL 5
`
`CAP
`
`PLUG
`
`Mag. 35,000x
`
`Figure 15. SEM views of general metal 5 integrity. 55°.
`
`29
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Mag. 13,500x
`
`Mag. 22,000x
`
`Mag. 30,000x
`
`M5 PLUGS
`
`METAL 4
`
`M5 PLUG
`
`METAL 4
`
`M4 PLUG
`
`METAL 3
`
`M5 PLUG
`
`CAP
`
`ALUMINUM 4
`
`BARRIER
`
`Figure 16. SEM views of metal 5 tungsten plugs. 55°.
`
`30
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`METAL 6
`
`METAL 5
`
`M5 PLUG
`
`METAL 4
`
`M4 PLUG
`METAL 3
`
`M3 PLUG
`
`METAL 2
`
`METAL 1
`
`Mag. 6500x
`
`METAL 5
`
`ILD 4
`
`M5 PLUG
`
`Mag. 26,000x
`
`METAL 4
`
`CAP
`
`ALUMINUM 5
`
`BARRIER
`
`ILD 4
`
`M5 PLUG
`
`Mag. 26,000x
`
`METAL 4
`
`Figure 17. SEM section views of metal 5-to-metal 4 vias.
`
`31
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`METAL 5
`
`M5
`PLUG
`
`ILD 4
`
`METAL 4
`
`Mag. 20,000x
`
`DELINEATION
`ARTIFACT
`
`CAP
`
`ALUMINUM 4
`
`BARRIER
`
`Mag. 52,000x
`
`Figure 18. SEM section views of metal 4 line profiles.
`
`32
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Mag. 8000x
`
`VIA (M4-M3)
`
`Mag. 8000x
`
`METAL 4
`
`METAL 3
`
`M4 PLUG
`
`METAL 4
`
`Mag. 25,000x
`
`MISALIGNMENT
`
`Figure 19. Topological SEM views of metal 4 patterning. 0°.
`
`33
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`M5 PLUG
`
`METAL 4
`
`Mag. 11,000x
`
`Mag. 25,000x
`
`M4 PLUG
`
`M5 PLUG
`
`METAL 4
`
`M4 PLUG
`
`METAL 3
`
`CAP
`
`ALUMINUM 4
`
`Mag. 30,000x
`
`M4 PLUG
`
`METAL 3
`
`Figure 20. SEM views of general metal 4 integrity. 55°.
`
`34
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`M4 PLUG
`
`Mag. 30,000x
`
`METAL 3
`
`M4 PLUG
`
`Mag. 32,000x
`
`METAL 3
`
`“SPILLOVER”
`
`M4 PLUG
`
`Mag. 35,000x
`
`CAP
`
`ALUMINUM 3
`
`Figure 21. SEM views of metal 4 tungsten plugs. 55°.
`
`35
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`ILD 4
`
`M5
`PLUG
`
`ILD 3
`
`METAL 5
`
`METAL 4
`
`M4 PLUG
`
`METAL 3
`
`Mag. 13,000x
`
`M4
`PLUG
`
`“SPILLOVER”
`
`ILD 3
`
`METAL 4
`
`METAL 3
`
`Mag. 16,000x
`
`ILD 2
`
`M3
`PLUG
`
`METAL 2
`
`METAL 4
`
`ILD 3
`
`M4
`PLUG
`
`Mag. 26,000x
`
`METAL 3
`
`Figure 22. SEM section views of metal 4-to-metal 3 vias.
`
`36
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`METAL 4
`
`ILD 3
`
`METAL 3
`
`M4
`PLUG
`
`Mag. 17,600x
`
`DELINEATION
`ARTIFACT
`
`CAP
`
`ALUMINUM 3
`
`Mag. 52,000x
`
`BARRIER
`
`Figure 23. SEM section views of metal 3 line profiles.
`
`VIA (M3-M2)
`
`METAL 3
`
`Figure 24. Topological SEM view of metal 3 patterning. Mag. 8000x, 0°.
`
`37
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`METAL 3
`
`M4
`PLUG
`
`Mag. 13,000x
`
`M4
`PLUG
`
`CAP
`
`ALUMINUM 3
`
`M3
`PLUG
`
`BARRIER
`
`Mag. 30,000x
`
`Figure 25. SEM views of general metal 3 integrity. 55°.
`
`38
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`M3
`PLUG
`
`METAL 2
`
`Mag. 30,000x
`
`M3
`PLUG
`
`CAP
`
`ALUMINUM 2
`
`Mag. 35,000x
`
`Figure 26. SEM views of metal 3 tungsten plugs. 55°.
`
`39
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`METAL 5
`
`METAL 4
`
`METAL 3
`
`Mag. 9000x
`
`METAL 2
`
`METAL 1
`
`N+
`
`METAL 3
`
`ILD 2
`
`M3 PLUG
`
`Mag. 26,000x
`
`METAL 2
`
`METAL 3
`
`ILD 2
`
`M3 PLUG
`
`Mag. 26,000x
`
`METAL 2
`
`Figure 27. SEM section views of metal 3-to-metal 2 vias.
`
`40
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`METAL 3
`
`ILD 2
`
`M3
`PLUG
`
`METAL 2
`
`ILD 1
`
`METAL 1
`
`Mag. 20,000x
`
`DELINEATION
`ARTIFACT
`
`CAP
`
`ALUMINUM 2
`
`BARRIER
`
`Mag. 52,000x
`
`Figure 28. SEM section views of metal 2 line profiles.
`
`41
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`VIA (M2-M1)
`
`METAL 2
`
`Mag. 9000x
`
`Mag. 8000x
`
`MISALIGNMENT
`
`M2 PLUG
`
`METAL 2
`
`Mag. 32,000x
`
`Figure 29. Topological views of metal 2 patterning. 0°.
`
`42
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`METAL 2
`
`Mag. 11,000x
`
`CAP
`
`BARRIER 2
`
`M2
`PLUG
`
`Mag. 31,000x
`
`Figure 30. SEM views of general metal 2 integrity. 55°.
`
`43
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`M2
`PLUG
`
`Mag. 30,000x
`
`METAL 1
`
`“SPILLOVER”
`
`M2
`PLUG
`
`METAL 1
`
`Mag. 35,000x
`
`M2
`PLUG
`
`Mag. 45,000x
`
`METAL 1
`
`“SPILLOVER”
`
`Figure 31. SEM views of metal 2 tungsten plugs. 55°.
`
`44
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Figure 32. SEM section views of metal 2-to-metal 1 vias.
`
`Mag. 40,000x
`
`Mag. 20,000x
`
`PLUG
`
`M2
`
`ILD 1
`
`MISALIGNMENT
`
`METAL2
`
`Mag. 26,000x
`
`P+
`
`METAL1
`
`PLUG
`
`M2
`
`METAL2
`
`ILD 1
`
`Mag. 20,000x
`
`P+
`
`POLY
`
`METAL1
`
`DIELECTRIC
`PRE-METAL
`
`METAL1
`
`PLUG
`
`M2
`
`ILD 1
`
`ILD 1
`
`PLUG
`
`M2
`
`METAL2
`
`METAL2
`
`45
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Mag. 8000x
`
`Mag. 9000x
`
`M2 PLUGS
`
`METAL 1
`
`M2 BARRIER
`
`METAL 1
`
`VOID
`
`Mag. 35,000x
`
`Figure 33. Topological SEM views of metal 1 patterning. 0°.
`
`46
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Mag. 8000x
`
`METAL 1
`
`Mag. 20,000x
`
`M2 PLUG
`
`POLY
`
`METAL 1
`
`Mag. 48,000x
`
`Figure 34. SEM views of general metal 1 integrity. 55°.
`
`47
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Figure 35. SEM section views of metal 1 contacts.
`
`Mag. 40,000x
`
`P+ S/D
`
`Mag. 35,000x
`
`N+ S/D
`
`POLYGATE
`
`METAL1
`
`METAL1
`
`POLYGATE
`
`VOID
`
`Mag. 35,000x
`
`Mag. 40,000x
`
`OXIDE
`TRENCH
`
`N+
`
`METAL1
`
`POLY
`
`VOID
`
`P+
`
`POLY
`
`OXIDE
`TRENCH
`
`DIELECTRIC
`PRE-METAL
`
`METAL1
`
`48
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Mag. 4800x
`
`POLY GATE
`
`DIFFUSION
`
`TRENCH OXIDE
`
`Mag. 6500x
`
`POLY GATE
`
`DIFFUSION
`
`NITRIDE
`
`POLY
`
`Mag. 13,000x
`
`Figure 36. Topological SEM views of poly patterning. 0°.
`
`49
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`NITRIDE
`
`Mag. 13,000x
`
`POLY GATE
`
`POLY GATE
`
`DIFFUSION
`
`Mag. 31,000x
`
`Figure 37. SEM views of general poly coverage. 55°.
`
`50
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`METAL 1
`
`POLY GATE
`
`N+ S/D
`
`Mag. 52,000x
`
`PRE-METAL
`DIELECTRIC
`
`METAL 1
`
`POLY
`
`N+ S/D
`
`GATE OXIDE
`
`Mag. 65,000x
`
`Figure 38. SEM section views of N-channel transistors.
`
`51
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`METAL 1
`
`VOID
`
`POLY
`
`P+ S/D
`
`Mag. 52,000x
`
`NITRIDE
`
`NITRIDE SIDEWALL
`SPACER
`
`SILICIDE
`
`SILICIDE
`
`glass etch, Mag. 70,000x
`
`Figure 39. SEM section views of P-channel transistors.
`
`52
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`VOID
`
`METAL 1
`
`P+ S/D
`
`TRENCH
`OXIDE
`
`Mag. 40,000x
`
`POLY
`
`GATE OXIDE
`
`METAL 1
`
`TRENCH
`OXIDE
`
`Mag. 52,000x
`
`Figure 40. SEM section views of trench oxide structures.
`
`53
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`STEP
`
`TRENCH OXIDE
`
`Mag. 45,000x
`
`N-WELL
`
`P-EPI
`
`P SUBSTRATE
`
`Mag. 1600x
`
`Figure 41. Section views illustrating the well structure.
`
`54
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Mag. 9000x, 0°
`
`COLLECTOR
`DIFFUSION
`
`TRENCH OXIDE
`
`EMITTER
`
`BASE
`
`Mag. 10,000x, 55°
`
`Figure 42. SEM views of a bipolar device.
`
`55
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`
`
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`
`
`Figure 43. Color cross section drawing illustrating device structure.
`
`Red = Diffusion, and Gray = Substrate
`
`Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly,
`
`P SUBSTRATE
`
`Ti SILICIDE
`
`P+ S/D
`
`P-EPI
`
`POLYCIDE
`
`N+ S/D
`
`N-WELL
`
`TRENCH OXIDE
`
`P-WELL
`
`PRE-METAL DIELECTRIC
`
`METAL 2
`
`METAL 4
`
`METAL 5
`
`METAL 6
`
`METAL 3
`
`ILD1
`
`ILD2
`
`ILD3
`
`ILD4
`
`M4 PLUG
`
`NITRIDE
`
`M5 PLUG
`
`METAL 1
`
`M2 PLUG
`
`M3 PLUG
`
`ILD5
`
`PASSIVATION
`
`56
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Figure 44. Topological SEM views of the Cache array. Mag. 9000x, 0°.
`
`poly
`
`metal 1
`
`N-WELL
`
`P-WELL
`
`N-WELL
`
`WORD LINES
`
`metal 2
`
`CONTACTS
`CONTACTS
`
`BIT LINE
`BIT LINE
`
`WORD LINES
`“PIGGYBACK”
`
`GND
`
`VCC
`
`CONTACTS
`
`BIT LINE
`
`VCC
`
`GND
`
`metal 3
`
`BIT LINE
`
`BIT LINE
`
`57
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`Figure 45. Perspective SEM views of the Cache array. Mag. 8000x, 55°.
`
`poly
`
`metal 1
`
`WORD LINES
`
`metal 2
`
`metal 3
`
`BIT CONTACTS
`BIT CONTACTS
`
`BIT LINES
`
`WORD LINES
`“PIGGYBACK”
`
`VCC
`
`GND
`
`58
`
`

`

`Motorola PC603R
`
`Integrated Circuit Engineering Corporation
`
`“PIGGYBACK”
`WORD LINE
`
`GND
`
`VCC
`
`metal 2
`
`poly
`
`BIT
`
`BIT
`
`GND
`
`VCC
`
`BIT
`
`1
`
`BIT
`
`2
`
`3
`
`4
`
`5
`
`6
`
`GND
`
`VCC
`
`WORD
`
`BIT
`
`1
`
`6
`
`4
`
`5
`
`3
`
`2
`
`BIT
`
`Figure 46. Topological SEM views of a Cache cell with schematic. Mag. 15,000x, 0°.
`
`59
`
`