throbber
Construction Analysis
`
`Intel Pentium Processor
`W/MMX
`
`Report Number: SCA 9706-540
`
`e m i c o nductorIn
`
`dustr y
`
`®
`
`S
`
`i n c e 1964
`
`bal S
`
`rvingtheGlo
`
`e
`
`S
`
`15022 N. 75th Street
`Scottsdale, AZ 85260-2476
`Phone: 602-998-9780
`Fax: 602-948-1925
`e-mail: ice@primenet.com
`Internet: http://www.ice-corp.com/ice
`
`IPR2015-01087 - Ex. 1030
`Micron Technology, Inc., et al., Petitioners
`1
`
`

`

` INDEX TO TEXT
`
` TITLE
`
`INTRODUCTION
`MAJOR FINDINGS
`
`TECHNOLOGY DESCRIPTION
`Assembly
`Die Process
`
`ANALYSIS RESULTS I
`Assembly
`
`ANALYSIS RESULTS II
`Die Process and Design
`
`ANALYSIS PROCEDURE
`
`TABLES
`Overall Evaluation
`Package Markings
`Die Material Analysis
`Horizontal Dimensions
`Vertical Dimensions
`
` PAGE
`
`1
`1
`
`2
`2 - 3
`
`4
`
`5 - 7
`
`8
`
` 9
` 10
` 10
`11
`12
`
`- i -
`
`2
`
`

`

` INTRODUCTION
`
`This report describes a construction analysis of the Intel 200MHz Pentium Processor with
`MMX technology. One sample was used for the analysis. The device was received in a
`296-pin, SPGA (Super PGA) with a metal heatsink.
`
` MAJOR FINDINGS
`
`Questionable Items:1
`
`• Quality of die manufacturing was good and we found no areas of quality or
`reliability concerns.
`
`Special Features:
`
`• Four metal, N-epi, CMOS process (not BiCMOS).
`
`• All metal layers employed tungsten via/contact plugs. Metals 2 - 4 employed tungsten
`plugs with "stubs" underneath at vias, for improved contact. Stacked vias were employed at
`all levels.
`
`• Chemical-mechanical planarization (CMP).
`
`• Oxide-filled shallow-trench isolation.
`
`• Titanium salicided diffusion structures.
`
`• Aggressive feature sizes (0.3 micron gates).
`
`Noteworthy Items:
`
`• Layout of the Pentium with MMX differs from the previous Pentium designs (120,
`133, and 166 MHz). Physical construction of the processors was basically the same
`(i.e. - Four metals, tungsten plugs at all levels, CMP planarization, 0.3 micron gate
`lengths). The most significant process difference appears to be no bipolar structures
`were used on the MMX device, but were present on the previously mentioned
`Pentium devices.
`
`- 1 -
`
`3
`
`

`

`1These items present possible quality or reliability concerns. They should be discussed
`with the manufacturer to determine their possible impact on the intended application.
` TECHNOLOGY DESCRIPTION
`
` Assembly:
`
`• The device was packaged in a 296-pin SPGA. A metal heatsink was employed on
`the top of the package. The die was mounted cavity down.
`
`• Eight decoupling capacitors were present on top of the package.
`
`• The PGA was constructed of fiberglass and was coated with a black epoxy-like
`material. The cavity was filled with black plastic material. Markings were etched
`into the plastic.
`
`• Triple tier package lands plated with gold.
`
`• Ultrasonic wedge wirebonding using gold wire.
`
`• Sawn dicing (full depth). The edges of the die had been beveled at the surface.
`
`• Silver-epoxy die attach. The backside of the die was plated with gold.
`
` Die Process:
`
`• Fabrication process: Oxide-filled shallow-trench isolation, CMOS process
`apparently employing twin wells in a N-epi on an N substrate.
`
`• Die coat: A thin patterned polyimide die coat was present over the entire die.
`
`• Final passivation: A single layer of nitride.
`
`• Metallization: Four levels of metal defined by dry-etch techniques. All consisted of
`aluminum with titanium-nitride caps. Metal 4 also employed a substantial titanium
`adhesion layer. There appeared to be evidence of very thin titanium adhesion layers
`under metals 1-3. Tungsten plugs were employed for vias and contacts under all
`metals. Metals 2 through 4 employed tungsten plugs with "stubs" underneath, for
`improved contact. The "stubs" penetrated into the metal
`
`- 2 -
`
`4
`
`

`

` TECHNOLOGY DESCRIPTION (continued)
`
`below the tungsten plugs. This is a unique processing feature. All plugs were lined
`with titanium-nitride. Stacked vias were employed at all levels.
`
`•
`
`Interlevel dielectrics 1, 2, and 3: The interlevel dielectric between all metals
`consisted of the same structure. A very thin glass was deposited first, followed by
`two thick layers of glass. The third layer of glass was planarized by CMP which left
`the surface very planar.
`
`• Pre-metal glass: A thick layer of glass followed by a thin layer of glass. This
`dielectric was also planarized by CMP.
`
`• Polysilicon: A single layer of dry-etched polycide (poly and titanium-silicide). This
`layer was used to form all gates on the die. Nitride sidewall spacers were used to
`provide the LDD spacing.
`
`• Diffusions: Implanted N+ and P+ diffusions formed the sources/drains of
`transistors. Titanium was sintered into the diffusions (salicide process).
`
`•
`
`Isolation: Local oxide isolation consisted of oxide-filled shallow-trench isolation. It
`was very planar with the diffused silicon surfaces.
`
`• Wells: Twin-wells in an N-epi on an N substrate.
`
`• SRAM: Level 1 on-chip data and code cache memory cell arrays (16KB each) were
`employed. The memory cells used a 6T CMOS SRAM cell design. Metal 3
`formed the bit lines (via metal 1 and 2). Metal 2 distributed Vcc and formed
`“piggyback” word lines. Metal 1 distributed GND and was used as cell
`interconnect. Polycide formed the select and storage gates. Cell pitch was 4.6 x 4.2
`microns (19µm2).
`
`• No redundancy fuses were found.
`
`- 3 -
`
`5
`
`

`

` ANALYSIS RESULTS I
`
` Assembly:
`
` Figures 1 - 2
`
`Questionable Items:1 None.
`
`Special Features:
`
`• SPGA package
`
`General Items:
`
`• The device was packaged in a 296-pin SPGA. A metal heatsink was employed on
`top of the package. The die was mounted cavity down. The PGA was constructed
`of fiberglass and was coated with a black epoxy-like material. The cavity was filled-
`in with black plastic material.
`
`• Overall package quality: Good. No defects were found on the external or internal
`portions of the packages. External pins were straight and placement was good. No
`voids were noted in the plastic cavity fill.
`
`• Wirebonding: Ultrasonic wedge bond method using gold wire. A three tier package
`land structure was used. Wire spacing and placement was good. Bond pitch was very
`close (95 microns); however, no problems were noted.
`
`• Die attach: Silver-epoxy die attach of good quality. No voids were noted in the die
`attach. The backside of the die was plated with gold.
`
`• Die dicing: Die separation was by full depth sawing and showed normal quality
`workmanship. No large chips or cracks were present at the die edges. The edges of
`the die had been beveled (see Figure 6). This is highly unusual and we do not know
`why it is done (or how).
`
`1These items present possible quality or reliability concerns. They should be discussed
`with the manufacturer to determine their possible impact on the intended application.
`
`- 4 -
`
`6
`
`

`

` ANALYSIS RESULTS II
`
` Die Process and Design:
`
` Figures 3 - 44a
`
`Questionable Items:1 None.
`
`•
`
` No areas of concern were found in the area of die fabrication.
`
`Special Features:
`
`• Four metal, twin-well, N-epi, CMOS process.
`
`• All metal layers employed tungsten via/contact plugs. Metals 2 - 4 employed tungsten
`plugs with "stubs" underneath at vias, for improved contact. Stacked vias were employed at
`all levels.
`
`• Chemical-mechanical planarization (CMP).
`
`• Oxide filled shallow-trench isolation.
`
`• Titanium salicided diffusion structures.
`
`• Aggressive feature sizes (0.3 micron gates).
`
`General Items:
`
`• Fabrication process: Oxide-filled shallow-trench isolation, CMOS process apparently
`employing twin-wells in an N-epi on an N substrate. No problems were found in the
`process.
`
`• Design implementation: Die layout was clean and efficient. Alignment was good at
`all levels.
`
`• Design features: Slotted bus lines were employed to relieve stress. Anti-dishing
`patterns were employed for planarization purposes. Numerous unconnected metal 4
`vias which appear to be used for probing purposes were present.
`
`- 5 -
`
`7
`
`

`

` ANALYSIS RESULTS II (continued)
`
`• Surface defects: No toolmarks, masking defects, or contamination areas were found.
`
`• Die coat: A patterned polyimide die coat was present over the entire die surface.
`
`• Final passivation: A single layer of nitride. Coverage was good. Edge seal was also
`good as the passivation extended into the scribe lane to seal the metallization.
`
`• Metallization: Four levels of metallization. All consisted of aluminum with
`titanium-nitride caps. Metal 4 employed a fairly thick titanium adhesion layer. The
`other levels probably used a titanium layer too thin to detect. Tungsten plugs were
`employed with all metals. Holes were noted in the center of some tungsten plugs at
`metals 2-4. All plugs were lined with titanium-nitride underneath and the presumed
`titanium layer over top.
`
`• Metal patterning: All metal layers were defined by a dry etch of good quality. Metal
`lines were widened (where needed), where vias made contact to them from above.
`
`• Metal defects: None. No voiding, notching or cracking of the metal layers was
`found. No silicon nodules were found following removal of the metal layers.
`
`• Metal step coverage: No metal (aluminum) thinning was present at the connections
`to the tungsten via plugs. The absence of thinning is due to the good control of plug
`height and the planarization technique employed.
`
`• Vias and contacts: All via and contact cuts were defined by a dry and wet-etch of
`good quality. Again, alignment of the metals and plugs was very good. Metals 2 - 4
`employed tungsten "stubs" at the bottom of the tungsten plugs. These unique
`features consisted of stubs of tungsten plug metallization that penetrated into the
`underlying aluminum. It is assumed that this represents a method to obtain good
`contact. Vias and contacts were placed directly over one another (stacked vias). No
`problems were noted.
`
`•
`
`Interlevel dielectrics 1, 2, and 3: The interlevel dielectric between all metals
`consisted of the same oxide structure. A very thin glass was deposited first,
`
`- 6 -
`
`8
`
`

`

` ANALYSIS RESULTS II (continued)
`
`followed by two thick layers of glass. The third layer of glass was subjected
`to CMP which left the surface very planar. No problems were found with any of
`these layers.
`
`• Pre-metal glass (under metal 1): A thick layer of silicon-dioxide followed by a thin
`layer of glass. This layer also appeared to have been planarized by chemical-
`mechanical planarization. No problems were found.
`
`• Polysilicon: A single level of polycide (poly and titanium-silicide) was used. It
`formed all gates and word lines in the array. Definition was by a dry etch of good
`quality. Nitride sidewall spacers were used throughout and left in place. No
`problems were found.
`
`•
`
`Isolation: The device used oxide-filled shallow-trench isolation which was quite
`planar with the silicon surface. No problems were present.
`
`• Diffusions: Implanted N+ and P+ diffusions were used for sources and drains.
`Titanium was sintered into the diffusions (salicide process) to reduce series
`resistance. An LDD process was used employing nitride sidewall spacers. No
`problems were found.
`
`• Wells: Apparently twin-wells were used in a N-epi on a N substrate. Definition
`was normal.
`
`• Buried contacts: Not used.
`
`• SRAM: As mentioned, Level 1 on-chip data and code Cache memory cell arrays (16KB
`each) were employed on the device. The SRAM cell array used a 6T CMOS SRAM cell
`design. Metal 3 formed the bit lines (via metals 1 and 2). Metal 2 distributed Vcc and
`formed “piggyback” word lines. Metal 1 distributed GND and was used as cell
`interconnect. Polycide formed the word lines/select and storage gates. Cell pitch was 4.2
`x 4.6 microns (19µm2).
`
`• No redundancy fuses were noted.
`
`- 7 -
`
`9
`
`

`

` PROCEDURE
`
`The devices were subjected to the following analysis procedures:
`
`External inspection
`
`X-ray
`
`Die optical inspection
`
`Delayer to metal 4 and inspect
`
`Aluminum removal (metal 4) and inspect tungsten plugs
`
`Delayer to metal 3 and inspect
`
`Aluminum removal (metal 3) and inspect tungsten plugs
`
`Delayer to metal 2 and inspect
`
`Aluminum removal (metal 2) and inspect tungsten plugs
`
`Delayer to metal 1 and inspect
`
`Aluminum removal (metal 1) and inspect tungsten plugs
`
`Delayer to polycide/substrate and inspect
`Die sectioning (90° for SEM)*
`
`Measure horizontal dimensions
`
`Measure vertical dimensions
`
`Die material analysis
`
`*Delineation of cross-sections is by glass etch unless otherwise indicated.
`
`- 8 -
`
`10
`
`

`

` OVERALL QUALITY EVALUATION: Overall Rating: Good
`
` DETAIL OF EVALUATION
`
`Package integrity
`Package markings
`Die placement
`Wirebond placement
`Wirebond quality
`Dicing quality
`Die attach quality
`Die attach method
`Dicing method:
`Wirebond method
`
`Die surface integrity:
`Toolmarks (absence)
`Particles (absence)
`Contamination (absence)
`Process defects (absence)
`General workmanship
`Passivation integrity
`Metal definition
`Metal integrity
`Metal registration
`Contact coverage
`Via/contact registration
`Etch control (depth)
`
`G
`G
`G
`G (tight wirebond pitch)
`N
`N
`G
`Silver-epoxy
`Sawn
`Ultrasonic wedge bonds using
` gold wire.
`
`G
`G
`G
`N (incomplete fill of plugs)
`G
`G
`G
`G
`G
`G
`N
`N
`
`G = Good, P = Poor, N = Normal, NP = Normal/Poor
`
`- 9 -
`
`11
`
`

`

` PACKAGE MARKINGS (partial)
`
` TOP (heatsink) BOTTOM (plastic)
`
` Intel
` Pentium
` w/MMX™ Tech
`
` Intel(cid:226)
` Pentium(cid:226)
` w/MMX™ Tech
` Q019 ES/2.8V
` m (cid:211)
` ‘92 ‘95
`
` DIE MATERIALS
`
`Overlay passivation:
`
`Single layer of nitride.
`
`Metallization 4:
`
`Aluminum with a titanium-nitride cap and a
`titanium adhesion layer.
`
`Interlevel dielectrics 1, 2, and 3:
`
`A thin layer of glass followed by two thick layers
`of glass.
`
`Metallization 1 - 3:
`
`Aluminum with a titanium-nitride cap and probably a
`very thin titanium adhesion layer.
`
`Via/contact plugs (M1 - M4):
`
`Tungsten (lined with titanium-nitride).
`
`Intermediate glass:
`
`Thick layer of silicon-dioxide followed by a
`thin glass. (No reflow glass).
`
`Polycide:
`
`Titanium-silicide on polysilicon.
`
`Salicide on diffusions:
`
`Titanium-silicide.
`
`- 10 -
`
`12
`
`

`

` HORIZONTAL DIMENSIONS
`
`Die size:
`
`10.9 x 12.7 mm (430 x 502 mils)
`
`Die area:
`Min pad size:
`Min pad window:
`Min pad space:
`Min metal 4 width:
`Min metal 4 space:
`Min metal 3 width:
`Min metal 3 space:
`Min metal 2 width:
`Min metal 2 space:
`Min metal 1 width:
`Min metal 1 space:
`Min via (M4-to-M3):
`Min via (M3-to-M2):
`Min via (M2-to-M1):
`Min contact:
`Min diffusion space:
`Min polycide width:
`Min polycide space:
`Min gate length* - (N-channel):
` - (P-channel):
`Min gate-to-contact space:
`
`SRAM cell size:
`SRAM cell pitch:
`
`139 mm2 (215,860 mils2)
`0.09 x 0.17 mm (3.6 x 6.6 mils)
`0.07 x 0.14 mm (2.9 x 5.6 mils)
`4 microns
`1.5 microns
`1.3 microns
`0.8 micron
`0.45 micron
`0.65 micron
`0.75 micron
`0.5 micron
`0.4 micron
`0.6 micron
`0.55 micron
`0.5 micron
`0.55 micron
`0.5 micron
`0.3 micron
`0.5 micron
`
`0.3 micron
`0.3 micron
`0.3 micron
`
`19 microns2
`4.2 x 4.6 microns
`
`*Physical gate length.
`
`- 11 -
`
`13
`
`

`

` VERTICAL DIMENSIONS
`
`Die thickness:
`
`(0.5 mm) 20 mils
`
` Layers
`
`Passivation:
`Metal 4 - cap:
` - aluminum:
` - barrier:
` - plugs:
`Interlevel dielectric 3 - glass 3:
`- glass 2:
`- glass 1:
`
`Metal 3 - cap:
`- aluminum:
`- plugs:
`Interlevel dielectric 2 - glass 3:
` - glass 2:
` - glass 1:
`
`Metal 2 - cap:
` - aluminum:
` - plugs:
`Interlevel dielectric 1 - glass 3:
`- glass 2:
`- glass 1:
`
`Metal 1 - cap:
`- aluminum:
`- plugs:
`Pre-metal glass - glass 2:
` - glass 1:
`Polycide - silicide:
` - poly:
`Trench oxide:
`
`0.7 micron
`0.03 micron (approximate)
`1.6 micron
`0.1 micron
`0.9 micron (not including "stub")
`0.5 - 1.4 micron
`0.4 micron
`0.07 micron (approximate)
`0.05 micron (approximate)
`0.75 micron
`0.9 micron (not including "stub")
`0.55 - 1.5 micron
`0.3 micron
`0.07 micron (approximate)
`0.05 micron (approximate)
`0.8 micron
`0.9 micron (not including "stub")
`0.35 - 1.15 micron
`0.35 micron
`0.07 micron (approximate)
`0.05 micron (approximate)
`0.55 micron
`0.6 - 0.9 micron
`0.08 micron (approximate)
`0.45 - 0.8 micron
`0.07 micron (approximate)
`0.2 micron
`0.4 micron
`
`- 12 -
`
`14
`
`

`

`N+ S/D diffusion:
`P+ S/D diffusion:
`N-epi:
`
`0.2 micron
`0.25 micron
`1.6 microns
`
`- 13 -
`
`15
`
`

`

` INDEX TO FIGURES
`
`ASSEMBLY
`
`Figures 1 - 2
`
`DIE LAYOUT AND IDENTIFICATION
`
`Figures 3 - 4
`
`PHYSICAL DIE STRUCTURES
`
`Figures 5 - 44a
`
`COLOR DRAWING OF DIE STRUCTURE
`
`Figure 40
`
`MEMORY CELL
`
`Figures 41 - 44a
`
`- ii -
`
`16
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`Figure 1. Package photographs of the Intel Pentium with MMX. Mag. 1.5x.
`
`17
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`Figure 2. Topological x-ray view of the package. Mag. 2.5x.
`
`18
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`Figure 3. Whole die photograph of the Intel Pentium with MMX. Mag. 16x.
`
`19
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`Figure 4. Die identification markings. Mag. 200x.
`
`20
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`Figure 5. Optical views of the die corners. Mag. 100x
`
`21
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`DIE SURFACE
`
`BEVEL
`
`Mag. 1000x
`
`SUBSTRATE
`
`METAL 4
`
`BEVEL
`
`Mag. 1500x
`
`SUBSTRATE
`
`PASSIVATION
`
`METAL 4
`
`METAL 3
`
`METAL 2
`
`METAL 1
`
`N+
`
`M4 PLUG
`
`M3 PLUG
`
`M2 PLUG
`
`M1 PLUG
`
`Mag. 8000x
`
`Figure 6. SEM section views of the edge seal structure.
`
`22
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`WAFFLE PATTERN
`
`POLYCIDE GATES
`
`Mag. 4000x, 0°
`
`WAFFLE PATTERN
`
`Mag. 13,500x
`
`TRENCH OXIDE
`
`Ti SILICIDE
`
`PRE-METAL
`DIELECTRIC
`
`Mag. 27,000x
`
`TRENCH OXIDE
`
`Figure 7. Topological and section views illustrating planarizing pattern.
`
`23
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`Mag. 800x
`
`Mag. 7000x, 0°
`
`Mag. 10,000x, 55°
`
`Figure 8. Optical and SEM views illustrating non-connected vias.
`
`24
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`Figure 9. SEM section views illustrating general device structure.
`
`Mag. 9000x
`
`Mag. 8000x
`
`GATES
`
`POLYCIDE
`
`METAL2
`
`PRE-METALDIELECTRIC
`
`METAL1
`
`IMD 1
`
`IMD 2
`
`METAL3
`
`METAL1
`
`N+ S/D
`
`M2 PLUG
`
`METAL2
`
`TRENCH OXIDE
`
`M1 PLUG
`
`M2 PLUG
`
`M4 PLUGS
`
`METAL4
`
`PASSIVATION
`
`N+ S/D
`
`GATES
`
`POLYCIDE
`
`METAL4
`
`PASSIVATION
`
`Mag. 7400x
`
`METAL1
`
`METAL2
`
`METAL3
`
`METAL4
`
`PASSIVATION
`
`25
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`PASSIVATION
`
`METAL 4
`
`Mag. 10,000x
`
`IMD 3
`
`IMD 2
`
`METAL 3
`
`METAL 3
`
`METAL 2
`
`METAL 4
`
`IMD 3
`
`METAL 3
`
`PASSIVATION
`
`CAP 4
`
`ALUMINUM 4
`
`BARRIER
`
`Mag. 13,000x
`
`Mag. 26,000x
`
`Figure 10. SEM section views of metal 4 line profiles.
`
`26
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`Mag. 5000x, 0°
`
`Mag. 15,000x, 55°
`
`Figure 11. SEM views of metal 4 patterning and coverage.
`
`27
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`W PLUG
`
`CAP 3
`
`ALUMINUM 3
`
`Mag. 35,000x
`
`W PLUG
`
`METAL 3
`
`Mag. 40,000x
`
`Figure 12. SEM views of metal 4 tungsten plugs. 55°.
`
`28
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`M4 PLUG
`
`METAL 4
`
`METAL 3
`
`IMD 2
`
`IMD 1
`
`METAL 1
`
`M3 PLUG
`
`METAL 2
`
`M2 PLUG
`
`stacked vias, Mag. 11,000x
`
`METAL 4
`
`M4 PLUG
`
`METAL 3
`
`M3 PLUG
`
`IMD 2
`
`METAL 2
`
`Mag. 15,000x
`
`Figure 13. SEM section views of metal 4-to-metal 3 vias.
`
`29
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`ALUMINUM 4
`
`Mag. 20,000x
`
`BARRIER 4
`
`M4
`PLUG
`
`IMD 3
`
`METAL 3
`
`PASSIVATION
`
`METAL 4
`
`M4 PLUG
`
`METAL 3
`
`IMD 2
`
`METAL 4
`
`M4 PLUG
`
`Mag. 13,000x
`
`Mag. 35,000x
`
`“STUB”
`
`METAL 3
`
`Figure 14. Additional SEM section views of metal 4-to-metal 3 vias.
`
`30
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`PASSIVATION
`
`IMD 3
`
`METAL 3
`
`METAL 2
`
`Mag. 17,600x
`
`IMD 3
`
`CAP 3
`
`ALUMINUM 3
`
`Mag. 52,000x
`
`Figure 15. SEM section views of metal 3 line profiles.
`
`31
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`METAL 3
`
`VIAS
`
`Mag. 5000x
`
`VIA
`
`Mag. 6500x
`
`Figure 16. Topological SEM views of metal 3 patterning. 0°.
`
`32
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`VIA
`
`Mag. 8000x
`
`METAL 3
`
`ALUMINUM 3
`
`CAP 3
`
`Mag. 31,000x
`
`W PLUG
`
`METAL 2
`
`ALUMINUM 3
`
`CAP 3
`
`Mag. 31,000x
`
`W PLUG
`
`METAL 2
`
`Figure 17. SEM views of general metal 3 integrity. 55°.
`
`33
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`“HOLES”
`(INCOMPLETE FILL)
`
`Mag, 30,000x
`
`W PLUGS
`
`METAL 2
`
`W PLUG
`
`Mag. 35,000x
`
`CAP 2
`
`ALUMINUM 2
`
`W PLUG
`
`METAL 2
`
`Mag. 35,000x
`
`Figure 18. SEM views of metal 3 tungsten plugs. 55°.
`
`34
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`Stacked vias,
`Mag. 17,600x
`
`METAL 3
`
`M3
`PLUG
`
`METAL 2
`
`M2
`PLUG
`
`METAL 1
`
`M4
`PLUG
`
`M4
`PLUG
`
`METAL 3
`
`Mag. 20,000x
`
`“HOLE”
`
`IMD 2
`
`METAL 2
`
`METAL 3
`
`IMD 2
`
`IMD 1
`
`IMD 2
`
`IMD 3
`
`IMD 2
`
`M3 PLUG
`
`Mag. 26,000x
`
`METAL 2
`
`“STUB”
`
`Figure 19. SEM section views of metal 3-to-metal 2 vias.
`
`35
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`IMD 2
`
`METAL 2
`
`METAL 2
`
`DELINEATION
`ARTIFACT
`
`Mag. 26,000x
`
`IMD 2
`
`CAP 2
`
`ALUMINUM 2
`
`Mag. 52,000x
`
`Figure 20. SEM section views of metal 2 line profiles.
`
`36
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`VIAS (M3-M2)
`
`METAL 2
`
`Mag. 7000x
`
`VIA (M2-M1)
`
`VIA (M3-M2)
`
`METAL 2
`
`Mag. 9000x
`
`Figure 21. Topological SEM views of metal 2 patterning. 0°.
`
`37
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`M3 PLUG
`
`METAL 2
`
`Mag. 12,000x
`
`M3
`PLUG
`
`M2
`PLUG
`
`CAP 1
`
`M1
`PLUG
`
`POLYCIDE
`
`CAP 2
`
`ALUMINUM 2
`
`ALUMINUM 1
`
`stacked structure, Mag. 22,000x
`
`Figure 22. SEM views of general metal 2 coverage. 55°.
`
`38
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`METAL 2
`
`M3
`PLUG
`
`M2
`PLUG
`
`METAL 1
`
`M1
`PLUG
`
`POLYCIDE
`
`Mag. 23,000x
`
`METAL 2
`
`M2
`PLUG
`
`METAL 1
`
`Mag. 35,000x
`
`Figure 22a. SEM details of metal 2 coverage. 55°.
`
`39
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`W PLUGS
`
`Mag. 13,000x
`
`W PLUGS
`
`Mag. 33,600x
`
`METAL 1
`
`Mag. 40,000x
`
`W PLUG
`
`METAL 1
`
`Figure 23. SEM views of metal 2 tungsten plugs. 55°.
`
`40
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`M3 PLUG
`
`M2 PLUG
`
`M1 PLUG
`
`IMD 2
`
`IMD 1
`
`METAL 3
`
`METAL 2
`
`METAL 1
`
`N+
`
`METAL 3
`
`METAL 2
`
`METAL 1
`
`stacked vias,
`Mag. 13,500x
`
`M3 PLUG
`
`M2 PLUG
`
`Mag. 17,600x
`
`METAL 2
`
`METAL 2
`
`M2
`PLUG
`
`IMD 1
`
`Mag. 26,000x
`
`METAL 1
`
`“STUB”
`
`Figure 24. SEM section views of metal 2-to-metal 1 vias.
`
`41
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`IMD 1
`
`METAL 1
`
`METAL 1
`
`PRE-METAL DIELECTRIC
`
`POLYCIDE
`
`Mag. 35,000x
`
`CAP 1
`
`ALUMINUM 1
`
`IMD 1
`
`Mag. 52,000x
`
`Figure 25. SEM section views of metal 1 line profiles.
`
`42
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`VIAS (M2-M1)
`
`CONTACTS
`
`METAL 1
`
`CONTACT
`
`METAL 1
`
`VIAS (M2-M1)
`
`Figure 26. Topological SEM views of metal 1 patterning. Mag. 6500x, 0°.
`
`METAL 1
`
`43
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`M2 PLUGS
`
`Mag. 10,000x
`
`METAL 1
`
`Mag. 10,000x
`
`METAL 1
`
`M2 PLUG
`
`M1
`PLUG
`
`METAL 1
`
`Mag. 15,000x
`
`Figure 27. SEM views of general metal 1 coverage. 55°.
`
`44
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`M2
`PLUG
`
`METAL 2
`
`M1
`PLUG
`
`M1
`PLUG
`
`POLYCIDE
`
`Mag. 27,000x
`
`METAL 1
`
`M1
`PLUG
`
`POLYCIDE
`
`Mag. 35,000x
`
`Figure 28. SEM details of metal 1 coverage. 55°.
`
`45
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`W
`PLUG
`
`POLYCIDE
`
`POLYCIDE
`
`Mag. 30,000x
`
`W
`PLUG
`
`POLYCIDE
`
`Mag. 52,000x
`
`Figure 29. SEM views of metal 1 plugs. 55°.
`
`46
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`IMD 1
`
`Ti SILICIDE
`
`METAL 1
`
`INCOMPLETE
`COVERAGE
`
`metal-to-diffusion,
`Mag. 26,000x
`
`M1
`PLUG
`
`METAL 1
`
`M1
`PLUG
`
`TRENCH OXIDE
`
`Ti SILICIDE
`
`metal 1-to-diffusion,
`Mag. 30,000x
`
`Ti SILICIDE
`
`METAL 1
`
`TiN
`
`M1
`PLUG
`
`POLY
`
`Ti SILICIDE
`
`metal 1-to-polycide,
`Mag. 35,000x
`
`NITRIDE SIDEWALL
`SPACERS
`
`Figure 30. Glass etch section views of metal 1 contacts.
`
`47
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`METAL 2
`
`IMD 1
`
`Mag. 20,000x
`
`METAL 1
`
`POLYCIDE
`
`M1
`PLUG
`
`TRENCH OXIDE
`
`METAL 1
`
`METAL 1
`
`POLYCIDE
`
`M1
`PLUG
`
`Mag. 35,000x
`
`TRENCH OXIDE
`
`METAL 1
`
`POLYCIDE
`
`M1
`PLUG
`
`Mag. 35,000x
`
`TRENCH OXIDE
`
`Figure 31. SEM section views of metal 1-to-polycide contacts.
`
`48
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`METAL 2
`
`M2
`PLUG
`
`METAL 1
`
`M1
`PLUG
`
`N+
`
`N+
`
`IMD 1
`
`METAL 1
`
`M1
`PLUG
`
`M1
`PLUG
`
`N+
`
`Mag. 20,000x
`
`Mag. 26,000x
`
`METAL 1
`
`PRE-METAL
`DIELECTRIC
`
`Mag. 35,000x
`
`M1
`PLUG
`
`N+
`
`Figure 32. SEM section views of metal 1-to-N+ contacts.
`
`49
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`METAL 1
`
`M1
`PLUG
`
`Mag. 40,000x
`
`POLYCIDE
`GATE
`
`P+ S/D
`
`METAL 1
`
`PRE-METAL
`DIELECTRIC
`
`M1
`PLUG
`
`TRENCH OXIDE
`
`P+
`
`Mag. 30,000x
`
`Figure 33. SEM section views of metal 1-to-P+ contacts.
`
`50
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`POLYCIDE
`GATES
`
`Mag. 6000x
`
`POLYCIDE
`
`DIFFUSION
`
`Mag. 8000x
`
`POLYCIDE
`
`DIFFUSION
`
`GATE
`
`GATE
`
`Mag. 8000x
`
`Figure 34. Topological SEM views of polycide gates. 0°.
`
`51
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`POLYCIDE
`
`Mag. 8000x
`
`DIFFUSION
`
`POLYCIDE
`
`NITRIDE SPACER
`
`Mag. 15,000x
`
`POLYCIDE GATE
`
`Mag. 30,000x
`
`NITRIDE
`
`DIFFUSION
`
`Figure 35. Perspective SEM views of polycide coverage. 55°.
`
`52
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`PRE-METAL DIELECTRIC
`
`N+ S/D
`
`N+ S/D
`
`POLYCIDE GATES
`
`Mag. 26,000x
`
`POLYCIDE GATE
`
`NITRIDE SPACER
`
`N+ S/D
`
`GATE OXIDE
`
`Mag. 52,000x
`
`Figure 36. SEM section views of N-channel transistors.
`
`53
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`IMD 1
`
`POLYCIDE GATE
`
`METAL 1
`
`M1
`PLUG
`
`P+ S/D
`
`Mag. 26,000x
`
`POLYCIDE GATE
`
`M1
`PLUG
`
`NITRIDE SPACER
`
`Mag. 52,000x
`
`P+ S/D
`
`Mag. 52,000x
`
`Figure 37. SEM section views of P-channel transistors.
`
`54
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`METAL 1
`
`TRENCH OXIDE
`
`Mag. 30,000x
`
`POLYCIDE
`
`GATE OXIDE
`
`POLYCIDE
`
`Mag. 52,000x
`
`GATE OXIDE
`
`TRENCH OXIDE
`
`POLYCIDE
`
`Mag. 52,000x
`
`TRENCH OXIDE
`
`GATE OXIDE
`
`Figure 38. SEM section views of trench oxide isolation.
`
`55
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`
`(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)(cid:0)
`
`Figure 40. Color cross section drawing illustrating device structure.
`
`Red = Diffusion,and Gray = Substrate
`
`Orange = Nitride,Blue = Metal,Yellow = Oxide,Green = Poly,
`
`N SUBSTRATE
`
`
`
`
`P-WELL
`
`3
`
`PLUG
`
`METAL 3
`
`METAL 1
`
`2
`
`PLUG
`
`METAL 2
`
`PASSIVATION
`
`4
`
`PLUG
`
`METAL 4
`
`PRE-METAL GLASS
`
`INTERLEVEL DIELECTRIC 1
`
`INTERLEVEL DIELECTRIC 2
`
`INTERLEVEL DIELECTRIC 3
`
`N-EPI
`
`N+ S/D
`
`SILICIDE
`
`P+ S/D
`
`SILICIDE
`
`PLUG 1
`
`TRENCH OXIDE
`
`POLY
`
`N-WELL
`
`56
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`BIT LINE
`
`BIT LINE
`
`metal 3
`
`“PIGGYBACK” WORD LINES
`
`VCC
`
`BIT LINE
`CONTACTS
`
`Figure 41. Topological SEM views of the Cache SRAM array. Mag. 6500x, 0°.
`
`metal 2
`
`57
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`GND
`
`VCC
`
`BIT LINE CONTACTS
`
`metal 1
`
`WORD LINES
`
`N-WELL
`
`P-WELL
`
`Figure 41a. Topological SEM views of the Cache SRAM array. Mag. 6500x, 0°.
`
`unlayered
`
`58
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`BIT
`LINES
`
`metal 3
`
`VCC
`
`metal 2
`
`Figure 42. Perspective SEM views of the Cache SRAM array. Mag. 7000x, 55°.
`
`59
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`GND
`
`metal 1
`
`WORD LINES
`
`Figure 42a. Perspective SEM views of the Cache SRAM array. Mag. 7000x, 55°.
`
`unlayered
`
`60
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`BIT LINE
`CONTACTS
`
`VCC
`
`metal 2
`
`GND
`
`metal 1
`
`WORD LINES
`
`unlayered
`
`Figure 43. Perspective SEM details of the Cache SRAM array. Mag. 15,000x, 55°.
`
`61
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`metal 3
`
`BIT
`
`BIT
`
`BIT
`
`BIT
`
`Figure 44. Topological SEM views of a Cache SRAM cell. Mag. 13,000x, 0°.
`
`metal 2
`
`62
`
`

`

`Intel Pentium
`
`Integrated Circuit Engineering Corporation
`
`BIT
`
`GND
`
`BIT
`
`metal 1
`
`VCC
`
`WORD LINE
`
`BIT
`
`1
`
`P-WELL
`
`N-WELL
`
`3
`
`GND
`
`4
`
`5
`
`6
`
`VCC
`
`unlayered
`
`BIT
`
`2
`
`WORD
`
`BIT
`
`1
`
`6
`
`4
`
`5
`
`3
`
`2
`
`BIT
`
`Figure 44a. Topological SEM views of a Cache SRAM cell with schematic.
`Mag. 13,000x, 0°.
`
`63
`
`

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