throbber
Construction Analysis
`
`Lattice ispLSI2032-180L
`CPLD
`
`Report Number: SCA 9712-573
`
`e m i c o nductorIn
`
`dustr y
`
`®
`
`S
`
`i n c e 1964
`
`bal S
`
`rvingtheGlo
`
`e
`
`S
`
`17350 N. Hartford Drive
`Scottsdale, AZ 85255
`Phone: 602-515-9780
`Fax: 602-515-9781
`e-mail: ice@ice-corp.com
`Internet: http://www.ice-corp.com
`
`IPR2015-01087 - Ex. 1029
`Micron Technology, Inc., et al., Petitioners
`1
`
`

`
` INDEX TO TEXT
`
` TITLE
`
`INTRODUCTION
`MAJOR FINDINGS
`
`
`
` PAGE
`
`1
`1
`
`TECHNOLOGY DESCRIPTION
`Die Process and Design 2 - 3
`
`ANALYSIS RESULTS
`Die Process and Design
`
`ANALYSIS PROCEDURE
`
`TABLES
`Overall Evaluation
`Die Material Analysis
`Horizontal Dimensions
`Vertical Dimensions
`
`4 - 6
`
`7
`
`8
` 8
` 9
`10
`
`i
`
`2
`
`

`
` INTRODUCTION
`
`This report describes a construction analysis of the Lattice ispLSI 2032-180L Complex
`Programmable Logic Device (CPLD). One device packaged in a 44-pin Thin Quad-Flat-Pack
`(TQFP) was received for the analysis.
`
` MAJOR FINDINGS
`
`Questionable Items:1
`
`• Excessive metal 2 and metal 1 aluminum thinning.
`
`Special Features:
`
`• Three types of EEPROM cells were used.
`
`• Mature technology using thin tunnel-oxide windows.
`
`1These items present possible quality or reliability concerns. They should be discussed
` with the manufacturer to determine their possible impact on the intended application.
`
`- 1 -1
`
`3
`
`

`
` TECHNOLOGY DESCRIPTION
`
` Die Process and Design :
`
` Fabrication process: Selective oxidation CMOS process employing twin-wells in an N
`substrate. No epi was used.
`
` Final passivation: A layer of nitride over a layer of glass (no die coat was present).
`
` Metallization: Two levels of metal interconnect were used. Both metal 2 and metal 1
`consisted of aluminum with a thin titanium-nitride (TiN) cap and barrier. Standard vias
`and contacts were employed (no plugs).
`
` •
`
` •
`
` •
`
`Interlevel dielectric: Interlevel dielectric (between M2 and M1) consisted of two layers
`of glass, with a spin-on-glass (SOG) between to provide planarization.
`
`
`
` •
`
` Pre-metal dielectric: Consisted of a single layer of reflow glass (probably BPSG) over
`various densified oxides.
`
` Polysilicon: A single layer of dry-etched polycide (poly and tungsten silicide) was
`used. This layer formed all gates on the die, and in the cell array it formed the
`capacitors, word lines, and tunnel oxide device. Oxide sidewall spacers were used on
`all gates, and left in place.
`
` Diffusion: Standard implanted N+ and P+ diffusions formed the sources/drains of the
`MOS transistors.
`
` Wells: Twin-wells in an N substrate. A shallow N-well was located under the P-
`channel devices. N-channel devices were located within the P-wells. A step was noted
`in the local oxide at the edges of the well boundaries.
`
` •
`
` •
`
` •
`
` •
`
`
`
`- 2 -2
`
`4
`
`

`
` TECHNOLOGY DESCRIPTION (continued)
`
` •
`
` The memory cell consisted of a standard EEPROM design. Metal was used to form
`the bit lines. Poly was used to form the word/select lines, capacitors, and the tunnel
`oxide devices.
`
`- 3 -3
`
` •
`
` Redundancy fuses were not present.
`
`
`5
`
`

`
` ANALYSIS RESULTS
`
` Figures 1 - 43
`
` Die Process:
`
`Questionable Items:1
`
`• Excessive metal 2 and metal 1 aluminum thinning.
`
`Special Features:
`
`• Three types of EEPROM cells were used.
`
`• Mature technology using thin tunnel-oxide windows.
`
`General Items:
`
`• Fabrication process: Selective oxidation CMOS process employing twin-well in a N
`substrate (no epi was used). No problems were found in this process.
`
` Process implementation: Die layout was clean and efficient. Alignment was good at all
`levels. No damage or contamination was found.
`
` Die coat: No die coat was present.
`
` Final passivation: A layer of nitride over a layer of glass. An integrity test indicated
`defect-free passivation. Edge seal was good.
`
` Metallization: Both metal 2 and metal 1 consisted of aluminum with a thin titanium-
`nitride (TiN) cap and barrier defined by dry-etch techniques. Standard vias and contacts
`were used (no plugs).
`
` •
`
` •
`
` •
`
` •
`
`1These items present possible quality or reliability concerns. They should be discussed
` with the manufacturer to determine their possible impact on the intended application.
`
`- 4 -4
`
`6
`
`

`
` ANALYSIS RESULTS (continued)
`
` •
`
` Metal patterning: The metal layers were patterned by a dry etch of normal quality.
`Contacts were completely surrounded by metal and metal lines were widened at
`contacts.
`
` •
`
` Metal defects: No voiding, notching, or neckdown was noted in either metal layer.
`
`• Metal step coverage: Metal 2 aluminum thinned up to 100 percent at vias. It was
`reduced to 95 percent with the addition of the cap and barrier. Metal 1 aluminum
`thinned up to 100 percent at the contacts. This thinning was reduced to 95 percent with
`the addition of the cap and barrier. This thinning appears to be excessive and not under
`good control.
`
`Interlevel dielectric: Interlevel dielectric (between M2 and M1) consisted of two layers
`of glass with a spin-on-glass between for planarization. No problems were found with
`these layers.
`
`
`
` •
`
` Pre-metal dielectric: Consisted of a single layer of reflow glass (probably BPSG) over
`a densified oxide. The glass was reflowed before contact cuts only. No problems were
`found.
`
` Vias and contacts: Via and contact cuts appeared to be defined by a two-step dry etch.
`No over-etching or other contact problems were found.
`
` Polysilicon: A single layer of polycide (poly and tungsten silicide) was used to form
`all the gates on the die. In the cell, poly formed the word/select lines, capacitors, and
`the tunnel oxide device. Oxide sidewall spacers were used on all gates and left in place.
`
` Diffusions: Standard implanted N+ and P+ diffusions formed the sources/drains of
`the MOS transistors. Diffusions were not silicided. No problems were noted.
`
` •
`
` •
`
` •
`
` •
`
`- 5 -5
`
`7
`
`

`
` ANALYSIS RESULTS (continued)
`
`
`
`Isolation: Local oxide (LOCOS) isolation was used. A step was present in the oxide at
`the well boundaries.
`
` EEPROM arrays: Three types of EEPROM memory cells were used. Metal was
`used to form the bit lines. Poly formed the word/select lines, capacitors, and the tunnel
`oxide device. Smallest cell pitch was 8.95 x 13.5 microns.
`
` Redundancy fuses were not present on the die.
`
`- 6 -6
`
` •
`
` •
`
` •
`
`8
`
`

`
` PROCEDURE
`
`The devices were subjected to the following analysis procedures:
`
`Internal optical inspection
`
`SEM inspection of passivation
`
`Passivation integrity test
`
`Delayer to metal 2 and inspect
`
`Aluminum removal (metal 2)
`
`Delayer to metal 1 and inspect
`
`Delayer to poly/substrate and inspect
`Die sectioning (90(cid:176) for SEM)*
`
`Die material analysis
`
`Measure horizontal dimensions
`
`Measure vertical dimensions
`
`*Delineation of cross-sections is by silicon etch unless otherwise indicated.
`
`- 7 -7
`
`9
`
`

`
` OVERALL QUALITY EVALUATION: Overall Rating: Normal
`
` DETAIL OF EVALUATION
`
`Die surface integrity:
`
`Toolmarks (absence)
`Particles (absence)
`Contamination (absence)
`Process defects (absence)
`General workmanship
`Passivation integrity
`Metal definition
`Metal integrity
`Contact coverage
`Contact registration
`
`G
`G
`G
`G
`N
`G
`N
`NP (thinning)
`G
`G
`
`G = Good, P = Poor, N = Normal, NP = Normal/Poor
`
` DIE MATERIAL ANALYSIS
`
`Final passivation:
`
`Metallization 2:
`
`A layer of nitride over a layer of silicon-
`dioxide.
`
`Aluminum with a thin titanium-nitride (TiN) cap and
`barrier. An apparent titanium (Ti) adhesion layer
`under the barrier metal.
`
`Interlevel dielectric:
`
`Two layers of silicon-dioxide.
`
`Metallization 1:
`
`Aluminum with a thin titanium-nitride (TiN) cap and
`barrier. An apparent titanium (Ti) adhesion layer
`under the barrier metal.
`
`Pre-metal dielectric:
`
`A single layer of BPSG reflow glass over a densified oxide.
`
`Poly:
`
`Tungsten (W) silicide.
`
`- 8 -8
`
`10
`
`

`
`Die size:
`
`Die area:
`
`Min pad size:
`
`Min pad window:
`
`Min pad space:
`
`Min metal 2 width:
`
`Min metal 2 space:
`
` HORIZONTAL DIMENSIONS
`
`2.1 x 4.5 mm (84 x 175 mils)
`
`9.5 mm2 (14,700 mils2)
`
`0.1 x 0.1 mm (4.1 x 4.1 mils)
`
`0.08 x 0.08 mm (3.4 x 3.4 mils)
`
`0.05 mm (2.2 mils)
`
`1.1 micron
`
`1.3 micron
`
`Min metal 2 pitch - (uncontacted):
`
`2.2 microns
`
` - (contacted):
`
`2.6 microns
`
`Min via:
`
`Min metal 1 width:
`
`Min metal 1 space:
`
`1.0 micron
`
`0.8 micron
`
`1.0 micron
`
`Min metal 1 pitch - (uncontacted):
`
`1.85 microns
`
` - (contacted):
`
`2.3 microns
`
`Min contact:
`
`Min poly width - (cell):
`
`1.0 micron
`
`0.65 micron
`
`Min poly width - (periphery):
`
`0.5 micron
`
`Min poly space:
`
`0.9 micron
`
`Min gate length1 - (N-channel):
`
`0.5 micron
`
` - (P-channel):
`
`0.65 micron
`
`Cell area2 (smallest):
`
`120.8 microns2
`
`Cell size2 (smallest):
`
`8.95 x 13.5 microns
`
`1Physical gate length.
`2Cell shown in Figures 22 - 31.
`
`- 10 -10
`
`11
`
`

`
` VERTICAL DIMENSIONS
`
`Die thickness:
`
` Layers
`
`Passivation 2:
`
`Passivation 1:
`
`Metal 2 - cap:
`
` - aluminum:
`
` - barrier:
`
`Interlevel dielectric 1 - glass 2:
`
` - SOG:
`
` - glass 1:
`
`Metal 1 - cap:
`
`- aluminum:
`
`- barrier:
`
`Reflow glass:
`
`Poly - silicide:
`
` - poly:
`
`Local oxide:
`
`N+ S/D diffusion:
`
`P+ S/D diffusion:
`
`N-well:
`
`P-well:
`
`0.3 mm (13 mils)
`
`0.45 micron
`
`0.27 micron
`
`0.04 micron
`
`0.74 micron
`
`0.11 micron
`
`0.48 micron
`
`0 - 1.2 microns
`
`0.17 micron
`
`0.07 micron
`
`0.47 micron
`
`0.11 micron
`
`0.3 - 0.75 micron
`
`0.15 micron
`
`0.12 micron
`
`0.48 micron
`
`0.25 micron
`
`0.25 micron
`
`1.0 micron
`
`3.5 microns
`
`- 11 -11
`
`12
`
`

`
` INDEX TO FIGURES
`
`DIE LAYOUT AND IDENTIFICATION
`
`Figures 1 - 3
`
`PHYSICAL DIE STRUCTURES
`
`Figures 4 - 43
`
`COLOR DRAWING OF DIE STRUCTURE
`
`Figure 21
`
`MEMORY CELL STRUCTURES
`
`Figures 22 - 41
`
`ii
`
`13
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`PIN 1
`
`Figure 1. Whole die photograph of the Lattice ispLSI 2032-180L CPLD. Mag. 50x.
`
`14
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`Figure 2. Optical views of the die markings from the surface. Mag. 800x.
`
`15
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`METAL 2
`
`Photograph #8,
`Mag. 13,000x
`
`METAL 2
`
`METAL 1
`
`Photograph #9,
`Mag. 13,000x
`
`PASSIVATION 2
`
`PASSIVATION 1
`
`METAL 2
`
`INTERLEVEL DIELECTRIC
`
`Photograph #9,
`Mag. 26,000x
`
`Figure 3. SEM views illustrating design rules 9 and 10.
`
`16
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`METAL 2
`
`Photograph #10, type C,
`aluminum intact
`
`BARRIER
`
`Photograph #10, type C,
`aluminum removed
`
`Figure 4. SEM views illustrating design rule 11. Mag. 13,000x.
`
`17
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`SOG
`
`METAL 2
`
`METAL 1
`
`PRE-METAL DIELECTRIC
`
`Photograph #11
`
`PASSIVATION 2
`
`METAL 2
`
`METAL 1
`
`PRE-METAL DIELECTRIC
`
`Figure 5. SEM views illustrating design rules 12, 13, and 14. Mag. 13,000x.
`
`Photograph #12
`
`18
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`METAL 2
`
`Photograph #13,
`aluminum intact,
`Mag. 13,000x
`
`BARRIER
`
`Photograph #13,
`aluminum removed,
`Mag. 13,000x
`
`METAL 2
`
`INTERLEVEL
`DIELECTRIC
`
`Photograph #14,
`Mag. 15,000x
`
`METAL 1
`
`Figure 6. SEM views illustrating design rules 15 and 16.
`
`19
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`METAL 1
`
`Photograph #15,
`Mag. 13,000x
`
`PASSIVATION
`
`METAL 2
`
`INTERLEVEL DIELECTRIC
`
`METAL 1
`
`PRE-METAL DIELECTRIC
`
`INTERLEVEL DIELECTRIC
`
`METAL 1
`
`SOG
`
`PRE-METAL DIELECTRIC
`
`Photograph #16,
`Mag. 13,000x
`
`Photograph #16,
`Mag. 26,000x
`
`Figure 7. SEM views illustrating design rules 17 and 18.
`
`20
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`RESIDUAL GLASS
`
`METAL 1
`
`Photograph #17, Type B,
`aluminum intact
`
`BARRIER
`
`Photograph #17, Type B,
`aluminum removed
`
`Figure 8. SEM views illustrating design rule 19. Mag. 13,000x.
`
`21
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`METAL 1
`
`POLYCIDE
`
`Photograph #18
`
`METAL 2
`
`INTERLEVEL DIELECTRIC
`
`METAL 1
`
`DIFFUSION
`
`Photograph #19
`
`Figure 9. SEM views illustrating design rules 20, 21, and 22. Mag. 13,000x.
`
`22
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`BARRIER
`
`Photograph #20, aluminum removed
`
`Figure 10. SEM view illustrating design rule 23. Mag. 13,000x.
`
`POLY
`
`Photograph #22
`
`Figure 11. SEM view illustrating design rules 25 and 26. Mag. 26,000x.
`
`23
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`P+ S/D
`
`POLY
`
`Photograph #23,
`Mag. 26,000x
`
`Photograph #25,
`Mag. 30,000x
`
`METAL 1
`
`P+ S/D
`
`P+ S/D
`
`SILICIDE
`
`POLY
`
`P+ S/D
`
`GATE OXIDE
`
`Photograph #25,
`Mag. 52,000x
`
`P+ S/D
`
`Figure 12. SEM views illustrating design rules 27 and 28.
`
`24
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`N+ S/D
`
`POLY
`
`Photograph #24,
`Mag. 26,000x
`
`INTERLEVEL DIELECTRIC
`
`METAL 1
`
`POLY
`
`N+ S/D
`
`N+ S/D
`
`Photograph #26,
`Mag. 26,000x
`
`METAL 1
`
`Photograph #26,
`Mag. 30,000x
`
`POLY
`
`N+ S/D
`
`Figure 13. SEM views illustrating design rules 27 and 29.
`
`25
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`P+ S/D
`
`N+ S/D
`
`POLY
`
`Photograph #27, Mag. 3250x
`
`P+ S/D
`
`N+ S/D
`
`POLY
`
`Photograph #27, Mag. 6500x
`
`Figure 14. SEM views illustrating design rule 30.
`
`26
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`BIT
`
`ENABLE
`
`metal 2
`
`metal 1
`
`poly
`
`GND
`
`WORD
`
`Figure 15. Topological SEM views of the EEPROM cell. Mag. 1625x, 0°.
`
`27
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`BIT ENABLE
`
`metal 2
`
`GND
`
`WORD
`
`Figure 16. Topological SEM views of the EEPROM cell. Mag. 3250x, 0°.
`
`metal 1
`
`28
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`1
`
`C
`
`2
`
`poly
`
`WORD
`
`BIT
`
`T
`
`2
`
`1
`
`C
`
`ENABLE
`
`Figure 17. Topological view and schematic of the EEPROM cell. Mag. 3250x, 0°.
`
`29
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`TUNNEL OXIDE
`WINDOW
`
`Figure 18. Topological SEM view of the tunnel oxide window. Mag. 26,000x, 0°.
`
`30
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`METAL 2
`
`METAL 1
`
`SELECT GATE
`
`TUNNEL OXIDE DEVICE
`
`Mag. 10,000x
`
`N+ S/D
`
`METAL 1
`BIT LINE CONTACT
`
`Mag. 26,000x
`
`POLYCIDE
`SELECT GATE
`
`N+ S/D
`
`METAL 1
`ENABLE LINE
`CONTACT
`
`N+ S/D
`
`Mag. 26,000x
`
`POLYCIDE
`
`Figure 19. SEM section views of an EEPROM cell (parallel to bit line).
`
`31
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`SILICIDE
`
`POLY
`
`N+ S/D
`
`TUNNEL OXIDE
`
`N+ S/D
`
`Mag. 52,000x
`
`SILICIDE
`
`POLY
`
`N+ S/D
`
`TUNNEL OXIDE
`
`Mag. 104,000x
`
`Figure 20. SEM section views of an EEPROM cell (parallel to bit line).
`
`32
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`CAPACITOR
`
`METAL 2
`
`METAL 1
`
`N+
`
`TUNNEL OXIDE
`DEVICE
`
`Mag. 8000x
`
`METAL 1 WORD
`LINE CONTACT
`
`POLYCIDE
`
`LOCAL OXIDE
`
`Figure 21. SEM section views of an EEPROM cell (perpendicular to bit line).
`
`Mag. 26,000x
`
`33
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`SILICIDE
`
`POLY
`
`TUNNEL OXIDE
`
`Mag. 40,000x
`
`SILICIDE
`
`POLY
`
`TUNNEL OXIDE
`
`N+
`
`Figure 22. SEM section views of an EEPROM cell (perpendicular to bit line).
`
`Mag. 104,000x
`
`34
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`WORD
`
`ENABLE
`
`GND
`
`A
`
`B
`
`metal 2
`
`metal 1
`
`poly
`
`Figure 23. Topological SEM views of an additional EEPROM cell. Mag. 1625x.
`
`35
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`WORD
`
`ENABLE
`
`GND
`
`metal 2
`
`A
`
`B
`
`metal 1
`
`Figure 24. Topological SEM views of an additional EEPROM cell. Mag. 2500x.
`
`36
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`4
`
`3
`
`2
`
`1
`
`C
`
`poly
`
`WORD
`
`A B
`
`4
`
`C
`
`T
`
`1
`
`2
`
`3
`
`ENABLE
`
`Figure 25. Topological view and schematic of an additional EEPROM cell.
`Mag. 2500x.
`
`37
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`Y
`
`BIT
`
`metal 2
`
`metal 1
`
`poly
`
`A
`
`VCC
`
`GND
`
`GND
`
`ENABLE
`
`A
`
`Figure 26. Topological SEM views of an additional EEPROM cell. Mag. 1625x.
`
`38
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`Y
`
`BIT
`
`metal 2
`
`A
`
`VCC
`
`GND
`
`GND
`
`ENABLE
`
`metal 1
`
`Figure 27. Topological SEM views of an additional EEPROM cell. Mag. 2500x.
`
`39
`
`

`
`Lattice ispLSI 2032-180L
`
`Integrated Circuit Engineering Corporation
`
`WORD
`
`WORD
`
`BIT
`
`A
`
`4
`
`3
`
`6
`
`5
`
`C
`
`2
`
`1
`
`poly
`
`2
`
`T
`
`1
`
`A
`
`3
`
`Y
`
`4
`
`6
`
`5
`
`C
`
`ENABLE
`
`Figure 28. Topological view and schematic of an additional EEPROM cell.
`Mag. 2500x.
`
`40

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