HANDBOOK OF
`MULTILEVEL
`METALLIZATION FOR
`INTEGRATED CIRCUITS
`Materials, Technology, and
`Applications
`
`Edited by
`
`Syd R. Wilson
`and
`Clarence J . Tracy
`
`Materials Research Organization
`Motorola Semiconductor Products Sector
`Mesa, Arizona
`
`John L. Freeman, Jr.
`
`Advanced Custom Technologies
`Motorola Semiconductor Products Sector
`Mesa, Arizona
`
`NOYES PUBLICATIONS
`Park Ridge, New Jersey, U.S.A.
`
`IPR2015-01087 - Ex. 1026
`Micron Technology, Inc., et al., Petitioners
`1
`
`

`

`Copyright C 1993 by Noyes Publications
`No pan of this book may be reproduced or utilized in
`any fonn or by any means, eleclronic or mechanical,
`including photocopying, recording or by any
`io.formation storage and retrieval system, without
`pennisslon in writing from the Publis her.
`Library of Congress Catalog Card Number: 93-26689
`ISBN: 0-8155-1340-2
`Printed in the United States
`
`Published in the United States of America by
`Noyes Publications
`Mill Road, Park Ridge, New Jersey 07656
`
`10 9 8 7 6 5 4 3 2 1
`
`Library of Congress Cataloging-in-Publi!=ation Data
`
`Handbook of multilevel roetaUi7..ation for integrated ci rcuits : materials,
`technology, and applications I edited by Syd R. Wilson, Clarence J. Tracy,
`lobo L Freeman, Jr.
`cro.
`p.
`Includes bibJjograpbical references and index.
`ISBN 0-8155-1340-2
`1. Integrated circuits-Design and construction. 2. Metall izing.
`I. Wilson, Syd R. II. Tracy, Clare nce J. Ill Freeman, John L
`TK7874.H3493 1993
`6213815--dc20
`
`93-26689
`CIP
`
`

`

`cy
`:onductor Products
`
`.er
`:onductor Products
`
`1ner
`dns University
`Laboratory
`
`::onductor Products
`
`g
`eering Department
`·sity
`
`. publication is
`• responsibility
`consequences
`•r informational
`·oduciS docs not
`, the Publisher.
`lion or product
`that use, is the
`yone intending
`ures mentioned
`suitability, and
`1dards.
`
`Table of Contents
`
`1
`
`INTRODUCTION ............................................................... 1
`Syd R. Wilson, Clarence J. Tracy, and John L. Freeman, Jr.
`1.0 MLM TERMINOLOGY AND STRUCTURE ................................. 1
`1.1 Structure Nomenclature ..................................................... 2
`1.2 Process or Fabrication Nomenclature ................................ 4
`1.3 Properties/ Behavior Nomenclature ................................... 6
`2.0 WHAT ARE THE USES OF METAL LAYERS
`IN AN INTEGRATED CIRCUIT? ................................................. 7
`2.1 Contact of the Devices and Other ,~lements ...................... 7
`2.2 Connecting Devices Together To Create Functions ........... 7
`2.3 Connecting Functions to Form Integrated Circuits ............. 8
`2.4 Power Distribution and Interface to the Package ................ 8
`3.0 WHY USE MUL TlPLE LAYERS OF METAL ............................... 8
`3.1 Allow a Tighter Packing of Devices .................................... 9
`3.2 Reduce the Chip Size or Increase the Number of
`Functions Per Chip .......................................................... 10
`3.3 Reduce the RC Time Constant of the
`Interconnect System ........................................................ 10
`4.0 TRENDS IN MULTILEVEL METALLIZATION ........................... 10
`5.0 METHODOLOGY FOR DEVELOPING AN MLM SYSTEM ....... 15
`5.1 Definition of the Target Technology ................................. 15
`5.2 Choice of Metal Pitch ...................................................... 17
`
`xl.ll
`
`

`

`xJv Contents
`
`5.3 Determination of the Metal Line and
`I LD Dimensions from Performance Modeling ................... 17
`5.4 Taking Account of the Effects of Processing and
`Reliability on Metal Line Dimensions and ILD Thickness .. 20
`5.5 Choice of Materials for Use in the MLM System .............. 22
`5.6 Defining the Preliminary Design Rules
`and Process Targets ........................................................ 23
`5.7 Process Integration Test Vehicle ........................... · .......... 27
`5.8 Final Design Rules .......................................................... 28
`6.0 SUMMARY ............................................................................... 28
`REFERENCES ....................................................................... ............ 29
`
`2
`
`1.0
`
`SILICIOES AND CONTt CTS FOR ULSI ................................. 32
`George E. Georgiou
`INTRODUCTION ...................................................................... 32
`1.1 Metallization and Device Performance ............................ 32
`1.2 AI·Si Reaction, Device Scaling and Barrier Materials ..... .. 35
`1.3 Sputtering Step Coverage and Need for
`CVD Metallization ............................................................ 37
`1.4 Planarization and Metallization ........................................ 40
`1. 5 Chapter Outline ............................................................... 42
`2.0 SILICIDES FOR APPLICATION TO SALICIDE
`AND POL YCIDE ....................................................................... 42
`2.1 Salicide- TiSi2 and CoSi2 ............................................................... 44
`2.2 Polycide-WSix orTaSix .................................................................. 53
`2.3 CMOS and Bipolar Contact Sllicides ................................ 56
`3.0 SPUTIERED BARRIER MATERIALS BETWEEN
`ALAND Si OR SILICIDE .......................................................... 59
`3.1 Ti and Ti-W ........................................................ ............. 60
`3.2 TiN and TiN on Ti .............................................. .............. 63
`4.0 CVD BARRIER MATERIALS .................................................... 67
`4.1 CVD TiN .......................................................................... 68
`4.2 Selective CVD W .............................................. .............. 73
`4.3 Blanket CVD W ............................................................... 78
`5.0 LOCAL INTERCONNECTS AND MULTILEVEL
`METALLIZATION ...................................................................... 82
`6.0 CONCLUSION AND FUTURE TRENDS ................................... 87
`REFERENCES ................................................................................... 90
`
`3
`
`ALUMINUM BASED MULTILEVEL METALLIZATIONS
`IN VLSI/ULSICs ....................................................................... 97
`K. Ramkumar, Sumanta K. Ghosh, and Arjun N. Saxena
`
`INTRODL
`1.0
`2.0 REQUIRE
`2.1 Cor
`3.0 APPLICA
`KEY PAC
`3.1 Cor
`3.2 Ho1
`3.3 Ve1
`lntE
`3.4
`4.0 PROPER
`4.1 Ma
`4.2 Ele
`4.3 AIL
`4.4
`La~
`4.5 Tu
`4.6 ML
`4.7 AI:
`4.8 AI:
`4.9 AI:
`5.0 CURREI
`MET ALL
`DE
`5.1
`5.2 Et
`5.3 PI
`5.4 Fe
`6.0 KEYRE
`MET AU
`6.1 H
`V1
`6.2
`7.0 FUTUR
`7.1 N·
`7.2 AI
`7.3 E
`8.0 SUMMJ
`REFERENCE
`
`4
`
`INORG
`Chiu H.
`INTROI
`1.0
`2.0 CVDPI
`2.1 c
`2.2 F
`2.3 F
`
`

`

`................... 17
`
`........................ 23
`........................ 27
`........................ 28
`.......................... 28
`....................... 29
`
`.................... 32
`
`.......................... 32
`..................... 32
`Materials ....... 35
`
`· ........................ 37
`..................... 40
`.................... 42
`
`................ 42
`.................... 44
`r ........ ,. ........... 53
`............ 56
`
`....... 59
`........ 60
`...... 63
`.. 67
`.. 68
`.. 73
`.. 78
`
`Contents xv
`
`INTRODUCTION ...................................................................... 97
`1.0
`2.0 REQUIREMENTS IN MULTILEVEL METALLIZATIONS ......... 100
`2.1 Conductors/Metals ......................................................... 100
`3.0 APPLICATIONS OF AIX IN MULTILEVEL METALLIZATIONS AND
`KEY PROBLEMS .................................................................... 1 02
`3.1 Contacts ........................................................................ 1 04
`3.2 Horizontal Interconnects ................................................ 105
`3.3 Vertical Interconnects (Via) ............................................ 106
`3.4
`lnterlevel Dielectrics ...................................................... 106
`4.0 PROPERTIES OF AI, AIX AND RELATED MATERIALS ......... 107
`4.1 Material Properties ........................................................ 1 07
`4.2 Electrical Properties ...................................................... 116
`4.3 Aluminum Alloys ............................................................ 119
`4.4 Layered Interconnects With Barrier Metals .................... 121
`4.5 Tungsten Clad AIX Interconnects ................................... 124
`4.6 Multilayer Interconnects ................................................. 124
`4.7 AIX Interactions With Barrier Metals .............................. 124
`4.8 AIX Interactions With ILDs ................................. .' ........... 125
`4.9 AIX Interactions With Silicides ....................................... 126
`5.0 CURRENT STATUS OF AI-BASED MULTIL.:EVEL
`METALLIZATIONS ................................................................. 126
`5.1 Deposition Technology .................................................. 127
`5.2 Etching of AI and Its Alloys ............................................ 143
`5.3 Planarization for Multilevel Metallization ........................ 151
`5.4 Four-Level Metallization Systems .................................. 168
`6.0 KEY RELIABILilY ISSUES IN AIX-BASED MULTILEVEL
`METALLIZATIONS AND SOME SOLUTIONS ........................ 170
`6.1 Horizontal Interconnects ................................................ 170
`Verticallnt.~rconnects (Contacts and Vias) ..................... 176
`6.2
`7.0 FUTURE DIRECiiONS .......................................................... 184
`7.1 New Dopants/Alloys ....................................................... 184
`7.2 Alternate Metallizations .................................................. 187
`7.3 Equipment ..................................................................... 189
`8.0 SUMMARY ............................................................................. 191
`REFERENCES ................................................................................. 193
`
`4
`
`INORGANIC DIELECTRICS ................................................... 202
`Chiu H. Ting
`INTRODUCTION .................................................................... 202
`1.0
`2.0 CVD PROCESS ...................................................................... 203
`2.1 Deposition Chemistry .................................................... 203
`2.2 Fundamental Reactions ................................................. 205
`2.3 PECVD .......................................................................... 212
`
`

`

`xvl Contents
`
`3.0 DEPOSITION EQUIPMENT ................................................... 214
`3.1
`LPCVD Systems ............................................................ 215
`3.2 APCVD Continuous Processing System ........................ 216
`3.3 PECVD Continuous Processing System ........................ 217
`3.4 Multichamber System .................................................... 217
`4.0 SPIN-ON DIELECTRICS ........................................................ 218
`4.1 Silicate SOG ................................................................. 219
`4.2 Siloxane SOG ............................................................... 221
`5.0 FILM CHARACTERIZATION .................................................. 223
`5.1 Stress Measurements .................................................... 223
`5.2 Moisture Measure ments ................................................ 227
`6.0. DOPED GLASSES ................................................................. 230
`6.1 PSG .............................................................................. 231
`6.2 BPSG ............................................................................ 234
`INTERMETAL LAYER DIELECiRIC ....................................... 243
`7.1 Dielectric Materials ........................................................ 244
`7.2 Deposition Reactions .............................................. ....... 244
`7.3 Step Coverage .............................................................. 245
`7.4 Water Absorption ........................................................... 253
`8.0 PASSIVATION LAYER ........................................................... 259
`8.1 PECVD SiN ................................................................... 260
`8.2 Plasma SiON ................................................................. 262
`9.0 SUMMARY ............................................................................. 265
`REFERENCES ....... ; ......................................................................... 266
`
`7.0
`
`5
`
`ORGANIC DIELECTRICS IN MULTILEVEL
`METALLIZATION OF INTEGRATED CIRCUITS ................... 274
`Krishna Seshan, Dominic J. Schepis and Laura B. Rothman
`1.0 GENERAL INTRODUCTION ................................................... 274
`2.0 HISTORICAL PERSPECTIVE ................................................. 277
`3.0 FUNDAMENTAL CHEMISTRY OF
`ORGANIC DIELECTRICS ....................................................... 283
`3.1 Materials Options .......................................................... 284
`3.2 Polyimide Structure ....................................................... 286
`3.3 Depositing Polyimides ................................................... 289
`3.4 Moisture Absorption ....................................................... 291
`3.5 Solvent Effects ......................................................... ..... 292
`3.6 Oxidation ....................................................................... 293
`3. 7 Dimensional Stability ..................................................... 293
`3.8 Metal-Polymer Interactions ............................................ 294
`3.9 Photosensitive Organic Dielectrics ................................ 297
`3.10 Summary ....................................................................... 297
`
`4.0 PROCES
`4.1 Sub
`4.2 Po~
`4.3 Curl
`4.4 Diffl
`4.5 Surr
`5.0 PROCES~
`5.1 Proc
`5.2 Path
`5.3 Planr
`5.4 Then
`5.5 Exan
`Semi
`5.6 Suriu
`6.0 RELIABilll
`6.1 Adha
`Into P
`6.2 Effecl
`6.3 Mech,
`6.4 Electr
`6.5 Long ·
`6.6 Sumn
`7.0 PERFORM)
`DIELECTRU
`7.1 Perfon
`Perfo~
`7.2
`7.3 Facto11
`8.0 FUTURE
`REFERENCES ...
`
`6
`
`1.0
`2.0
`
`2.6
`
`

`

`I
`
`.................... 214
`.................... 215
`..................... 216
`..................... 217
`..................... 217
`..................... 218
`..................... 219
`..................... 221
`..................... 223
`..................... 223
`...................... 227
`...................... 230
`...................... 231
`...................... 234
`...................... 243
`...................... 244
`...................... 244
`....................... 245
`....................... 253
`....................... 259
`....................... 260
`....................... 262
`....................... 265
`....................... 266
`
`rs ................... 274
`1 B. Rothman
`........................ 274
`........................ 277
`
`........................ 283
`........................ 284
`......................... 286
`......................... 289
`......................... 291
`......................... 292
`......................... 293
`......................... 293
`......................... 294
`......................... 297
`.......................... 297
`
`Contents
`
`xvll
`
`4.0 PROCESSING OF POLYMER FILMS .................................... 298
`4.1 Substrate Preparation and Polyimide Coating ................ 298
`4.2 Polyimide Adhesion ....................................................... 299
`4.3 Curing of Polyimides ..................................................... 301
`4.4 Diffusion of Water ......................................................... 301
`4.5 Summary ....................................................................... 302
`5.0 PROCESS INTEGRATION WITH ORGANIC DIELECTRICS . 303
`5.1 Processes for Forming MLM Structures ......................... 303
`5.2 Patterning of Organic Dielectrics ................................... 307
`5.3 Planarization ................................................................. 308
`5.4 Thermal Budget Considerations ..................................... 31 1
`5.5 Examples of Organic Dielectrics in
`Semiconductor Technologies ......................................... 313
`5.6 Summary ....................................................................... 314
`6.0 RELIABILITY ........................... ,. .............................................. 315
`6.1 Adhesion and its Connection to Diffusion of Metal
`into Polyimide; The Interphase and Interface Stress ...... 316
`6.2 Effect of Moisture Ingress ................................... , .......... 322
`6.3 Mechanical .................................................................... 324
`6.4 Electrical Properties ...................................................... 32:5
`6.5 Long Term Reliability ........................ : ............................ 328
`6.6 Summary ....................................................................... 330
`7.0 PERFORMANCE ADVANTAGES OF ORGANIC
`DIELECTRICS ........................................................................ 330
`7.1 Performance Comparisons ............................................ 330
`7.2 Performance Conclusions .............................................. 337
`7.3 Factors in the Ultimate t:.1mits to Performance ............... 337
`8.0 FUTURE TRENDS .................. ................................................ 339
`REFERENCES ................................................................................. 341
`
`6
`
`PLANARIZA TION TECHNIQUES ........................................... 346
`Jeff Olsen and Farhad Moghadam
`1.0 WHY PLANARIZE? ........................................................... · ..... 346
`2.0 CONCEPTS ............................................................................ 347
`2.1 Nomenclature ............... ................................................. 347
`2.2 Gap Filling ..................................................................... 348
`2.3 Topography Smoothing ................................................. 350
`2.4 Step Height Reduction ................................................... 355
`2.5 The Cost Of Achieving Long Range Or Global
`Planarization ................................................................. 357
`Integration Of Planarization Techniques ........................ 358
`
`2.6
`
`

`

`xvlil Contents
`
`3.0 THERMAL FLOW OF BOROPHOSPHOSILICATE GLASS
`{BPSG FILMS) ........................................................................ 359
`3.1 The BPSG Film ............................................................. 360
`3.2 The Flow-Anneal Process .............................................. 364
`3.3 Planarization Characteristics ......................................... 365
`3.4 Variations Of The Basic BPSG Deposition-
`Flow Sequence .............................................................. 367
`3.5 New Approaches To Glass Flow Planarization ............... 369
`4.0 PLANARIZATION WITH SACRIFICIAL PHOTORESIST ........ 371
`4.1
`Planarization Results; Idealized Case ............................ 372
`. 4.2 Planarization Results; Real World Cases ....................... 375
`4.3 Enhancements Of The Basic Resist-Etchback
`T echnlque ..................................................................... 378
`4.4 Global Planarization Using Resist-Etchback Methods .... 380
`5.0 PLANARIZATION USING SfiN-ON-GLASS ........................... 382
`5.1
`Elements Of SOG Planarization Techniques ................. 383
`5.2 Non-Etchback Techniques ............................................. 385
`5.3 Etchback Techniques .................................................... 391
`5.4 Planarization Results; Idealized Cases .......................... 392
`5.5 Planarization Results; Real-World Cases ................•...... 394
`5.6 Process Window ............................................................ 400
`5.7 Tradeoffs; Etchback vs. Non-Etchback Techniques ....... 401
`5.8 Additional Applications of and Enhancements
`to the Basic SOG Techniques ........................................ 402
`6.0 DEPOSITION-ETCH BACK TECHNIQUES ............................. 404
`6.1 · What Can Be Accomplished By Dep-Etch? ................... 404
`6.2 Facet-Forming Dep-Etch Techniques ............................ 409
`6.3 Spacer-Forming Oep-Etch Techniques .......................... 421
`6.4 Radius-Growth Dep-Etch Techniques ............................ 423
`6.5 Dep-Etch For Gap-Filling Plus Dep-Etch
`For Planarization ........................................................... 425
`7.0 PLANARIZATION BY CHEMICAL-MECHANICAL POUSHING . 426
`7.1 Planarization Techniques Using CMP ..................... ....... 427
`7.2 Polishing Mechanism ..................................................... 429
`7.3 Step Removal By Polishing ........................................... 431
`7.4 Technology And Manufacturing Issues .......................... 437
`8.0 GAP FILLING USING CVD OZONE-TEOS OXIDES .............. 439
`8.1 Conformal And Hyper-Conformal Step Coverage .......... 440
`8.2 Applications ................................................................... 441
`8.3
`Issues ............................................................................ 445
`9.0 OUTLOOK .............................................................................. 447
`REFERENCES ................................................................................. 448
`
`7
`
`1.0
`2.0
`
`LITHOGRJ
`MULTILE~
`Gregory W
`INTRODUC
`INTRODUC
`2.1 Resi!
`2.2 Resi!
`2.3 Gene
`2.4 Resi!
`MLM
`2.5 StepJ
`2.6 Metre
`2.7 MLM
`3.0 ETCH ........
`3.1 Conti
`3.2 Metal
`3.3 Plane
`3.4 ViaE
`3.5 Pad E
`3.6 Sumr
`REFERENCES ...
`
`I
`
`8
`
`ELECTRO·
`INTER CON
`Michael L. l
`1.0
`INTRODUC
`2.0 THEORYO
`3.0 ELECTROt-.
`3.1
`The t<
`4.0 MEASUREr
`CURRENT
`5.0 ELECTRO~
`5.1 Direct
`6.0 LIFE TEST
`6.1 Statis1
`6.2 Extraf
`Opera
`6.3 Electr'
`6.4 AC/Pt
`7.0 DAMAGEFI
`7.1 Electn
`8.0 STRESS-IN
`REFERENCES ....
`
`

`

`Contents
`
`xlx
`
`rE GLASS
`..................... 359
`...................... 360
`, ..................... 364
`...................... 365
`,..
`...................... 367
`ttlon ............... 369
`RESIST ........ 371
`...................... 372
`...................... 375
`·>ack
`....................... 378
`ck Methods .... 380
`....................... 382
`ISS ................. 383
`....................... 385
`....................... 391
`....................... 392
`....................... 394
`....................... 400
`achniques ....... 401
`1ents
`........................ 402
`........................ 404
`n? ................... 404
`........................ 409
`........................ 421
`........................ 423
`
`........................ 425
`1L POUSHING . 426
`........................ 427
`........................ 429
`........................ 431
`......................... 437
`(IDES .............. 439
`:overage .......... 440
`......................... 441
`......................... 445
`......................... 447
`......................... 448
`
`(
`
`7
`
`1.0
`2.0
`
`LITHOGRAPHY AND ETCH ISSUES FOR A
`MULTILEVEL METALLIZATION SYSTEM ............................ 461
`Gregory W. Grynkewich and John N. Helbert
`INTRODUCTION .................................................................... 461
`INTRODUCTION TO PATIERN TRANSFER TECHNOLOGY .. 461
`2.1 Resist Principles ............................................................ 463
`2.2 Resist Selection Performance Criteria ........................... 467
`2.3 General MLM Resist Processing .................................... 478
`2.4 Resist Processes For Reflective and Topographical
`MLM Situations .............................................................. 483
`2.5 Stepper Performance Criteria ........................................ 488
`2.6 Metrology ...................................................................... 505
`2.7 MLM Photolithographic Applications .............................. 507
`3.0 ETCH ...................................................................................... 528
`3.1 Contact Etch .................................................................. 529
`3.2 Metal Etch ..................................................................... 537
`3.3 Planarization Etch ......................................................... 556
`3.4 Via Etch ......................................................................... 564
`3.5 Pad Etch ........................................................... : ........... 566
`3.6 Summary ....................................................................... 567
`REFERENCES .................................................... : ............................ 569
`:J
`ELECTRO- AND STRESS-MIGRATION IN MLM
`INTERCONNECT STRUCTURES .......................................... 579
`Michael L. Dreyer and Paul S. Ho
`INTRODUCTION .................................................................... 579
`1.0
`2.0 THEORY OF ELECTROMIGRATION ..................................... 581
`3.0' ELECTROMIGRATION IN THIN FILMS .................................. 585
`3.1 The Kinetics of Damage Formation; Flux Divergence .... 587
`4.0 MEASUREMENT OF TEMPERATURE AND
`CURRENT DENSITY IN MLM STRUCTURES ........................ 593
`5.0 ELECTROMIGRATION MEASUREMENT TECHNIQUES ...... 597
`5.1 Direct Measurements of Mass Transport ........................ 598
`6.0 LIFE TEST METHOD ............................................................. 600
`6.1 Statistical Nature of ElectromigratiOI') Failure Times ...... 603
`6.2 Extrapolating Life Test Data To Circuit
`Operating Conditions ..................................................... 606
`6.3 Electromigration Characteristics .................................... 608
`6.4 AC/Pulsed DC Electromigration ..................................... 623
`7.0 DAMAGE FORMATION IN MULTILEVEL METALLIZATION .. 626
`7.1 Electro migration Damage in Multilevel Interconnects ..... 627
`8.0 STRESS-INDUCED VOID FORMATION ................................ 632
`REFERENCES ................................................................................. 641
`
`8
`
`

`

`xx Contents
`
`9
`
`MULTILEVEL METALLIZATION TEST VEHICLE ................. 648
`Syd R. Wilson, Charles J. Varker, and John L Freeman, Jr.
`INTRODUCTION .................................................................... 648
`1.0
`2.0 PROCESS CONTROL ............................................................ 650
`2.1 Test Chip Layout Considerations ................................... 650
`2.2 Process Control Structures ............................................ 651
`3.0 DEFECTlVIiY AND YIELD ENHANCEMENT STRUCTURES ... 665
`3.1 Combs, Snakes, and Snakes Combined with Combs ..... 666
`3.2 Via Chains ..................................................................... 669
`3.3 Contact Chains .............................................................. 671
`· 3.4 Via/Contact Chains at Minimum Pitch ............................ 672
`3.5 Stacked Via Chains or Vias Stacked On Contact Chains .. 673
`3.6
`Interdigitated Via C hains and Snakes ............................ 673
`3. 7 Capacitors ..................................................................... 67 4
`4.0 TEST STRUCTURES FOR RELIABILiiY ............................... 676
`4.1
`Introduction ................................................................... 676
`4.2 Conventional Methods of Reliability Testing
`and Analysis .................................................................. 678
`4.3 Multilevel Metallization Reliability Test Structures ......... 679
`4.4 Conventional Planar Electromigration Test Structures ... 680
`4.5 Test Structures For Accelerated Wafer Level
`Reliability Testing ...................... ~('· ................................ 682
`5.0 SUMMARY .... : ........................................................................ 685
`REFERENCES ................................................................................. 685
`
`10 MANUFACTURING AND ANALYTIC METHODS ................... 687
`Thomas Seidel
`1.0
`INTRODUCTION (BUSINESS PERSPECTIVES) ................... 687
`2.0 PERFORMANCE DRIVERS ................................................... 692
`3.0 ARCHITECTURE .................................................................... 694
`4.0 UNIT PROCESSES ................................................................ 695
`4.1
`Lithography ................................................................... 696
`4.2 Gate (Poly Etch) ............................................................ 697
`4.3 Contact (Silicide/Salicide) .............................................. 698
`4.4 Poly-to-Metal or ILDO ..................................................... 700
`4.5 ContacWia- Dielectric Etch .......................................... 701
`4.6 ContacWia - Barrier Films ............................................ 701
`4. 7 ContacWia - Fills .......................................................... 703
`4.8
`Interconnects - Deposition ............................................. 705
`4.9
`Interconnects- Aluminum Etch ...................................... 706
`4.1 0 I nterlevel or I ntermetal Dielectric ................................... 707
`4.11 Planarization ................................................................. 707
`4.12 Passivation .................................................................... 709
`
`5.0 KEY DESIC:
`6.0 DESIGN FC
`6.1 Metric
`6.2 MLM
`7.0 EQUIPMEN
`7.1 BaCk£
`7.2 Curre1
`8.0 CHALLENG
`8.1 Conta
`8.2 Metro!
`8.3
`lntegr:
`8.4 Cost c
`8.5 Limite
`8.6 Summ
`9.0 CONTROL I
`9.1 Statist
`9.2 Total F
`9.3 Analyt
`9.4 Test V
`9.5 Asserr
`1 0.0 SUMMARY.
`REFERENCES .....
`
`1.0
`2.0
`
`11 CHARACTE
`MULTILEVE
`Simon Thorn
`INTRODUCl
`IMAGING TE
`2.1 Scanni
`2.2 Transn
`2.3 Scanni1
`Force ~
`2.4 Thermc:
`2.5 Focuse
`3.0 SURFACE AI
`3.1 Auger E
`3.2 X-ray P
`3.3 Second
`4.0 THIN FILM 'B
`4.1 Electror
`4.2 Rutherf1
`4.3 X-Ray C
`4.4 X-Ray F
`
`

`

`LE ................. 648
`~reeman, Jr.
`....................... 648
`....................... 650
`....................... 650
`....................... 651
`"RUClURES ... 665
`Nith Combs ..... 666
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`........................ 672
`ontact Chains .. 673
`........................ 673
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`........................ 676
`......................... 676
`ling
`......................... 678
`aructures ......... 679
`est Structures ... 680
`Level
`......................... 682
`......................... 685
`.......................... 685
`
`>OS ................... 687
`
`ES) ................... 687
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`
`• •
`
`•
`
`Contents
`
`xxi
`
`5.0 KEY DESIGN RULES ............................................................. 709
`6.0 DESIGN FOR MANUFACTURE ............................................. 710
`6.1 Metrics for Design for Manufacturing ............................. 71 1
`6.2 MLM Examples of DFM ................................................. 713
`7.0 EQUIPMENT INTEGRATION ................................................. 715
`7.1 Background ................................................................... 715
`7.2 Current Tool Status ....................................................... 716
`8.0 CHALLENGES AND REQUIREMENTS .................................. 72.0
`8.1 Contamination ............................................................... 720
`8.2 Metrology Testbed ......................................................... 720
`8.3
`Integrator Ownership ..................................................... 722
`8.4 Cost of a Second Party's Selling Price ........................... 72.2
`8.5 Limited Flexibility of a Cluster Platform ......................... 722
`8.6 Summary of Equipment Integration ............................... 723
`9.0 CONTROL AND ANALYTIC CAPABILITY .............................. 723
`9.1 Statistical Process Control (SPC) .................................. 723
`9.2 Total Preventive Maintenance (TPM) ......