United States Patent [191
`Billig et al.
`
`11 11 Patent Number:
`1451 Date of Patent:
`
`5,025,300
`Jun. 18, 1991
`
`[54] INTEGRATED CIRCUITS HAVING
`IMPROVED FUSIBLE LINKS
`[75] Inventors: James N. Billig, Slatington; James D.
`Chlipnla; Kuo H. Lee, both of Lower
`Macungie Township, Lehigh
`County; W i a m J. Nagy,
`Bethlehem, all of Pa.
`[73] Assignee: ATBT Bell Laboratories, Murray
`Hill, N.J.
`[21] Appl. No.: 560,462
`Jul. 25,1990
`[22] Filed:
`
`Related U.S. Application Data
`[63] Continuation of Ser. No. 373,763, Jun. 30, 1989, aban-
`doned.
`Int. Cl.5 ..................... HOlL 29/34, HOlL 27/02;
`[5 11
`HOlL 23/48
`[52] U.S. Cl. ........................................ 357/51; 357/54;
`357/65
`[58] Field of Search .............................. 357/5 1, 54, 65
`References Cited
`I561
`U.S. PATENT DOCUMENTS
`3,792,319 2/1974 Tsang .................................. 317/235
`4,455,194 6/1984 Yabu et al. .......................... 156/653
`8/1985 Takayama et al. ................... 357/51
`4,536,949
`4,628,590 12/1986 Udo et al. ............................. 357/51
`4,692,190 9/1987 Komatsu ............................... 357/51
`
`................................
`4,720,470 1/1988 Johnson
`357/40
`4,774,561 9/1988 Takagi ................................... 357/51
`1/198Y Kawanabe et al. ................... 357/51
`4,795,720
`8/1989 Fischer .................................. 357/5 1
`4,853,758
`FOREIGN PATENT DOCUMENTS
`52-28280 3/1977 Japan ..................................... 357/51
`62-1 19938 1/1987 Japan ..................................... 357/51
`OTHER PUBLICATIONS
`"Process and Structure for Laser Fuse Blowing", ZBM
`Technical Disclosure Bulletin, vol. 31 (May 1989), p. 93.
`U.S. patent application Ser. No. 07/084531 (F. H. F i ,
`scher Case 3).
`Primary Examiner-J. Carroll
`Attorney, Agent, or Firm-James H. Fox
`ABSTRACT
`1571
`An integrated circuit includes a conductive fusible link
`(14) that may be blown by laser energy. The dielectric
`material (15) covering the fuse is etched away to expose
`the fuse. A protective dielectric layer (30) is formed on
`the fuse to a controlled thickness less than that of the
`interlevel dielectric. The resulting structure prevents
`shorts between conductors that might otherwise occur
`due to debris from the fuse-blowing operation, and
`provides protection to the integrated circuit. In addi-
`tion, the fuse blowing operation is more consistent from
`fuse to fuse.
`
`13 Claims, 1 Drawing Sheet
`
`IPR2015-01087 - Ex. 1010
`Micron Technology, Inc., et al., Petitioners
`1
`
`

`

`U.S. Patent
`US. Patent
`
`June 18, 1991
`June 18, 1991
`
`5,025,300
`
`
`
`I.
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`formed, and the fuse blown, before the deposition of a
`final caps dielectric layer.
`
`INTEGRATED CIRCUITS HAVING IMPROVED
`FUSIBLE LINKS
`
`This application is a continuation of application Ser. 5
`No. 373,763 filed Jun. 30, 1989, abandoned.
`
`BRIEF DESCRIPTION O F THE DRAWING
`FIG. 1 shows an integrated circuit having multi-level
`metal conductors and an interlevel dielectric.
`FIG. 2 shows the integrated circuit after etching off
`BACKGROUND O F THE INVENTION
`the intedevel dielectric from the fusible link.
`FIG. 3 shows the protective dielectric covering the
`1. Field of the Invention
`The present invention relates to a technique for mak- 10 fusible link.
`FIG. 4 shows debris resulting from blowing the fus-
`ing integrated circuits having improved fusible conduc-
`tive links.
`ible link.
`2. Description of the Prior Art
`DETAILED DESCRIPTION
`Integrated circuits frequently include fusible conduc-
`tive links ("fuses") that may be rendered non-conduc- 15 The following detailed description relates to an im-
`tive (i.e., "blown") by the application of laser energy.
`proved technique for forming integrated circuit fuses.
`Referring to FIG. 1, a first embodiment shows a semi-
`For example, in dynamic or static memory chips, defec-
`conductor substrate 10 having formed thereon a dielec-
`tive memory cells may be replaced by blowing the fuses
`tric layer 11. The substrate is silicon in the illustrative
`associated with the defective cells, and activating a
`spare row or column of cells, which may also be accom- 20 case, and the dielectric layer is typically grown or de-
`posited silicon dioxide. Shown on the dielectric layer 11
`plished by blowing fuses. Logic circuits may also be
`is a first conductor 12, which is optional insofar as the
`repaired or reconfigured by blowing fuses. For exam-
`ple, it is known to initially fabricate a generic logic chip
`present invention is concerned, but when present typi-
`having a large number of interconnected logic gates.
`cally comprises doped polysilicon, and may also include
`Then, in a final processing step, the chip is customized 25 a metal silicide in part or all of the conductor 12.
`Formed on conductor 12 is a dielectric layer 13, typi-
`to perform a desired logic function by disconnecting the
`cally a flowable glass, such as a borophosphosilicate
`unnecessary logic elements by blowing the fuses that
`glass (BPSG). The layer 13 may be a spin-on glass, or
`connect them to the desired circuitry. Still other appli-
`cations of laser-blown fuses are possible.
`may be deposited from a variety of precursor gases,
`The reliability of blowing the fuses is significant, 30 including tetraethoxysilane (TEOS), or alternately si-
`especially when a large number of fuses must be suc-
`lane (SiH4), according to principles known in the art.
`The dielectric layer 13 is typically formed subsequent to
`cessfully blown for an integrated circuit to function
`properly. One limiting factor in successful fuse blowing
`the formation of active device regions, including, for
`is the minimum laser energy required to blow the fuses.
`example, gate, source, and drain regions, which may be
`That is, if the laser energy is not high enough, then some 35 made by methods known in the art.
`A fusible link 14 is formed on layer 13 by depositing
`of the fuses that are to be blown will not in fact be
`rendered non-conductive. Such process variables as the
`a metal layer, and patterning it by techniques known in
`the art. The metal is typically aluminum in present sili-
`thickness or width of the fuse, and the variations in the
`laser energy from one shot to the next, can affect the
`con technology, or gold in present group 111-V tech-
`reliability of fuse blowing. On the other hand, the debris 40 nology, with other metals, including refractory metals,
`generated by successfully blowing the link can itself
`being possible. The fusible link may be a target area of
`lead to reliability problems. That is, if the conductive
`a metal runner that is of the same geometry (width and
`link material (typically doped polysilicon, metal silicide,
`height) as the rest of the runner. Alternately, the fusible
`or a metal) is re-deposited on the chip after the fuse is
`link may be a portion of a metal runner that has reduced
`blown, then it may land in an area that could cause 45 cross-sectional area for improved ease of blowing by
`reliability concerns. For example, the blown link mate-
`laser irradiation. One technique for locally reducing the
`rial may re-deposit so as to short together two conduc-
`height of the metal runner in the fusible link portion is to
`tors on the same or different levels of the chip.
`first deposit a metal layer of a given thickness, in the
`One technique for improving the reliability of blow-
`conventional fashion. Then, a window is etched in the
`ing fuses with radiant (e.g., laser) energy is described in 50 metal layer in the area were the fuse is to be formed.
`co-assigned U.S. patent application Ser. No. 07/084531
`Next, a thin metal layer is deposited. The two metal
`now U.S. Pat. No. 4,853,758. As taught therein, the
`layers are then patterned to form the desired metal
`dielectric material covering a fuse may be partially
`runners having a thickness that includes both layers,
`etched away, reducing its thickness over a fuse that is
`while leaving a fusible link of reduced thickness in the
`formed in a lower conductor level. This allows the fuse 55 region of the window. This optional fuse-forming tech-
`to blow more easily (that is, at a lower energy level)
`nique is further described in co-pending application Ser.
`than if the full dielectric thickness were retained.
`No. 07/374,423 filed 6/30/89, and co-assigned here-
`with. It is significant that metal tends to reflect laser
`energy more than polysilicon or metal silicides in most
`cases, so that the problem of successfully blowing a
`metal link is greater than for blowing fuses formed of
`these other materials.
`The fusible link has a dielectric layer 15 formed
`thereon, which is referred to as the "interlevel" dielec-
`tric herein. Layer 15 is typically silicon dioxide depos-
`ited at a relatively low temperature, and may be depos-
`ited from TEOS or other precursor gases. In the illus-
`trative embodiment, an optional second level metal
`
`SUMMARY O F THE INVENTION
`We have invented a technique for improving the 60
`reliability of blowing fuses in a solid state device. In one
`embodiment, the dielectric layer covering the fuse is
`selectively etched away to expose the fuse. A controlled
`thickness of a protective dielectric material is then
`formed to cover the link, prior to blowing the fuse. The 65
`thickness of the protective dielectric is less than the
`thickness of the dielectric that was etched from the fuse.
`In another embodiment, a protective dielectric layer is
`
`3
`
`

`

`5,025,300
`
`3
`4
`controlled over the surface of the wafer, and the varia-
`conductor is formed on the interlevel dielectric layer 15
`tions in the multiple depositions are additive, so that the
`by deposition and patterning, which may be accom-
`final thickness of the interlevel dielectric may vary over
`plished in the same manner as for the first level metal. In
`a relatively wide range. For example, the thickness
`an illustrative process used with CMOS integrated cir-
`cuits formed with 1.25 micrometer minimum line- 5 variation is typically greater than plus or minus 25 per-
`widths, the first level metal runner is aluminum having
`cent, and in one present two-level metal process in a 0.9
`a thickness of 500 nanometers (5000 angstroms) and a
`micrometer technology, the variation in the interlevel
`width of 1.75 micrometers. The interlevel dielectric is
`dielectric thickness is about plus or minus 50 percent for
`phosphorus doped TEOS having a thickness of 600
`a nominal 700 nanometer (7000 angstrom) thickness. On
`nanometers (6000 angstroms) over the fusible link.
`10 the other hand, the re-deposited protective dielectric
`typically has a thickness that is controlled to within plus
`Referring to FIG. 2, the interlevel dielectric is etched
`or minus 10 percent in present processes. A grown
`off the fusible link portion 14 of the patterned conduc-
`dielectric may also have a relatively well controlled
`tor. In the illustrative case, the etched region extends 10
`thickness. The use of the inventive technique allows the
`micrometers along the length of the fusible link (perpen-
`dicular to the plane of the drawings), and extends 8 15 dielectric layer to fracture more uniformly, and the
`micrometers laterally. This may be accomplished by
`molten (or vaporized) link material to be ejected more
`conventional lithographic and etching techniques. For
`consistently.
`Referring to FIG. 4, the fusible link area is shown
`example, in the illustrative case, a 1 micrometer thick
`after the link is blown by application of laser energy.
`photoresist layer (not shown) is deposited over the
`interlevel dielectric 15 (and second level metal conduc- 20 For the above-noted fusible link, a neodymium-YAG
`tors 16 and 17) and patterned by conventional litho-
`laser at a wavelength of 1064 nanometers and energy of
`graphic techniques to expose the fusible link 14. The
`about 1.25 micro-Joules, using a 45 nanosecond full-
`interlevel dielectric is then etched off the fusible link
`width-half-maximum (FWHM) pulse, is sufficient to
`using reactive ion etching techniques known in the art.
`blow the link. As can be seen in the illustrative case, the
`To ensure complete removal of the interlevel dielectric 25 metal debris 40-42 that may result is prevented by the
`from the fusible link, over-etching is accomplished so
`protective dielectric from contacting adjacent conduc-
`that about 300 nanometers (3000 angstroms) of the glass
`tor regions. Otherwise, it is apparent that the debris
`layer 13 is also removed, as shown. Note that the photo-
`could readily short out the various first and second level
`resist serves as an etch mask to prevent removal of the
`metal conductors to the same or another metal level.
`interlevel dielectric from regions adjacent to the fusible 30 After the link-blowing operation, the integrated circuit
`link. After etching, the photoresist etch mask is re-
`wafer is desirably cleaned in a commercial cleaning
`solution (e.g. PRS 1000) to remove loose debris. A final
`moved by conventional techniques.
`Referring to FIG. 3, a layer of protective dielectric
`"caps" layer, typically of silicon nitride or silicon diox-
`material 30 is formed on the exposed top surface (as
`ide, is usually deposited over the surface of the inte-
`viewed) of the integrated circuit precursor. The protec- 35 grated circuit for protection, according to principles
`tive dielectric may be formed by deposition, as in the
`known in the art.
`The foregoing illustrative example has shown the
`illustrative embodiment. Hence, the exposed portion of
`the fusible link 14, the second level metal runners 16,17,
`fusible link in the bottom metal level in a two metal
`level structure, in which case the dielectric removed
`the interlevel dielectric 15, and the portions of the glass
`layer 13 adjacent to the fusible link are covered by the 40 from the fuse is an "interlevel" dielectric. However, the
`protective dielectric 30. The thickness of the protective
`fuse may be located in the top metal level (e.g. 16, 17),
`which is normally covered by a relatively thick "caps"
`dielectric layer is less than that of the interlevel dielec-
`tric, and typically less than one-half the thickness of the
`layer of silicon dioxide or silicon nitride (not shown). In
`interlevel dielectric. However, the thickness of the pro-
`that case, the caps layer may be selectively etched to
`tective dielectric layer is typically at least 10 nanome- 45 expose the fuse, and the protective layer formed prior to
`ters (100 angstroms), in order to provide adequate pro-
`the fuse blowing operation. If desired, an optional final
`caps layer may then be deposited to help ensure protec-
`tection. In the illustrative embodiment, the protective
`dielectric layer is a low temperature oxide (TEOS)
`tion of the device. Alternately, the protective dielectric
`having a thickness of 200 nanometers (2000 angstroms).
`layer may be formed on the top metal layer, and the fuse
`The protective dielectric layer is retained over the ac- 50 blown, prior to deposition of the final caps layer. In that
`case, no selective etching of the caps layer is necessary.
`tive device area of the integrated circuit. However, it is
`Still more metal levels are possible, with the use of the
`typically removed by standard lithographic and etching
`techniques from the bondpads, in order to allow for
`protective dielectric according to the inventive tech-
`electrical connections to be made to the bondpads.
`nique being possible for fuses formed in any of the pat-
`The use of a protective dielectric of reduced thick- 55 terned metal levels. It is also possible to practice the
`ness (as compared to the interlevel dielectric) allows the
`present invention for fuses formed in a polysilicon or
`silicide conductor level (e.g., 12 in FIG. 1).
`fusible link to be blown more consistently and cleanly
`Although silicon dioxide has been described as the
`than would be the case if the full thickness of the inter-
`protective dielectric in the illustrative embodiment
`level dielectric layer 15 were retained. This is because a
`protective dielectric layer that is re-deposited, or 60 above, the use of other dielectrics is possible. For exam-
`ple, silicon nitride and silicon oxynitride may be used.
`grown, on the fusible link can have a much better con-
`trolled thickness than is typically possible for the inter-
`The use of a grown (instead of deposited) protective
`level dielectric. That is, the process steps for forming
`dielectric is also possible. For example, an aluminum
`the interlevel dielectric usually include not only a depo-
`conductor may have its surface oxidized to obtain a
`sition step, but also at least one etch-back step, followed 65 protective dielectric surface layer of A1203 of the de-
`by another deposition step, in order to obtain a void-
`sired thickness. This may be conveniently accomplished
`free interlevel dielectric having a relatively planar sur-
`by introducing oxygen into the plasma-producing appa-
`face. However, the etch-back step is not very easily
`ratus (e.g., a reactive ion etcher) that was previously
`
`4
`
`

`

`5,025,300
`
`5
`6
`5. The integrated circuit of claim 1 having a top metal
`used to etch the pattern into the aluminum layer. How-
`level, wherein said at least one conductive fusible link is
`ever, note that a grown dielectric will form only over
`formed in said top metal level.
`the exposed surfaces (top and sides) of the patterned
`6. The integrated circuit of claim 1 wherein said pro-
`conductor levels (e.g., 14, 16 and 17), and will not form
`over the interlevel dielectric. Still other metal used to 5 tective dielectric layer has a thickness less than on-half
`form the patterned metal level that includes the fusible
`said given thickness.
`7. The integrated circuit of claim 1 wherein said pro-
`links may have oxides, nitrides, or other dielectric lay-
`tective dielectric layer has a thickness of at least 10
`ers grown thereon.
`In addition to the above-noted advantages relating to
`nanometers.
`reliability and ease of link blowing, the use of the pro- 10
`8. An integrated circuit comprising a patterned metal
`tective dielectric helps prevent contaminants from
`level formed on a first layer of dielectric material (e.g.,
`reaching the active device areas on the integrated cir-
`13), and a second layer of dielectric material (e.g., 15) of
`a given thickness covering portions of said patterned
`cuit substrate. This allows the laser processing to be
`accompiished under non-clean room conditions, and
`metal level, wherein said patterned metal level includes
`also helps protect the integrated circuit from scratches. 15 at least one conductive fusible link portion (e.g., 14)
`What is claimed is:
`having top and side surfaces that are not covered by
`1. An integrated circuit comprising a patterned metal
`said second layer of dielectric material,
`level formed on a first layer of dielectric material (e.g.,
`Characterized in that said fusible link portion of said
`13), and a second layer of dielectric material (e.g., 15) of
`patterned metal level has formed thereon a protec-
`tive dielectric layer (e.g., 30) comprising an oxide
`a given thickness covering portions of said patterned 20
`metal level, wherein said patterned metal level includes
`or nitride of said metal having a thickness on said
`at least one conductive fusible link portion (e.g., 14) that
`top and side surfaces of at least 10 nanometers but
`less than said given thickness.
`is not covered by said second layer of dielectric mate-
`9. The integrated circuit of claim 8 wherein said fus-
`rial,
`Characterized in that said fusible link portion and said 25 ible link is aluminum.
`10. The integrated circuit of claim 8 wherein said
`second layer of dielectric material are covered by a
`protective dielectric layer (e.g., 30) having a thick-
`fusible link is a refractory metal.
`ness less than said given thickness, wherein said
`11. The integrated circuit of claim 8 further compris-
`second layer and said protective dielectric layer
`ing an additional patterned metal level (e.g., 16, 17)
`each essentially comprise silicon dioxide.
`30 formed on said second layer of dielectric material,
`2. The integrated circuit of claim 1 wherein said fus-
`wherein said second layer of dielectric material is an
`ible link is aluminum.
`interlevel dielectric.
`3. The integrated circuit of claim 1 wherein said fus-
`12. The integrated circuit of claim 8 having a top
`ible link is a refractory metal.
`metal level, wherein said at least one conductive fusible
`4. The integrated circuit of claim 1 further compris- 35 link is formed in said top metal level.
`13. The integrated circuit of claim 8 wherein said
`ing an additional patterned metal level (e.g., 16, 17)
`formed on said second layer of dielectric material,
`protective dielectric layer has a thickness less than on-
`wherein said second layer of dielectric material is an.
`half said given thickness.
`*
`*
`*
`*
`*
`
`interlevel dielectric.
`
`40
`
`.
`
`5
`
`