`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`MICRON TECHNOLOGY, INC., AND MICRON MEMORY JAPAN, INC.,
`Petitioners
`
`v.
`
`MASSACHUSETTS INSTITUTE OF TECHNOLOGY
`Patent Owner
`____________________
`
`Case: IPR2015-01087
`U.S. Patent No. 6,057,221
`____________________
`
`
`
`DECLARATION OF DR. MICHAEL THOMAS IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW
`
`IPR2015-01087 – Ex. 1001
`Micron Technology, Inc. et al., Petitioners
`1
`
`

`

`Table of Contents
`
`I.  BACKGROUND AND QUALIFICATIONS ................................................................. 8 
`
`II.  ASSIGNMENT AND MATERIALS REVIEWED ...................................................... 9 
`
`III.  TECHNOLOGY BACKGROUND ............................................................................ 11 
`
`IV.  THE ’221 PATENT ................................................................................................. 13 
`
`V.  UNDERSTANDING OF THE LAW ......................................................................... 19 
`
`A.  Anticipation .................................................................................................... 19 
`
`B.  Obviousness ................................................................................................... 19 
`
`VI.  LEVEL OF ORDINARY SKILL IN THE ART .......................................................... 21 
`
`VII. PATENTABILITY ANALYSIS .................................................................................. 22 
`
`A.  Claim Construction ....................................................................................... 22 
`
`B. 
`
`Scope and content of the prior art ............................................................. 25 
`
`1.  Koyou .......................................................................................................... 25 
`
`2.  Wada ............................................................................................................ 31 
`
`3. 
`
`4. 
`
`Lou ............................................................................................................... 34 
`
`Billig ............................................................................................................. 36 
`
`C.  Koyou anticipates Claims 3-4, 6-8, 23, 25-26, and 28 of the ʼ221 patent
`
`38 
`
`1. 
`
`2. 
`
`Independent Claim 3 ................................................................................. 38 
`
`Independent Claim 26 ............................................................................... 49 
`
`3.  Dependent Claims 4, 6-8, 23, 25 and 28 ................................................ 51 
`
`D.  Wada and either of Lou or Billig, combined with general knowledge in
`the art, render Claims 14-15 and 29 of the ʼ221 patent obvious ..................... 56 
`
`1. 
`
`Independent Claim 14 ............................................................................... 57 
`
`
`
`2
`
`

`

`2.  Dependent claims 15 and 29 .................................................................... 63 
`
`3.  Motivation to combine the teachings of Wada and either of Lou or
`Billig, with the general knowledge in the art ................................................... 65 
`
`Patent Owner’s reexamination arguments do not overcome
`4. 
`unpatentability over Wada and either of Lou or Billig, and the general
`knowledge in the art ............................................................................................ 68 
`
`E.  Koyou and Wada, combined with general knowledge in the art, render
`claims 3-4, 6-8, 23, 25-26 and 28 of the ʼ221 patent obvious .......................... 71 
`
`1.  Koyou and Wada, combined with general knowledge in the art,
`disclose every limitation of claims 3-4, 6-8, 23, 25-26 and 28 ...................... 72 
`
`2.  Motivation to combine Koyou, Wada, and the general knowledge in
`the art ..................................................................................................................... 78 
`
`Patent Owner’s reexamination arguments do not overcome
`3. 
`unpatentability over Koyou, Wada and the general knowledge in the art .. 80 
`
`F.  Koyou and either of Lou or Billig render claims 13, 17-18, 21-22, 24,
`27, and 30 of the ’221 patent obvious .................................................................. 87 
`
`G.  Koyou, Wada and either of Lou or Billig, combined with general
`knowledge in the art, render claims 13, 17-18, 21-22, 24, 27, and 30 of the
`’221 patent obvious ................................................................................................. 89 
`
`
`
`
`
`
`
`3
`
`

`

`EXHIBITS
`
`Exhibit #
`
`Exhibit Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`Declaration of Dr. Michael Thomas
`
`Curriculum Vitae of Dr. Michael Thomas
`
`U.S. Patent No. 6,057,221
`
`File History for U.S. Patent No. 6,057,221
`
`The New IEEE Standard Dictionary of Electrical and Electronic Terms, Fifth
`Ed., Institute of Electrical and Electronics Engineers, Inc., New York
`(1993)
`
`Japan Pat. Appl. Publ. No. 8-213465 to Koyou (including English
`translation and supporting declaration)
`
`Japan Pat. Appl. Publ. No. 6-244285 to Wada, et al. (including English
`translation and supporting declaration)
`
`1008
`
`U.S. Patent No. 5,729,042 to Lou et al.
`
`1009
`
`U.S. Patent Application No. 514,800 filed August 14, 1995 (to which U.S.
`Pat. No. 5,729,042 claims priority)
`
`1010
`
`U.S. Patent No. 5,025,300 to Billig et al.
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`Ex Parte Reexamination Application No. 90/011,607, Request for Ex
`Parte Reexamination filed March 30, 2011
`
`Ex Parte Reexamination Application No. 90/011,607, Corrected Pre-
`amendment under 35 C.F.R. 1.530 filed April 14, 2011
`
`Ex Parte Reexamination Application No. 90/011,607, Order Granting
`Request for Ex Parte Reexamination filed June 23, 2011
`
`Ex Parte Reexamination Application No. 90/011,607, Non-Final Office
`Action of January 26, 2012
`
`Ex Parte Reexamination Application No. 90/011,607, Request for
`Reconsideration filed March 26, 2012
`
`
`
`4
`
`

`

`1016
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`Ex Parte Reexamination Application No. 90/011,607, Declaration of Dr.
`Bernstein filed March 26, 2012 (including exhibits)
`
`Ex Parte Reexamination Application No. 90/011,607, Notice of Intent to
`Issue Ex Parte Reexamination Certificate of July 11, 2012
`
`“Thermal Conductivity of Metals,” The Engineering
`ToolBox, http://www.engineeringtoolbox.com/thermal-conductivity-
`metals-d_858.html (last visited April 1, 2015)
`
`Pierson, Handbook of Refractory Carbides and Nitrides: Properties,
`Characteristics, Processing, and Applications, Noyes Publications (1996)
`
`U.S. Patent No. 5,872,389 to Nishimura et al.
`
`U.S. Patent No. 5,675,174 to Nakajima
`
`U.S. Patent No. 5,538,924 to Chen
`
`U.S. Patent No. 5,300,461 to Ting
`
`U.S. Patent No. 5,729,041 to Yoo
`
`1025
`U.S. Patent No. 5,747,869 to Prall
`1026 Wilson et al., Handbook of Multilevel Metallization For Integrated Circuits:
`Materials, Technology, and Applications, Noyes Publications (1993)
`1027 Wolf, Silicon Processing for the VLSI ERA Volume 2: Process Integration,
`Lattice Press, Sunset CA (1990)
`
`1028
`
`1029
`
`Construction Analyses of the Samsung KM44C4000J-7 16 Megabit
`DRAM, published by Integrated Circuit Engineering, Scottsdale AZ,
`Report No. SCA 9311-3001 (available at
`http://smithsonianchips.si.edu/ice/cd/9311_300.pdf)
`
`Construction Analyses of the Lattice ispLSI2032-180L CPLD, published
`by Integrated Circuit Engineering, Scottsdale AZ, Report No. SCA 9712-
`573 (available at http://smithsonianchips.si.edu/ice/cd/9712_573.pdf)
`
`
`
`5
`
`

`

`1030
`
`1031
`
`1032
`
`1033
`
`1034
`
`1035
`
`1036
`
`1037
`
`1038
`
`Construction Analysis of the Intel Pentium Processor w/MMX,
`published by Integrated Circuit Engineering, Scottsdale AZ, Report No.
`SCA 9706-540 (available at
`http://smithsonianchips.si.edu/ice/cd/9706_540.pdf)
`
`“Intel Introduces The Pentium® Processor With MMX™ Technology,”
`http://www.intel.com/pressroom/archive/releases/1997/dp010897.htm
`(last visited April 14, 2015)
`
`“Intel Microprocessor Quick Reference Guide,”
`http://www.intel.com/pressroom/kits/quickreffam.htm#pentium (last
`visited April 26, 2015)
`
`Construction Analyses of the Motorola PC603R Microprocessor,
`published by Integrated Circuit Engineering, Scottsdale AZ, Report No.
`SCA 9709-551 (available at
`http://smithsonianchips.si.edu/ice/cd/9709_551.pdf)
`
`Construction Analyses of the Toshiba TC5165165AFT-50 64 Mbit
`DRAM, published by Integrated Circuit Engineering, Scottsdale AZ,
`Report No. SCA 9702-524 (available at
`http://smithsonianchips.si.edu/ice/cd/9702_524.pdf)
`
`“Material: Stainless steel, bulk,”
`https://www.memsnet.org/material/stainlesssteelbulk/ (last visited April
`14, 2015)
`
`“Material: Silicon Dioxide (SiO2), bulk,”
`https://www.memsnet.org/material/silicondioxidesio2bulk/ (last visited
`April 14, 2015)
`
`Osaka, et al. “Development of new electrolytic and electroless gold
`plating processes for electronics applications,” Science and Technology
`of Advanced Materials, vol. 7 (2006), pp. 425-437.
`
`Uttecht et al., "A four-level-metal fully planarized interconnect
`technology for dense high performance logic and SRAM applications,"
`VLSI Multilevel Interconnection Conference, 1991, Proceedings, Eighth
`International IEEE, June 11-12, 1991, pp. 20-26.
`
`1039
`
`Ex Parte Reexamination Application No. 90/011,607, Patent Owner
`Statement filed August 12, 2011
`
`
`
`6
`
`

`

`1040
`
`1041
`
`Seshan ed., Handbook of Thin-Film Deposition Processes and Techniques:
`Principles, Methods, Equipment and Applications, Second Ed., Noyes
`Publications, New York (2002)
`
`Vlassak, et al., “A new bulge test technique for the determination of
`Young’s modulus and Poisson’s ratio of thin films”, J. Mater. Res., Vol.
`7, No. 12, Dec 1992.
`
`
`
`7
`
`

`

`
`I, Michael E. Thomas, hereby declare:
`
`I.
`
`1.
`
`BACKGROUND AND QUALIFICATIONS
`
`I have worked in the field of integrated circuit fabrication since 1979. From
`
`1979 to 2003, I performed and/or led research and development relating to barrier,
`
`insulating, and conductive thin film processing and advanced sub-micron interconnect
`
`design and fabrication for VLSI memory and logic devices.
`
`2.
`
`From 1979 to 1987, I was employed at Fairchild Semiconductor Corporation
`
`where I performed material and process R&D for micron and submicron multilevel
`
`interconnect technologies, including barrier and interconnect metallization, inorganic
`
`inter-level dielectric materials and novel thin film conductor structures. I also
`
`developed a three-level metal interconnect specification for production of advanced
`
`bipolar and CMOS memory and logic.
`
`3.
`
`From 1987 to 1999, I was employed at National Semiconductor Corporation
`
`where my responsibilities included evaluating new deep sub-micron interconnect
`
`technology and performing extensive yield analyses associated with interconnect
`
`processing. I was also co-chair for the SIA National Roadmap Committee for
`
`Interconnect Technology representing National Semiconductor.
`
`4.
`
`From 1999 to 2003, I was Chief Technology Officer in Honeywell Electronic
`
`Materials Corporation where I organized an 80+ person research team to assemble a
`
`facility to develop and evaluate low k dielectric, PVD metallization and lithography
`
`
`
`8
`
`

`

`products for deep submicron manufacturing technologies. I also participated in the
`
`International Interconnect Technology Conference Organizing Committee (IITC) to
`
`promote greater knowledge of the required interconnect technology for advanced
`
`circuit requirements.
`
`5.
`
`Since 2003, I have provided expert consulting services in the fields of VLSI
`
`device fabrication, including thin film deposition technology, interconnect
`
`manufacturing and packaging technology.
`
`6.
`
`I am an author of over 40 scholarly publications and am a named inventor of
`
`over 50 patents relating to semiconductor devices and manufacturing technology.
`
`7.
`
`I hold dual B.S.E. degrees in Chemical and Metallurgical Engineering from the
`
`University of Michigan (1973), and a Ph.D. in Materials Science and Engineering from
`
`Stanford University (1980).
`
`8.
`
`A copy of my curriculum vitae is attached as Exhibit 1002 hereto.
`
`II. ASSIGNMENT AND MATERIALS REVIEWED
`
`9.
`
`I submit this declaration in support of a petition for inter partes review of U.S.
`
`Patent No. 6,057,221 (“the ’221 patent”) (Ex. 1003) by Micron Technology, Inc.
`
`(“Micron”) and Micron Memory Japan, Inc. (“Micron Memory Japan” or “MMJ”)
`
`(collectively “Petitioners”).
`
`10.
`
`I have been informed that the ’221 patent is currently owned by Massachusetts
`
`Institute of Technology (“MIT” or “Patent Owner”).
`
`11.
`
`I am not an employee of Micron, MMJ, or of any affiliate or subsidiary thereof.
`
`
`
`9
`
`

`

`12.
`
`I am being compensated for my time at a rate of $650 per hour. My
`
`compensation is in no way dependent on the substance of the opinions I have offered
`
`below, or upon the outcome of Petitioners’ petition for inter partes review (or the
`
`outcome of the inter partes review, if trial is instituted).
`
`13.
`
`I have been asked to provide certain opinions regarding the patentability of the
`
`’221 patent. Specifically, I have been asked to provide an opinion as to whether
`
`Japanese Patent Application Publication No. 8-213465 to Koyou (“Koyou”) (Ex.
`
`1006) discloses every limitation of claims 3-4, 6-8, 23, 25-26 and 28 to one of ordinary
`
`skill in the art, and as to whether in addition, or in the alternative, claims 3-4, 6-8, 13-
`
`15, 17-18 and 21-30 would have been obvious over one or more of Koyou, Japanese
`
`Patent Application Publication No. 6-244285 to Wada, et al. (“Wada”) (Ex. 1007), U.S.
`
`Patent No. 5,729,042 to Lou et al. (“Lou”) (Ex. 1008 and Ex. 1009) and U.S. Patent
`
`No. 5,025,300 to Billig et al. (“Billig”) (Ex. 1010).
`
`14. The opinions expressed in this declaration are not exhaustive of my opinions
`
`on the patentability of claims 3-4, 6-8, 13-15, 17-18 and 21-30. Therefore, the fact
`
`that I do not address a particular point should not be understood to indicate any
`
`opinion on my part that any claim otherwise complies with the patentability
`
`requirements.
`
`15.
`
`I have also been asked to consider, in particular, a Request for Reconsideration
`
`of March 26, 2012 (Ex. 1015), and a declaration in support thereof, submitted during
`
`an ex parte reexamination of the ’221 patent, and to provide my opinions regarding the
`
`
`
`10
`
`

`

`same. The declaration was made by ’221 patent co-inventor Dr. Joseph Bernstein (the
`
`“Bernstein Declaration” or “Bernstein Decl.”) (Ex. 1016).
`
`16. The comments provided below are not an exhaustive statement of the points in
`
`the Request for Reconsideration or in the supporting Bernstein Declaration with
`
`which I disagree. Therefore, the fact that I do not address a particular point
`
`advocated by MIT or Dr. Bernstein should not be understood to indicate agreement
`
`on my part.
`
`17.
`
`In forming my opinions, I have reviewed the original prosecution history of the
`
`’221 patent (Ex. 1004), as well as the ex parte reexamination prosecution history
`
`relating to U.S. Patent No. 6,057,221, including the Request for Reconsideration and
`
`Dr. Bernstein’s Declaration.
`
`18.
`
`I am also familiar with the prior art and the knowledge of one of ordinary skill
`
`in the art at the relevant time and have specifically analyzed Koyou, Wada, Lou and
`
`Billig.
`
`19.
`
`I have also considered the documents identified as Exhibits 1005 through 1041
`
`above.
`
`III. TECHNOLOGY BACKGROUND
`
`20. By way of background, the ’221 patent relates to prior art technology
`
`commonly used in the integrated circuit manufacturing industry. This technology
`
`involves embedding fuses into integrated circuits during the manufacturing process.
`
`
`
`11
`
`

`

`21. As is well-known, these integrated circuits commonly include active elements
`
`such as transistors formed on a silicon substrate, to which electrical connections are
`
`made using a multi-level “interconnect” structure, each level containing electrically-
`
`conducting lines for interconnecting circuit elements, and each level separated by an
`
`electrically insulating layer.
`
`22. The embedded fuses were commonly situated in one of the metal levels present
`
`in a multi-level interconnect structure.
`
`23. Once an integrated circuit device containing such fuses has been fabricated, but
`
`typically before it has been packaged, the device is tested for operability. If defective
`
`circuit components are detected, the embedded fuses can be blown to disconnect the
`
`defective circuits and, optionally, to make alternate connections to redundant circuitry
`
`also embedded in the device.
`
`24. This methodology permits the manufacturer to salvage otherwise inoperative
`
`devices, or chips, and boost overall manufacturing yield.
`
`25.
`
`Selectively blowing embedded laser fuses can also be performed to program
`
`generic logic devices.
`
`26. One common fuse structure used for repair and programming in the prior art
`
`was the laser fuse, sometimes called a “laser fuse-link,” a “laser cut-link” or simply
`
`“fuse-link” or “cut-link.” To “blow” this type of fuse, a conductive element in the
`
`integrated circuit is exposed to a focused laser beam for a length of time and power
`
`level sufficient to evaporate or ablate the element, thereby creating an open circuit.
`
`
`
`12
`
`

`

`IV. THE ’221 PATENT
`
`27. The ’221 patent (Ex. 1003), titled “Laser-Induced Cutting of Metal
`
`Interconnect,” relates to methods for severing connections between electrical circuits
`
`using laser cut-links of a particular form and composition. See, e.g., ’221 patent,
`
`Abstract.
`
`28. The ’221 patent acknowledges that the use of laser cut-links was well-known in
`
`the prior art (see, e.g., ’221 patent, col. 1:10-21) and that laser cut-links were commonly
`
`employed to replace defective circuit components with redundant circuit components
`
`for improved manufacturing yield, and to program logic circuits (’221 patent, col.
`
`1:22-48).
`
`29. According to the ’221 patent, however, prior art cut-links were typically
`
`“undistinguished segment[s]” of a line in the circuit having a uniform width (’221
`
`patent, Fig. 1) or having a “dog bone” shape where the width of the segment being
`
`cut is narrower than the rest of the structure (’221 patent, Fig. 2). ’221 patent, col.
`
`1:49-61.
`
`30. According to the ’221 patent:
`
`Whereas the design of earlier cut-links mirrors the narrowed
`“dog-bone” of conventional fuse design, a preferred embodiment
`of this invention rejects this model and, instead, widens the
`segment where the circuit is to be severed. Where circuitry is cut
`by a laser, the high resistance of a fuse is not required to produce
`the needed influx of thermal energy. In this context, the thermal
`
`
`
`13
`
`

`

`energy needed to melt the conductive material is supplied by an
`external source, i.e., the laser. As the present inventors have
`recognized, the use of the laser frees the designer from the
`necessity of using a high resistance segment to generate the heat
`necessary to cut the circuit. Although intuition might further
`suggest that a fuse-shaped cut-link of thin width could be severed
`with greater precision and efficiency
`than an otherwise
`comparable cut-link of greater width, the present inventors have
`recognized
`that
`this
`notion
`is
`generally
`false.
`
`To the contrary, an electrical interconnect which may be cut with
`greater success and with improved efficiency includes a cut-link
`pad in which the thermal resistance per unit length is lower, rather
`than higher, than the connected lines. In a preferred embodiment,
`the thermal resistance is lowered by adopting a form that is the
`inverse of the traditional “dog bone” design. The form of this
`new design is such that the width of the cut-link pad is
`substantially greater than the width of the lines.
`
`’221 patent, col. 1:64 to 2:21.
`
`31. Though the ’221 patent admits that cut-links were typically “coated with a
`
`passivation layer to protect the circuit from oxidation,” (’221 patent, col. 1:16-18), the
`
`patent describes an embodiment in which a cut-link that lies on a silicon oxide
`
`substrate is covered by a silicon nitride passivation layer that is harder than the silicon
`
`oxide substrate (’221 patent, col. 2:59-67). Silicon nitride is recommended because
`
`
`
`14
`
`

`

`“increasing hardness and brittleness is correlated with increasing susceptibility to
`
`fracture.” ’221 patent, col. 6:26-29.
`
`32.
`
`Figure 3 of the ’221 patent, shown below, depicts an embodiment of the cut-
`
`links described in the ’221 patent, including a cut-link pad 20 connected to conducting
`
`lines 21 and 22.
`
`
`
`33. The laser beam spot is shown as 24 in Figure 3 above.
`
`34.
`
`Figure 10 of the ’221 patent, shown below, depicts another embodiment and
`
`includes a cut-link pad 20 connected to conducting lines, or vias, 21a and 22a
`
`
`
`extending from the bottom of the pad.
`
`
`
`
`
`
`
`15
`
`

`

`
`In Fig. 10 above, the cut-link pad is embodied in a multi-level chip, and, when
`
`35.
`
`standard half-micron silicon process technology is used, the vias are about a half
`
`micron wide and the lines are wider. ’221 patent, col. 8:30-35.
`
`36. The ’221 patent further provides that:
`
`When cutting, the cut-link should ideally be entirely within the
`beam spot as determined above. Absorption across the entire
`surface promotes uniform heating of the pad. An infrared laser
`typically produces beams having a minimum diameter of about
`two microns. Further, the tolerance for beam positioning error is
`typically about 0.2 to 0.5 microns. Accordingly, a pad designed to
`have a preferable length and width of two to three microns can
`absorb the bulk of the energy transmitted by the laser while
`remaining entirely within the beam spot.
`
`’221 patent, col. 5:3-12.
`
`37. The ’221 patent further provides that:
`
`Designing the cut-link pad to approximate the size and shape of
`the laser beam spot also provides an additional benefit. Less
`
`
`
`16
`
`

`

`energy misses the cut-link pad resulting in less energy being
`absorbed into the surrounding dielectric material which reduces
`the likelihood that this surrounding material will be damaged by
`thermal stresses.
`
`’221 patent, col. 6:13-18.
`
`38. According to the ’221 patent, the described embodiments can be more
`
`efficiently ablated for the following reasons:
`
`First, the structures of the present invention retain thermal energy
`at the site of the cut-link more effectively than the cut-links of the
`prior art by restricting dissipative heat transfer from the cut-link
`into the connected lines. Second, the shapes of preferred
`structures produce increased stress at the perimeter of the cut-link
`pad, thereby generating a more forceful fracture of the
`surrounding material. Third, the shapes of preferred structures
`create stress concentration points that will produce fractures
`radiating outwardly from the site of the cut-link pad, thereby
`improving the likelihood that the fracture will be clean, i.e., will
`not create inter-linked fracture passages through which escaping
`metal may form a "short" defeating the attempt to cleanly sever
`the circuit. Fourth, where the cut-link pad more closely
`approximates the size and shape of the laser beam, the cut-link
`absorbs a greater portion of the laser's energy, thereby producing
`a more efficient transfer of energy and a reduced danger of
`damaging the surrounding material. Fifth, where a passivative
`coating comprised of a brittle material is used, the fracture is
`biased toward the passivative coating, and, hence, toward the
`
`
`
`17
`
`

`

`surface of a chip for efficient removal of the passivative coating
`and non-damaging expulsion of the metal comprising the cut-link
`pad. Sixth, by trapping the heat within the confines of the cut-link
`pad and limiting its escape through the connected lines, the site at
`which the cut develops is confined within this narrow region and
`damage to other parts of the circuit is minimized.
`
`’221 patent, col. 3:8-34.
`
`39. The ’221 patent, as reexamined, includes 20 claims. Claims 3, 14, 17 and 26 are
`
`independent, and the rest dependent. All claims are directed toward a method for
`
`cutting a conductive link, which I will sometimes refer to as a “laser fuse,” between
`
`interconnected circuits on a substrate by maintaining a laser beam on a portion of the
`
`link called a “cut-link pad” until sufficient energy is absorbed into the cut-link pad to
`
`sever the conductive link.
`
`40.
`
`Independent claim 14 is directed to performing the method on laser fuses
`
`having a cut-link pad and electrically-conductive lines that lie on a substrate. See, e.g.,
`
`’221 patent, Figure 3 above. Independent claims 3, 17 and 26 are more narrowly
`
`directed to laser fuses having a cut-link pad and electrically-conductive lines that
`
`extend from the pad into the substrate. See, e.g., ’221 patent, Figure 10 above.
`
`
`
`18
`
`

`

`V. UNDERSTANDING OF THE LAW
`
`A. Anticipation
`41.
`I have been informed that, for a claim to be invalid as “anticipated,” every
`
`limitation of the claim must be found in a single prior art reference, either expressly or
`
`inherently.
`
`42.
`
`I have also been informed that patent drawings may only be relied on for
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`showing proportions and dimensions if persons having ordinary skill in the art would
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`understand the specification as providing an indication that the drawings are to scale.
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`B. Obviousness
`43.
`I have also been informed that, where each and every element is not present in
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`a single reference, a claim may still be invalid as “obvious” if the differences between
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`the subject matter sought to be patented and the prior art are such that the subject
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`matter as a whole would have been obvious at the time the invention was made to a
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`person having ordinary skill in the art to which said subject matter pertains. I
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`understand that the following factors must be evaluated to determine whether the
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`claimed subject matter is obvious: (1) the scope and content of the prior art; (2) the
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`difference or differences, if any, between each claim of the patent and the prior art;
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`and (3) the level of ordinary skill in the art at the time the patent was filed.
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`44.
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`I understand that obviousness may be shown by considering more than one
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`item of prior art and by considering the knowledge of a person having ordinary skill in
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`the art and that obviousness may be based on various rationales, including:
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`(A) Combining prior art elements according to known methods to yield
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`predictable results;
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`(B) Simple substitution of one known element for another to obtain predictable
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`results;
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`(C) Use of known techniques to improve similar devices (methods, or
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`products) in the same way;
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`(D) Applying a known technique to a known device (method, or product) ready
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`for improvement to yield predictable results;
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`(E) “Obvious to try” – choosing from a finite number of identified, predictable
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`solutions, with a reasonable expectation of success;
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`(F) Known work in one field of endeavor may prompt variations of it for use
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`in either the same field or a different one based on design incentives or
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`other market forces if the variations are predictable to one of ordinary skill
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`in the art; and
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`(G) Some teaching, suggestion, or motivation in the prior art that would have
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`led one of ordinary skill to modify the prior art reference or to combine
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`prior art reference teachings to arrive at the claimed invention.
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`45.
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`I have also been informed and I understand that so-called “objective indicia” of
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`non-obviousness, also known as “secondary considerations,” like the following are
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`also to be considered when assessing obviousness: (1) commercial success; (2) long-
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`felt but unresolved needs; (3) copying of the invention by others in the field; (4) initial
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`expressions of disbelief by experts in the field; (5) failure of others to solve the
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`problem that the inventor solved; and (6) unexpected results. I also understand that
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`there must be a nexus between the claimed subject matter and the evidence of
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`objective indicia of non-obviousness, and that the evidence of objective indicia of
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`non-obviousness must be commensurate in scope with the claimed subject matter.
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`VI. LEVEL OF ORDINARY SKILL IN THE ART
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`46.
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`I understand that the hypothetical person of ordinary skill in the art is
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`considered to have the normal skills and knowledge of a person in a certain technical
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`field, as of the time of the invention at issue. I understand that factors that may be
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`considered in determining the level of ordinary skill in the art include: (1) the
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`education level of the inventor; (2) the types of problems encountered in the art; (3)
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`the prior art solutions to those problems; (4) rapidity with which innovations are
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`made; (5) the sophistication of the technology; and (6) the education level of active
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`workers in the field. I also understand that “the person of ordinary skill” is a
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`hypothetical person who is presumed to be aware of the universe of available prior
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`art.
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`47.
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`I have determined that a person of ordinary skill in the art with respect to the
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`technology described in the ’221 patent would be a person with a Bachelor of Science
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`degree in electrical engineering, chemical engineering, materials science, chemistry or
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`
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`physics and at least 3-5 years of work experience designing devices and/or fabricating
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`chips, or a person with a Master’s degree in the same areas and at least 2-3 years of the
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`same work experience, or a person with a Ph.D. in the same areas with 1 year of such
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`work experience.
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`48. Based on my experience and education, I consider myself (as of no later than
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`1982, and since) to be a person of at least ordinary skill in the art with respect to the
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`field of technology implicated by the ’221 patent.
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`VII. PATENTABILITY ANALYSIS
`
`A. Claim Construction
`49.
`I have been informed that a claim subject to inter partes review is given its
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`“broadest reasonable construction in light of the specification.” I have been further
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`informed that the words of the claim are to be given their plain meaning in view of
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`the specification as interpreted by one of ordinary skill in the art.
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`50. Consistent with these guidelines, I believe that the terms “cut-link pad” and
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`“cutlink pad”(all claims), “substrate” (all claims) and “harder than the substrate”
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`(claims 14-15 and 29-30) should be construed as follows:
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`Term
`
`Construction
`
`cut-link pad,
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`an electrically-conductive segment of a circuit capable of being
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`cutlink pad
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`ablated in whole or in part when exposed to a laser beam.
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`substrate
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`base structure, including overlying insulating layers
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`harder than the
`substrate
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`harder than the layer of the substrate upon which the cut-link
`pad resides.
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`51. The proper construction of “cut-link pad” and “cutlink pad,” as provided
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`above, is evident from Figures 1-11 of the ’221 patent and from the associated
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`description in the specification, each depicting elements, labeled “20,” which are
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`designed to be removed by laser ablation, and which the patent identifies as “cut-link
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`pads.” See, e.g., ’221 patent at 3:48 to 4:20, 4:36-38; 6:29-31 (“When a laser pulse is
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`incident on the cut-link pad 20, the cut-link pad 20 is heated and expands.”); Figs 1-
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`11.
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`52. With respect to the above construction of the term “substrate,” the ’221 patent
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`consistently defines this term as including overlying insulating layers. See, e.g., ’221
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`patent at 2:22-27 (“The electrical interconnect of this invention includes an insulating
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`substrate upon which a pair of electrically-conductive lines are bonded to a cut-link
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`pad . . .”), 6:45-57 (“Typically, the substrate 34 of a chip includes a silicon wafer base
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`upon which a dielectric material, such as a silicon oxide, is layered.”). The above
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`construction is also consistent with common usage in the industry. See, e.g., The New
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`IEEE Standard Dictionary of Electrical and Electronic Terms (1993) (Ex. 1005) at 1306
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`(“substrate (1) (integrated circuits). The supporting material upon or within which an
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`integrated circuit is fabricated or to which an integrated circuit is attached.”).
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`53. The proper construction of “harder than the substrate,” as provided above, is
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`evident from the specification of the ’221 patent, which consistently uses this term in
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`reference to the layer of the substrate upon which the cut-link pad resides, and not to
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`the base substrate or wafer.