Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`APPENDIX A: ADDITIONAL DISAGREEMENTS WITH MR.
`MCALEXANDER’S DECLARATION
`
`I have read Mr. McAlexander’s declaration dated January 22, 2016. I have issue
`
`(1)
`with many of his assertions. A select few representative issues are addressed below.
`
`Failing to mention a particular passage of his should not be interpreted as silent
`
`agreement on my part. My critique follows his in page order.
`
`A.
`
`Level of Ordinary Skill
`
`In my original Declaration, I discussed the appropriate level of ordinary skill in the
`
`(2)
`art [see par. 26 of Jacob Opening Declaration]. It is my understanding that Mr.
`
`McAlexander adopted my opinion regarding the appropriate level of ordinary skill in the
`
`art. See Exhibit 2014, par. 30.
`
`(3) However, in his Declaration, Mr. McAlexander states that the level of ordinary
`skill that I proposed is “too high […] because the ’734 patent is written in terms that
`
`could be understood and utilized by a person without such extensive
`
`experience” [McAlexander, par. 30] Mr. McAlexander is wrong. The ’734 patent and
`
`related prior art center around DDRx SDRAM memory systems and bidirectional data
`
`strobes. DDRx SDRAMs are the primary memories today that use such data strobes, and
`
`
`
`Page of 1
`
`40
`
`Ex. 1020-0001
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`these strobes are what enable the memory systems to transfer data at their incredibly high
`
`rates. The level of ordinary skill that I proposed accounts for a familiarity with and an
`
`understanding of this sophisticated technology, so that the person of ordinary skill would
`
`appreciate the important strobe-related details of the ’734 patent and the related prior art.
`
`To the extent that Mr. McAlexander’s opinions reflect an erroneous perspective that fails
`
`to take into account the details of the bidirectional data strobes of DDRx SDRAM, his
`
`opinions are incorrect and should be discounted.
`
`B.
`
`Background of the Field Relevant to the ’734 Patent
`
`(4) Mr. McAlexander contends that the strobe signals, whose buffer circuits are the
`focus of the patent, are of a type he calls “door-knocking signals” [McAlexander, par.
`
`31]. These strobes are not “door-knocking” signals. The term “door-knocking signal”
`
`comes from telecommunications, not digital systems design, and it corresponds to an
`
`incoming telephone call, for instance when a line is busy. Using the term to describe
`
`high-speed memory-systems design is not only inappropriate; it is misleading. Timing
`
`strobes used for the capture of data are not described in this manner, as they must be
`
`transmitted and delivered in extremely tight lock-step with the data pulses that they
`
`represent, whereas the telecommunication signal is asynchronous. In addition, the
`
`
`
`Page of 2
`
`40
`
`Ex. 1020-0002
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`behavior that Mr. McAlexander suggests by misnaming the DQS a “door-knocking
`
`signal”—that the signal is meant as an early warning that some event is about to transpire
`
`on the bus—is representative of a type of asynchronous strobe that was used in older
`
`digital systems and is found nowhere in the DDR SDRAM standards.
`
`(5) Mr. McAlexander asserts that the point of the ’734 patent is to build memory
`systems out of physically and electrically incompatible parts. For example:
`
`As the specification explains, in a memory system that uses a data strobe
`buffer according to the teachings of the ‘734 patent, each such device “may
`be any type of semiconductor memory device,” for example DDR or
`MDDR, Ex. 1001, ‘734 patent at 3:57-11, such that, for example, DIMM 0
`and DIMM 1 shown above could be DDR, whereas DIMM 2 could be
`MDDR. As I will further discuss below, the inventive data strobe buffer en-
`ables mixed-type memory systems. [McAlexander, par. 39]
`
`… a single data strobe buffer that could control different types of memory
`devices in a single system would be advantageous. [McAlexander, par. 49]
`
`… because the same data strobe circuit can process a signal from a given in-
`put/output node in multiple manners of operation, different types of memo-
`ries can be connected onto the same signal line. [McAlexander, par. 52]
`
`
`
`Page of 3
`
`40
`
`Ex. 1020-0003
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`(6) Mr. McAlexander’s assertions notwithstanding, the notion that the patent is about
`building incompatible systems is simply untrue. In general, industry tries to avoid
`
`building systems with incompatible parts that all operate differently in the same channel,
`
`and Mr. McAlexander cannot point to any counterexample beyond hypotheticals. In fact,
`
`the DRAM industry spends extra time, power, and silicon area (each of which costs extra
`
`money) to ensure that all DRAMs in a system behave in exactly the same way, even if
`
`some or all of them are capable of acting in incompatible manners. For instance, when
`
`multiple speed grades of DRAM are used in the same system, they all run at the speed of
`
`the slowest DRAM. The DRAM’s mode register and the memory controller ensure this
`
`consistency of behavior, by having every DRAM adhere to the memory controller’s
`
`system-wide guidelines.
`
`Samsung contends that the ’734 patent’s disclosure of “a memory system including
`
`(7)
`a data strobe buffer which can interface with different types of semiconductor memory
`
`devices” necessarily means that such semiconductor memory devices will be
`
`incompatible types all residing in the memory channel together. Despite Samsung’s
`
`assertions, this is not what the ’734 patent discloses. The patent simply instructs how to
`
`choose one signal (e.g., a reference voltage) over another (e.g., a complementary clock
`
`
`
`Page of 4
`
`40
`
`Ex. 1020-0004
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`signal), which would enable a controller to be compatible with a wider range of DRAM
`
`device types.
`
`(8) Mr. McAlexander says the following:
`
`Another such method, as is commonly used in connection with DDR1 de-
`vices, and optionally used with DDR2 devices, is to compare the incoming
`data strobe signal with a data strobe bar signal. See ¶ 44, supra.
`[McAlexander, par. 54]
`
`This statement is incorrect. DDR1 SDRAM does not use a data strobe bar signal,
`
`(9)
`or a differential comparison between the data strobe signal and some hypothetical data
`
`strobe bar. While DDR2 does optionally use a differential signal, DDR1 SDRAM only
`
`uses a single-ended strobe signal.
`
`(10) Mr. McAlexander misrepresents my earlier academic work and uses the
`misrepresentation to support his position. He states, “In the DDR2 standard, differential
`
`signaling is an optional feature; the system designer can determine whether it is necessary
`
`(given the expected noise level) to sacrifice power efficiency by enabling this feature. See
`
`Ex. 2013 (Jacob et al., Memory Systems) § 12.3.4 at 475.” [McAlexander, par. 46] This
`
`misrepresents what is actually written on page 475 of my Memory Systems book. In fact,
`
`
`
`Page of 5
`
`40
`
`Ex. 1020-0005
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`I only state that differential DQS is an optional feature in DDR2; I make no statement at
`
`all concerning “power efficiency” or whether the feature represents a “sacrifice” of any
`
`sort:
`
`Differential Strobes and FBGA Packages

`In addition to dynamic termination control, DDR2 SDRAM device architec-
`ture also contains other features that differentiate it from DDR SDRAM de-
`vice architecture. For example, DDR2 SDRAM devices can optionally sup-
`port a differential DQS signal, while DDR SDRAM devices only support a
`single ended DQS signal. The differential DQS signal enables the DDR2
`SDRAM device to bolster the signal integrity [continues on to page 476] of
`the reference strobe, thus enabling it to operate at higher data rates. [Jacob,
`Ng, and Wang, Memory Systems, Morgan-Kaufmann, 2007]
`
`(11) Further, Mr. McAlexander misstates how the DDR2 SDRAM part actually works.
`
`McAlexander asserts, “If the noise is expected to be low, the system designer can save
`
`power by using only single-ended DQS signals, as well as saving on the chip and board
`
`real estate needed to accommodate the additional pins and to run the additional signal
`
`wires for the DQS# signal.” [McAlexander, par. 46] This assertion has no basis in fact:
`
`one cannot reduce either chip or board “real estate” by eliminating the DQS# signal,
`
`precisely because, as Mr. McAlexander points out, it is optional, and the choice is made
`
`
`
`Page of 6
`
`40
`
`Ex. 1020-0006
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`at system initialization time. The memory controller, at system initialization time, can
`
`choose either single-ended or differential DQS by setting a value in the DRAM’s mode
`
`register. DDR2 SDRAM can perform either type of signaling, because it contains the
`
`circuitry for both modes, and the controller chooses the mode by setting the appropriate
`
`bit in the mode register at run-time. Thus, when one chooses not to use the differential
`
`mode, there is no saving in die area, because the circuitry is already in the chip.
`
`C.
`
`Summary of the ’734 Patent
`
`(12) Mr. McAlexander discusses the drivers of the ’734 patent. He states, “The ’734
`patent also discloses a flexible driver (or transmitter), which allows the data strobe buffer
`
`to operate with a wider range of functionality than previously available, such as adjust
`
`drive strength and increase transmission quality, for example, by reconfiguring the driver
`
`to provide on-die termination during a read operation” [McAlexander, par. 50]. Note
`
`that, while the patent does discuss these issues, none of this is mentioned in any of the
`
`challenged claims.
`
`D.
`
`The “Flexible Receiver” of the ’734 Patent
`
`In paragraph 54, Mr. McAlexander explains his interpretation of the language in
`
`(13)
`Claim 1 (note that inaccuracies in this paragraph were pointed out earlier). He states the
`
`Page of 7
`40
`
`Ex. 1020-0007
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`the receiver “must receive a data strobe signal” and “process it” and, in particular, “must
`
`also be capable of processing the incoming second data strobe signal in two different
`
`ways.” These ways are “by comparing it to a reference voltage” and “by a method that
`
`does not involve comparison to a reference voltage” (emphasis original). Note that, in
`
`McAlexander’s own words, the receiver circuit need only “be capable of” two different
`
`methods of processing—i.e., it is sufficient to have present in the receiver the circuitry
`
`that can process a strobe in two different ways; nothing in the claim requires that both be
`
`used, in the same system, on the same DRAMs. However, in the paragraphs that follow,
`
`McAlexander asserts that Claim 1 must be interpreted, through the “further configured”
`
`language, to mean that both modes must be used within the same system, at different
`
`points in time, while the system is operational [McAlexander, pars. 55–73]. He can point
`
`to no language that supports his interpretation, because none exists. Instead, he merely
`
`asserts, “It is my opinion that” the controller would dynamically switch back and forth
`
`[McAlexander, par. 55].
`
`(14) Mr. McAlexander’s position is that simply being able to perform two different
`strobe-processing operations is not sufficient to meet the limitations of Claim 1 … in his
`
`opinion, not only must a circuit be able to perform two different strobe-processing
`
`
`
`Page of 8
`
`40
`
`Ex. 1020-0008
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`operations, it must necessarily dynamically switch back and forth between the two while
`
`running. He can point to nothing in the claim language or the specification that supports
`
`his interpretation that “configured … further configured” means anything other than
`
`“configured … also configured” or “configured … also designed to.” Mr. McAlexander
`
`does not disagree with the fact that the circuits in both the ’734 patent and in the prior art
`
`are designed to process multiple strobe-signal protocols. He simply states that, to satisfy
`
`the claim language, “it is [his] opinion that” [McAlexander, par. 55] the strobe buffer’s
`
`different processing functions must used at different times, in the same system, on the
`
`same DRAMs. This is the scenario of combining incompatible DRAMs into the same
`
`system and interfacing with each in a manner that is incompatible with the others. As I
`
`have mentioned before, this is not at all disclosed in the ’734 patent.
`
`In paragraphs 58–63, Mr. McAlexander uses the Korean patent application to
`
`(15)
`justify his interpretation, saying it “supports my opinion, and demonstrates that the
`
`patentees invented a data strobe buffer that operates in two modes in a single system, and
`
`thus would dynamically switch between the modes during operation” [McAlexander,
`
`par. 58]. He points to original claim 12, and a section entitled “Means for Solving
`
`Problems,” of the ’734 Korean Priority Application as supporting his opinion
`
`
`
`Page of 9
`
`40
`
`Ex. 1020-0009
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`[McAlexander, pars. 59 and 60]. I disagree. In fact, the ’734 Korean Priority Application
`
`explicitly discloses that the claimed “mode” is a configuration required by the memory-
`
`device type. For example, the ’734 Korean Priority Application states that “the selector
`
`(130) may select the reference voltage (Vref) in response to the mode signal, and the
`
`mode signal is the signal that implies that the type of the semiconductor memory device
`
`(200) is DDR SDRAM” (Korean Application, p. 14, emphasis added). Similarly, the ’734
`
`Korean Priority Application states that “the comparator (120) selects the ground voltage
`
`in response to the mode signal, and the mode signal is the signal that implies that the
`
`type of the semiconductor memory device (200) is MDDR SDRAM” (Korean
`
`Application, p. 15, emphasis added). Thus, according to the ’734 Korean Priority
`
`Application, and contrary to Mr. McAlexander’s assertions, the mode signal is tied to the
`
`memory device: it “implies that the type of the semiconductor memory device is” a
`
`particular value, and therefore the mode of the buffer’s receiving circuit would be a
`
`configuration required by the type of memory device.
`
`(16) Most importantly regarding the Korean application, I disagree with the premise of
`using it at all. This application contains errors and self-contradictions that change the
`
`
`
`Page 10
`
` of
`
`40
`
`Ex. 1020-0010
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`meaning of the patent in non-trivial ways, depending on how each inconsistent statement
`
`is interpreted. I suspect that this is why the application was ultimately abandoned.
`
`(17) Mr. McAlexander states the following:
`
`… it is my understanding that NVIDIA claims that the data strobe buffer of
`claim 1 is static, in that it does not have both modes available to it at once
`and, therefore, cannot dynamically change modes nor access multiple types
`of memory. In my view, this is incorrect, as it would exclude the embodi-
`ment of Figures 3A, 3B, and 4, which demonstrates two modes of processing
`the same received signal. [McAlexander, par. 67]
`
`(18) This is incorrect. As I describe above, Figures 3A and 3B depict the operation of
`the buffer circuit of Figure 4 when it is placed in each of its two different modes; Figures
`
`3A and 3B do not disclose that a buffer circuit implementing these two modes must also
`
`switch between them dynamically. In addition, I believe Mr. McAlexander’s
`
`understanding is incorrect. NVIDIA does not use the non-technical and imprecise word
`
`“available” to describe the circuit behavior. The problem with using the non-technical and
`
`imprecise word “available” can be seen in the following:
`
`[I]t is my opinion that the data strobe buffer receiver claimed by the ’734
`patent must be capable of being “configured . . . in the first mode” and “fur-
`
`Page
`
`
`
`
`
` of 11 40
`
`Ex. 1020-0011
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`ther configured . . . in the second mode” during operation. A data strobe buf-
`fer that does not have both claimed modes available at any given time dur-
`ing operation would not practice the claims of the ’734 patent. [McAlexan-
`der, par. 70, emphasis added]
`
`If by “available” Mr. McAlexander simply means that the data-strobe buffer circuit
`
`(19)
`has the ability to operate in whatever mode it is placed (by virtue of the mode signal, for
`
`example), then all of the buffer circuits concerned operate that way. However, Mr.
`
`McAlexander interprets his own non-technical term “available” to mean that the
`
`controller in which the buffer circuit is found must necessarily switch between both
`
`modes, and do so “during operation.” He is free to interpret his own term as he sees fit, as
`
`the term has no specific connotation within the field of computer design; however,
`
`nothing in the patent specification or claim language supports such an understanding of
`
`the circuit. Mr. McAlexander attempts to justify this interpretation:
`
`As the patent explains, one of its goals is to “provide a memory system in-
`cluding a data strobe buffer which can interface with different types of
`semiconductor memory devices.” [McAlexander, par. 71, emphasis original]
`
`(20) Despite the fact that the patent does not go on to say further, “… in the same
`
`system simultaneously,” Mr. McAlexander reads it as if it does and tries to explain his
`
`
`
`Page 12
`
` of
`
`40
`
`Ex. 1020-0012
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`reasoning: “Nowhere does the ‘734 patent require or even suggest that all the memory
`
`devices be of the same type” [McAlexander, par. 72]. This is a fallacy. Just because a
`
`patent fails to say something explicitly cannot be taken as evidence that it in fact requires
`
`the opposite. Indeed, nowhere does the ’734 patent require or even suggest that one
`
`would put more than one memory device in a system (for example, Figures 1 and 6 show
`
`systems with only one memory device each), and yet using multiple devices is clearly
`
`how manufacturers build systems, both today and when the ’734 patent was written. If
`
`Mr. McAlexander’s logic is to hold, then one cannot interpret the ’734 patent to apply to
`
`memory systems with more than one memory device in them.
`
`(21) At the end of the section, Mr. McAlexander finally agrees that the Lai circuit meets
`the limitations of the ’734 claims: “it is not required to show that a device actually is
`
`configured to use both modes during operation, only that the structure as it exists allows
`
`such configurations to be used” [McAlexander, par. 73, emphasis original]. The buffer
`
`circuits of Lai and the ’734 patent are identical: the two disclose the exact same circuit
`
`and the exact same modes or circuit configurations. Thus, they both “allow” the same
`
`“configurations to be used” in precisely the same manner, and thus Lai meets the claim
`
`language in precisely the same manner as the embodiments of the ’734 patent.
`
`
`
`Page 13
`
` of
`
`40
`
`Ex. 1020-0013
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`E.
`
`The “Flexible Driver” of the ’734 Patent
`
`In this section, pars. 74–79, Mr. McAlexander describes the operation of the
`
`(22)
`drivers and discusses their relationship with on-die termination. What Mr. McAlexander
`
`discusses in this section is not at all reflected in the challenged claims. The claims
`
`mention nothing at all about four different driver states; the claims mention nothing at all
`
`about termination; the claims mention nothing at all about whether the control signals are
`
`“independently configurable” or not. While there are other claims in the patent’s claim set
`
`that do mention termination (e.g., Claims 4, 5, 6, etc.), it is improper to import those
`
`limitations into claims that do not specify termination. Mr. McAlexander is importing
`
`limitations from the specification and other claims into the challenged claims, which is
`
`improper. Mr. McAlexander is quick to assure that this is not, in fact, what he is doing:
`
`To be clear, it is not my opinion that, in order to practice the various driver
`claims of the ’734 patent (such as claims 3, 14, and 15), a device must im-
`plement on-die termination. Rather, it is that the novel and inventive struc-
`ture of the ’734 patent’s driver easily lends itself to such applications as on-
`die termination. However, if a driver does not have the two independently
`configurable control signals that allow for all four states, it is my opinion
`that it does not practice claims 3, 14, and 15 of the ’734 patent.
`[McAlexander, par. 79, emphasis added]
`
`
`
`Page 14
`
` of
`
`40
`
`Ex. 1020-0014
`
`

`
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`(23) Again, to be very clear, the asserted claims mention absolutely nothing at all about
`“states” of the driver, let alone requiring four different ones; the claims mention
`
`absolutely nothing at all about termination, which corresponds to the fourth of Mr.
`
`McAlexander’s “state” limitations; the claims mention absolutely nothing at all about
`
`whether the control signals are “independently configurable” or not. Mr. McAlexander
`
`even says, “it is not my opinion that, in order to practice the various driver claims of the
`
`’734 patent (such as claims 3, 14, and 15), a device must implement on-die termination.”
`
`But then he follows that up with an opinion that any driver failing to implement on-die
`
`termination also fails to practice the driver claims 3, 14, and 15.
`
`F.
`
`Background on Lai
`
`(24) Mr. McAlexander asserts that the circuit for the Lai data-strobe buffer “can operate
`in only one way (mode) in a given memory system; and that mode of operation can never
`
`change” [McAlexander, par. 84]. Although Mr. McAlexander expresses the opinion that
`
`the receiver in Lai is configured to operate in “only one way,” Mr. McAlexander testified
`
`during his deposition that Lai discloses a memory controller with a data-strobe receiver
`
`that can interface with single-ended and differential data strobes [Ex. 1009 at 38:20–24].
`
`Mr. McAlexander’s expressed opinion is countered by his sworn testimony.
`
`
`
`Page 15
`
` of
`
`40
`
`Ex. 1020-0015
`
`

`
`(cid:91)(cid:8)(cid:90)(cid:8)(cid:110)(cid:75)(cid:97)(cid:109)(cid:103)(cid:106)(cid:109)(cid:110)
`(cid:91)(cid:8)(cid:90)(cid:8)(cid:110)(cid:75)(cid:97)(cid:109)(cid:103)(cid:106)(cid:109)(cid:110)
`(cid:45)(cid:43)(cid:55)(cid:22)(cid:1)(cid:13)(cid:21)(cid:20)(cid:1)(cid:13)(cid:23)(cid:20)(cid:55)(cid:26)(cid:20)(cid:55)
`(cid:45)(cid:43)(cid:55)(cid:22)(cid:1)(cid:13)(cid:21)(cid:20)(cid:1)(cid:13)(cid:23)(cid:20)(cid:55)(cid:26)(cid:20)(cid:55)
`Reply Declaration in Support of Inter Partes Review of USP 7,804,734 — Appendix A
`
`(cid:68)(cid:77)(cid:75)(cid:75)(cid:83)(cid:88) (cid:44)(cid:88) (cid:80)(cid:76)(cid:88)(cid:46)(cid:88)
`(cid:56)(cid:81)(cid:82)(cid:23)(cid:88)(cid:30)(cid:46)(cid:2)(cid:88)(cid:32)(cid:26)(cid:26)(cid:41)(cid:88)
`(cid:68)(cid:77)(cid:75)(cid:75)(cid:83)(cid:88) (cid:44)(cid:88) (cid:80)(cid:76)(cid:88)(cid:46)(cid:88)
`(cid:56)(cid:81)(cid:82)(cid:23)(cid:88)(cid:30)(cid:46)(cid:2)(cid:88)(cid:32)(cid:26)(cid:26)(cid:41)(cid:88)
`
`US. Patent
`
`US 7,804,734 B2
`
`(cid:52)(cid:62)(cid:59)(cid:10)(cid:85) (cid:23)(cid:18)(cid:85)
`(cid:52)(cid:62)(cid:59)(cid:10)(cid:85) (cid:23)(cid:18)(cid:85)
`
`(cid:24)(cid:66)(cid:110)
`
`(cid:32)(cid:77)(cid:84)(cid:110)
`
`(cid:32)(cid:77)(cid:84)(cid:110)
`
`(cid:53)(cid:64)(cid:60)(cid:13)(cid:85) (cid:46)(cid:85)(cid:53)(cid:64)(cid:60)(cid:13)(cid:85) (cid:46)(cid:85)
`
`(cid:53)(cid:64)(cid:60)(cid:13)(cid:85) (cid:46)(cid:85)
`
`(cid:65)(cid:84)(cid:41)(cid:57)(cid:110)
`(cid:65)(cid:84)(cid:41)(cid:57)(cid:110)
`(cid:52)(cid:63)(cid:59)(cid:11)(cid:85) (cid:22)(cid:22)(cid:85)
`(cid:52)(cid:63)(cid:59)(cid:11)(cid:85) (cid:22)(cid:22)(cid:85)
`
`(cid:16)(cid:18)
`
`(cid:29)(cid:88)
`
`(cid:16)(cid:18)
`
`(cid:67)(cid:35)(cid:110)
`
`(cid:1)(cid:2)(cid:105)
`
`
`
`(cid:1)(cid:2)(cid:105)(cid:1)(cid:2)(cid:105)
`
`(cid:1)(cid:2)(cid:105)
`(cid:1)(cid:2)(cid:105)
`
`(cid:1)(cid:2)(cid:105)
`
`(cid:1)(cid:2)(cid:105)
`
`(25) Beyond contradicting himself, Mr. McAlexander is simply incorrect. As mentioned
`earlier, the Lai data-strobe buffer uses precisely the same circuit as the ’734 patent
`(cid:101)(cid:110)
`embodiment. The two are compared side-by-side in the figure below. The buffer from the
`(cid:19)(cid:10)(cid:110)(cid:47)(cid:48)(cid:49)(cid:50)(cid:55)
`(cid:46)(cid:42)(cid:27)(cid:28)(cid:55)
`(cid:46)(cid:42)(cid:27)(cid:28)(cid:55)
`(cid:54)(cid:55)(cid:86)(cid:88)(cid:102)(cid:105)(cid:103)(cid:105)(cid:25)(cid:55)(cid:102)(cid:105)
`(cid:1)(cid:2)(cid:105)
`(cid:1)(cid:2)(cid:105)
`(cid:19)(cid:10)(cid:110)(cid:47)(cid:48)(cid:49)(cid:50)(cid:55)
`(cid:19)(cid:10)(cid:110)(cid:47)(cid:48)(cid:49)(cid:50)(cid:55)
`(cid:1)(cid:2)(cid:105)
`(cid:19)(cid:10)(cid:110)(cid:47)(cid:48)(cid:49)(cid:50)(cid:55)
`(cid:34)(cid:79)(cid:85)(cid:110)
`(cid:34)(cid:79)(cid:85)(cid:110)
`’734 patent is shown on the left; the buffer from the Lai patent is shown on the right.
`(cid:53)(cid:64)(cid:60)(cid:13)(cid:85) (cid:46)(cid:85)
`(cid:4) (cid:22)(cid:9)(cid:20)(cid:110)
`(cid:4) (cid:22)(cid:9)(cid:20)(cid:110)
`(cid:19)(cid:19)(cid:10)(cid:110)
`Sep. 28, 2010
`Sheet 8 0f 12
`(cid:53)(cid:64)(cid:60)(cid:13)(cid:85) (cid:46)(cid:85)
`(cid:84)(cid:85)
`(cid:19)(cid:19)(cid:10)(cid:110)
`(cid:19)(cid:19)(cid:10)(cid:110)
`(cid:51)(cid:88)(cid:24)(cid:25)(cid:105)
`FIG. 8A
`(cid:2)(cid:3) (cid:26)(cid:58)(cid:52)(cid:110)
`(cid:67)(cid:35)(cid:110)
`(cid:19)(cid:19)(cid:10)(cid:110)
`(cid:100)(cid:101)(cid:105)(cid:65)(cid:105)(cid:32)(cid:105)(cid:32)(cid:105)(cid:35)(cid:105)
`(cid:24)(cid:66)(cid:110)
`(cid:2)(cid:3) (cid:26)(cid:58)(cid:52)(cid:110)
`(cid:2)(cid:3) (cid:26)(cid:58)(cid:52)(cid:110)
`(cid:2)(cid:3) (cid:26)(cid:58)(cid:52)(cid:110)
`(cid:67)(cid:35)(cid:110)
`(cid:24)(cid:66)(cid:110)
`(cid:87)(cid:105)(cid:53)(cid:9)(cid:105)(cid:9)(cid:105)(cid:26)(cid:27)(cid:28)(cid:105)(cid:35)(cid:105)(cid:33)(cid:105)(cid:21)(cid:105)(cid:101)(cid:105)
`(cid:46)(cid:42)(cid:27)(cid:28)(cid:55)
`(cid:19)(cid:10)(cid:110)(cid:47)(cid:48)(cid:49)(cid:50)(cid:55)
`(cid:24)(cid:66)(cid:110)
`(cid:34)(cid:79)(cid:85)(cid:110)
`(cid:2)(cid:3) (cid:26)(cid:58)(cid:52)(cid:110)
`(cid:13)(cid:9)(cid:9)(cid:21)(cid:110)
`(cid:13)(cid:9)(cid:9)(cid:21)(cid:110)
`
`(cid:46)(cid:42)(cid:27)(cid:28)(cid:55)(cid:46)(cid:42)(cid:27)(cid:28)(cid:55)
`(cid:24)(cid:66)(cid:110)
`(cid:19)(cid:10)(cid:110)(cid:47)(cid:48)(cid:49)(cid:50)(cid:55)
`
`(cid:19)(cid:10)(cid:110)(cid:47)(cid:48)(cid:49)(cid:50)(cid:55)(cid:19)(cid:10)(cid:110)(cid:47)(cid:48)(cid:49)(cid:50)(cid:55)
`(cid:67)(cid:35)(cid:110)
`(cid:24)(cid:66)(cid:110)
`
`(cid:34)(cid:79)(cid:85)(cid:110)(cid:34)(cid:79)(cid:85)(cid:110)
`(cid:2)(cid:3) (cid:26)(cid:58)(cid:52)(cid:110)
`(cid:19)(cid:19)(cid:10)(cid:110)
`I._______H-.M__£Z
`(cid:19)(cid:19)(cid:10)(cid:110)
`(cid:98)(cid:110)(cid:88)(cid:105)
`(cid:32)(cid:77)(cid:84)(cid:110)(cid:44)(cid:110)
`(cid:32)(cid:77)(cid:84)(cid:110)(cid:44)(cid:110)
`(cid:46)(cid:42)(cid:27)(cid:28)(cid:55)
`(cid:46)(cid:42)(cid:27)(cid:28)(cid:55)
`(cid:19)(cid:10)(cid:110)(cid:47)(cid:48)(cid:49)(cid:50)(cid:55)
`(cid:19)(cid:10)(cid:110)(cid:47)(cid:48)(cid:49)(cid:50)(cid:55)
`(cid:19)(cid:19)(cid:10)(cid:110)
`(cid:2)(cid:3) (cid:26)(cid:58)(cid:52)(cid:110)
`(cid:19)(cid:19)(cid:10)(cid:110)
`
`(cid:19)(cid:19)(cid:10)(cid:110)(cid:19)(cid:19)(cid:10)(cid:110)
`(cid:34)(cid:79)(cid:85)(cid:110)
`(cid:53)(cid:64)(cid:60)(cid:13)(cid:85) (cid:46)(cid:85)
`(cid:34)(cid:79)(cid:85)(cid:110)
`(cid:34)(cid:79)(cid:85)(cid:110)
`(cid:4)(cid:19)(cid:20)(cid:105)(cid:51)(cid:105)(cid:92)(cid:105)
`(cid:19)(cid:10)(cid:110)(cid:47)(cid:48)(cid:49)(cid:50)(cid:55)
`
`(cid:3)(cid:64)(cid:105)(cid:51)(cid:105)(cid:71)(cid:105)(cid:64)(cid:105)
`(cid:2)(cid:3) (cid:26)(cid:58)(cid:52)(cid:110)
`
`(cid:2)(cid:3) (cid:26)(cid:58)(cid:52)(cid:110)(cid:2)(cid:3) (cid:26)(cid:58)(cid:52)(cid:110)
`(cid:46)(cid:42)(cid:27)(cid:28)(cid:55)
`(cid:34)(cid:79)(cid:85)(cid:110)
`(cid:19)(cid:10)(cid:110)(cid:47)(cid:48)(cid:49)(cid:50)(cid:55)
`(cid:19)(cid:19)(cid:10)(cid:110)
`(cid:19)(cid:19)(cid:10)(cid:110)
`(cid:54)(cid:88)(cid:64)(cid:105)
`(cid:46)(cid:42)(cid:27)(cid:28)(cid:55)
`(cid:24)(cid:66)(cid:110)
`(cid:2)(cid:3) (cid:26)(cid:58)(cid:52)(cid:110)
`(cid:2)(cid:3) (cid:26)(cid:58)(cid:52)(cid:110)
`(cid:67)(cid:35)(cid:110)
`(cid:24)(cid:66)(cid:110)
`
`(cid:24)(cid:66)(cid:110)(cid:24)(cid:66)(cid:110)
`
`
`(cid:67)(cid:35)(cid:110)(cid:67)(cid:35)(cid:110)
`(26) The Lai data-strobe buffer (right) can operate in two ways, processing the
`(cid:24)(cid:66)(cid:110)
`(cid:24)(cid:66)(cid:110)
`(cid:53)(cid:64)(cid:60)(cid:13)(cid:85) (cid:46)(cid:85)
`(cid:67)(cid:35)(cid:110)
`(cid:67)(cid:35)(cid:110)
`incoming DQS strobe in two different manners. In a given memory system, the memory
`(cid:53)(cid:64)(cid:60)(cid:13)(cid:85) (cid:46)(cid:85)
`
`(cid:53)(cid:64)(cid:60)(cid:13)(cid:85) (cid:46)(cid:85)(cid:53)(cid:64)(cid:60)(cid:13)(cid:85) (cid:46)(cid:85)
`
`(cid:14)(cid:9)(cid:9)(cid:18)(cid:110)
`(cid:14)(cid:9)(cid:9)(cid:18)(cid:110)
`(cid:33)(cid:78)(cid:65)(cid:110)
`(cid:33)(cid:78)(cid:65)(cid:110)
`
`(cid:8)(cid:45)(cid:26)(cid:42)(cid:20)(cid:34)(cid:26)(cid:17)(cid:47)(cid:17)(cid:36)(cid:50)
`(cid:8)(cid:45)(cid:26)(cid:42)(cid:20)(cid:34)(cid:26)(cid:17)(cid:47)(cid:17)(cid:36)(cid:50)
`
`controller will dictate which of those two manners is used. The buffer’s mode of
`(cid:53)(cid:64)(cid:60)(cid:13)(cid:85) (cid:46)(cid:85)
`(cid:53)(cid:64)(cid:60)(cid:13)(cid:85) (cid:46)(cid:85)
`operation will change whenever the mode signal MSEL changes; this much is clear from
`
`the circuit, because the mode signal MSEL controls the Multiplexer circuit, which selects
`
`
`
`Page 16
`
` of
`
`40
`
`(cid:1)(cid:2)(cid:105)
`
`(cid:1)(cid:2)(cid:105)
`
`(cid:16)(cid:18)
`
`(cid:29)(cid:88)
`
`(cid:16)(cid:18)
`
`(cid:101)(cid:110)
`(cid:46)(cid:42)(cid:27)(cid:28)(cid:55)
`(cid:34)(cid:79)(cid:85)(cid:110)
`(cid:54)(cid:55)(cid:86)(cid:88)(cid:102)(cid:105)(cid:103)(cid:105)(cid:25)(cid:55)(cid:102)(cid:105)
`
`(cid:84)(cid:85)
`(cid:51)(cid:88)(cid:24)(cid:25)(cid:105)
`(cid:100)(cid:101)(cid:105)(cid:65)(cid:105)(cid:32)(cid:105)(cid:32)(cid:105)(cid:35)(cid:105)
`(cid:87)(cid:105)(cid:53)(cid:9)(cid:105)(cid:9)(cid:105)(cid:26)(cid:27)(cid:28)(cid:105)(cid:35)(cid:105)(cid:33)(cid:105)(cid:21)(cid:105)(cid:101)(cid:105)
`(cid:67)(cid:35)(cid:110)
`(cid:46)(cid:42)(cid:27)(cid:28)(cid:55)
`(cid:34)(cid:79)(cid:85)(cid:110)
`(cid:98)(cid:110)(cid:88)(cid:105)
`(cid:4)(cid:19)(cid:20)(cid:105)(cid:51)(cid:105)(cid:92)(cid:105)
`(cid:3)(cid:64)(cid:105)(cid:51)(cid:105)(cid:71)(cid:105)(cid:64)(cid:105)
`(cid:54)(cid:88)(cid:64)(cid:105)
`
`(cid:67)(cid:35)(cid:110)
`
`(cid:16)(cid:18)
`
`(cid:29)(cid:88)
`
`(cid:16)(cid:18)
`
`(cid:16)(cid:18)
`
`(cid:29)(cid:88)
`
`(cid:16)(cid:18)
`
`(cid:16)(cid:18)
`
`(cid:16)(cid:18)
`
`
`
`(cid:29)(cid:88)(cid:29)(cid:88)
`
`(cid:101)(cid:110)
`(cid:54)(cid:88)(cid:64)(cid:105)
`(cid:54)(cid:55)(cid:86)(cid:88)(cid:102)(cid:105)(cid:103)(cid:105)(cid:25)(cid:55)(cid:102)(cid:105)
`(cid:3)(cid:64)(cid:105)(cid:51)(cid:105)(cid:71)(cid:105)(cid:64)(cid:105)
`(cid:46)(cid:42)(cid:27)(cid:28)(cid:55)
`(cid:54)(cid:88)(cid:64)(cid:105)
`(cid:4)(cid:19)(cid:20)(cid:105)(cid:51)(cid:105)(cid:92)(cid:105)
`(cid:34)(cid:79)(cid:85)(cid:110)
`(cid:3)(cid:64)(cid:105)(cid:51)(cid:105)(cid:71)(cid:105)(cid:64)(cid:105)
`(cid:98)(cid:110)(cid:88)(cid:105)
`(cid:4)(cid:19)(cid:20)(cid:105)(cid:51)(cid:105)(cid:92)(cid:105)
`(cid:84)(cid:85)
`(cid:51)(cid:88)(cid:24)(cid:25)(cid:105)
`(cid:98)(cid:110)(cid:88)(cid:105)
`(cid:100)(cid:101)(cid:105)(cid:65)(cid:105)(cid:32)(cid:105)(cid:32)(cid:105)(cid:35)(cid:105)
`(cid:101)(cid:110)
`(cid:87)(cid:105)(cid:53)(cid:9)(cid:105)(cid:9)(cid:105)(cid:26)(cid:27)(cid:28)(cid:105)(cid:35)(cid:105)(cid:33)(cid:105)(cid:21)(cid:105)(cid:101)(cid:105)
`
`(cid:101)(cid:110)(cid:101)(cid:110)
`(cid:87)(cid:105)(cid:53)(cid:9)(cid:105)(cid:9)(cid:105)(cid:26)(cid:27)(cid:28)(cid:105)(cid:35)(cid:105)(cid:33)(cid:105)(cid:21)(cid:105)(cid:101)(cid:105)
`(cid:54)(cid:55)(cid:86)(cid:88)(cid:102)(cid:105)(cid:103)(cid:105)(cid:25)(cid:55)(cid:102)(cid:105)
`(cid:87)(cid:10