I ll]t ililll lil llll llll llll lllll lllll llll lllll llll lllll lll llll llll
`us00717387182
`
`(12) United States Patent
`Kong et al.
`
`iro¡ Patent No.: US 7rl73r87l Bz
`1+s; Date of Patent:
`Feb. 6,2007
`
`(54) SEMTCONDUCTOR MEMORY DEVTCE AND
`METHOD OF'OUTPUTTING DÄTA STROBE
`SIGNAL THEREOF
`(75) Inventors: Eun-Youp Kong, Seoul (KR);
`Jun-Young Jeon, Seoul (KR);
`Jae-Ilyeong Lee, Gyeonggi-do (KR)
`(73) Assignee: Samsung Electronics Co., Ltd.,
`Suwon-si (KR)
`( * ) Notice: Subject to any disclaimer, the tenn of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 268 days.
`
`(21) App1. No.: 101392,582
`(22) Filed: Mar. 19, 2003
`(65)
`Prior Publication Data
`US 200310179627 A1 Sep. 25, 2003
`(30)
`Foreign Application Priority Data
`I['{,ar.20,2002 (KR)
`2002-t5117
`(51) Int. Cl.
`GIIC 17/18
`(2006.01)
`GIIC 8/00
`(2006.01)
`(s2) u.s. cr.
`3651225.7; 3651230.03
`(58) Field of Classification Search ........... 365/189.05,
`365/ 230.O8, 233, 52, 230.03, 230.06, 225.7,
`36512W
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`6,388,935 Bl*
`512002 Kawagoeetal. ........ 3651225.7
`
`6,424,590 B1*
`6,498,766 B2*
`6,519,188 82 *
`6,807,108 82 I
`6,8t9,602 B2*
`6,8t9,626 824
`
`712002
`t2/2002
`2/2003
`tol2004
`1v2004
`l/2004
`
`Tanrishi et al. ........ 3651230.09
`Lec et ol. ................... 3651233
`Ryoo et al. ............ 365/189.05
`Maruyma et al. .... 365/189.05
`Seo et al.
`365/189.05
`Oknda et al. ............... 3651233
`
`o\)
`
`x cited by examiner
`P rí m ary E xam íne r-T rong Phan
`(74) Attorney, Agent, or Firm-Marger Johnson &
`McCollom, P.C.
`(s7)
`
`ABSTRACT
`
`A semiconductor memory device is disclosed. The device
`comprises at least one data input/otttput reference signal
`input and output pin and a plurality of integrated circuits,
`each with a data input/output reference signal input and
`output pad connected to the data inpuloutput reference
`signal input and output pin. Each integrated circuit Íìuther
`comprises a data inpuloutput reference signal input and
`outpnt bufler for bufering a data inpuloutput reference
`signal input from the data inpuloutput reference signal input
`and ontput pad when data is input. This buffer also bufers
`an intemally generated data inpuloutput reference signal,
`and outputs the buffered signal when data is output. The
`internally generated data input/output refe¡ence signal out-
`put can be disabled on each integrated circuit in response to
`a control signal, thus allowing a single one ofthe plurality
`of integrated circnits to be selected to generate the reference
`signal.
`
`7 Claims, 5 Drawing Sheets
`
`mnl¡ol
`sirqrit
`
`DQSB
`
`D(¡SB
`
`cor¡toI
`cftcuit
`
`DSO DSr
`
`DSO DSI
`
`DIOB
`
`DI
`DO
`
`DI
`DO
`
`DIOB
`
`EXHIBIT 1012
`MCALEXANDER
`ilta16
`
`Anne Toíêano, CSR 106211
`
`NVIDIA Corp.
`Exhibit 1004
`Page 00'l
`
`Ex. 1012-0001
`
`

`
`U.S. Patent
`
`Feb.6,2oo7 sheet 1 of 5
`
`us 7,173,871 B2
`
`E[G. 1
`(COI\IIúENTIONAL ARf)
`
`DAS
`
`l(xl
`
`I
`rêl
`
`DQsE
`
`DSO DSI
`
`-l?r-2
`
`DQSB
`
`1&2
`
`Þso D.sr
`
`I
`
`l8-1
`
`ÐIOB
`
`DI
`DO
`
`DI
`DO
`
`DIOB
`
`NVIDIA Corp.
`Exhibit 1004
`Page 002
`
`Ex. 1012-0002
`
`

`
`U.S. Patent
`
`Feb.6o 2oo7 sheet 2 o15
`
`us 70173,871B.2
`
`FIG.2
`
`DQS
`
`200
`
`I
`control
`circuit
`
`tz-l
`
`DQSB
`
`I
`
`2L6A
`
`DQSB
`
`L2-2
`
`20-2
`
`control
`cirsuit
`
`DSO DSI
`
`DSO DSI
`
`t3-
`
`14-1
`
`18-t
`
`DIOB
`
`DI
`DO
`
`DI
`DO
`
`LBA
`
`t4-2
`
`DIOB
`
`NVIDIA Corp.
`Exhibit 1004
`Page 003
`
`Ex. 1012-0003
`
`

`
`U.S. Patent
`
`Feb. 6,2007 sheet 3 of 5
`
`us 70173,871B2
`
`F[G.3
`
`2l
`
`32
`_-l_
`I vcc
`
`-1
`
`DSI
`
`P1
`
`N1
`
`20-l
`
`.-\
`
`conüol signal
`getrefatin8
`ci¡cuit
`
`n
`
`coN
`
`Í2
`
`r
`
`-J-l
`
`vcc
`
`Y2.
`
`DQS
`
`DSO
`
`s"r^/ol
`/-4ja.{a
`
`NVIDIA Corp.
`Exhibit 1004
`Page 004
`
`Ex. 1012-0004
`
`

`
`LJ.S. Patent
`
`Feb.6,200T sheet 4 of 5
`E[G.4
`
`us 7,173,87l B2
`
`14
`
`PVCCIT
`
`vcc
`
`TT}
`
`A
`
`N3
`
`N4
`
`F[G.5
`
`vcc
`
`P4
`
`P5
`
`B
`
`¿m
`
`coN
`
`22
`
`/
`
`22
`
`/
`
`I8
`
`coN
`
`NVIDIA Corp.
`Exhibit 1004
`Page 005
`
`Ex. 1012-0005
`
`

`
`U.S. Patent
`
`Feb.6,2oo7 sheet 5 of 5
`H[G.6
`
`us 7,173,87r B2
`
`I
`
`2t6-l
`
`50
`
`52
`
`DQS
`
`_l
`
`NVIDIA Corp.
`Exhibit 1004
`Page 006
`
`P6
`
`N5
`
`vcc
`
`m
`
`N6
`
`t
`
`tL
`
`L
`
`DSI
`
`DSO
`
`Ex. 1012-0006
`
`

`
`us 7,173,871B2
`
`l2
`SEMICONDUCTOR MEMORY DEVICE AND
`110-2. For read operations, buffers 116-1 and 116-2 each
`METHOD OF OUTPUTTING D.ATA STROBE
`receive and bufer output data strobe signal DSO irtemally
`SIGNAL THEREOF
`generated to generate the data strobe signal DQS.
`The input data strobe signals DSI generated by the data
`5 strobe signal input/output buffers 11ó-1 and 116-2 are input
`BACKGROUND OF THE INVENTION
`to the data input/output buffers 18-1 and l8-2 in the i¡rte-
`This application claims the priority of Korean Patent grated circuits ll0-l,ll0-2, respectively. Each data strobe
`Application No. 2002-0015117, filed on Mar. 20,2002, in
`signal DSI is used as a reference signal for captruing the
`the-Korean Intellectual Property Ofice.
`input data DL In the same manner, the output data strobe
`tt
`is used as a rererence signal for capturi'g the
`F'ELD oF THE TNVENTT.N
`:liåîi?:,?
`Data input and output operation of the semiconductor
`The present invention relates to a semiconductor memory nernory device shown in FIG. 1 will be described below.
`device and more particularly to the semiconductor mernory For inputting four-bit or eighfbit data to the semiconduc-
`device comprising at least two integrated circuits in which rs tor menory device 100, the data strobe signal DQS is inpnt
`data is input and output in association with a ¡eference through the data strobe signal input pin L1 and at the same
`(called a data strobe signal) and a method for outputting the dme four bits or eiglrt bits of data DQ are inpttt to the
`data strobe signal out of tlre semiconductor memory device. serniconductorrnenory device via the data input/output pins
`DESCRT'TT.NoFRELATEDART,. lhLi"rttli';lÏi:iiî$::",ri'ffi:i:;;::HíïäË:
`Generarly, a doubre data rate (DDR) synchro,rous semi- lH::tååï,îi'irit#:.iå'itt*î'i"'-iïå:?1iiå;ffiå"1:
`conducto¡ menìory device uses a data strobe signal as a
`be input to the semiconductor rnemory device, thereby
`reference signal to capture input data and output data. generating the input data DL
`Accordingly, the data strobe signal is required to be gener- 25 For oúputting fourbits or eiglrt bits ofdata DQ from the
`ated in tirne for capturing the data.
`serniconductor memory device, a data strobe signal DQS is
`In conventional semiconductor memory devices, one data reqnired to be output from the semiconductor memory
`strobe signal is generated for inputting and outputting four device. Thus, tfte data strobe signal inp¡t/output b¡fers
`bits or eight bits ofdata with one clock cycle to and fron the 11ó-1 and 116-2 in the integrated cicuits 110-1 and 110-2
`semiconductor memory device, so that the conventional :o bnffer, respectively, the o¡tput data strobe signals DSO,
`seniconductor memory device has otte data strobe signal which are i¡ternally generated, thereby generating the data
`pin.
`strobe signals DQS to be outpnt from the semicondtlctor
`Sometirues, the semiconductor rnernory device is fonned mel¡ory device tluo¡gh the data strobe signal i¡puloutput
`by packaging two or rnore DDR synclronous semiconductor pin 11. At the same time, the data inpuloutput bufers 18-1
`mernory devices together. Each DDR syncluonous semicon- ¡s and 18-2 buffer the output data DO read from the integrated
`ductor memory device is refe¡red to he¡einafter as an inte- circ¡its L0-1 and 10-2, thereby generating the data DQ to be
`grated circuit in the same package as a data strobe signal output tluough the data input and output pins 13-1 and 13-2.
`pad.
`Typically, the length ofthe signal line between the data
`FIG. L illustrates a block diagram of a conventional strobesignal padl2-lintheintegratedcircuitll0-1 andthe
`serniconductor memory device 100 comprising ûrst and ¿o data strobe signal pin 11 is different from that between the
`second integrated circuits 110-L and 110-2. The fust and data strobe signal pad l2-2 tn the integrated circuit 110-2
`second integrated circuits include data strobe sigral pads and the data strobe signal pin 11. Further, the data strobe
`l2-l and l2-2, data input and output pads l4-l and l4-2'
`signal DSO intemally generated in the integrated circuit
`data strobe signal input and output bufiers (DQSBs) 116-1 110-1 is not exactly synchronized with the data strobe signal
`and 116-2, and data input and otttput bufers (DIOBs) 1.8-1 +s DSO intemally generated in the integrated circuit 110-2. As
`and 18-2, respectively.
`a result, the relative timing between the data strobe signals
`generated from the integrated circuits 110-1 and 110-2 is
`Thesemiconductormenorydeviceincludesadatastrobe
`signal (DQS) pin 11, which is commonly comected to the
`skewed. Accordingl¡ the data strobe signal DQS uray not be
`data strobe signal pads l2-l and 12-2 fonned in the first and syncfuonized to capture the data in time. That is, when the
`secondintegratedcircuitsll0-1 and110-2,respectively.he 59 data is read out from the conventional semiconductor
`senúconductormemorydevicefurtherincludesapluralityof memory device shown in FIG. 1, even tlìough two data
`data input and output (DQ) pins 13-l and 13-2, connected to
`strobe signals are generated from the two integrated circuits,
`respective data input and output pads 14-1 and 14-2 in the only one data strobe signal may be output frorn the semi-
`integrated circuits tL0-1 and 110-2.
`conductor memory device through the data strobe signal
`For write operations, the data input and output bufers s5 input and output pin 11 at a time. Accordingly, the tirning for
`18-1 and 18-2 generate input data DI to be written into the outputting the data strobe signal may not be syncfuonized
`integrated circuits 110-1 or ll0-2 by buffering dâta DQ that with the timing for outputting the data.
`is externally input respectively through the data input and
`output pins L3-1 and 13-2. For read operations, the data
`input and output buffers 18-1 and 18-2 generate the data DQ oo
`by buffering output data DO read respectively from the
`Inaneforttoovercometheproblemsdescribedabove,in
`integrated circuits L10-1 and 110-2.
`one enbodiment ofthe present invention a setniconductor
`Fãr write operations, the dâta slrobe signal inpuloutput memory device having two, or more than two, integrated
`butrers 1Ló-L and 116-2 each receive and bufier the data circuits in one package, is capable ofeliminating skewing of
`strobe signal DQS extemally input through the extemal data es data strobe signals'
`strobe signal input and output pin 11. to generate input data
`In accordance with one aspect of the present invention,
`strobesignalDslforrespectiveintegratedcircuitsll0-1 and the present embodiments exemplify a semiconductor
`NVIDIA Corp.
`Exhibit 1004
`Page 007
`
`SUMMARY OF THE INVENTION
`
`Ex. 1012-0007
`
`

`
`us 7,173,871B.2
`
`.
`
`DETAILED DESCRIPTION OF PREFFERED
`EMBODIMENTS
`
`34
`menory device comprising at least one data input/output FIG. ó illustrates a circuit diagram of a data strobe signal
`referenòe signal input and output pin, and a plurality of
`input and output bufer in accordance with the present
`integrated circuits, each integrated circuit having a data invention'
`inpulouþut reference signal input and output bufer with a
`selectable output disable capability, each such bufer con- 5
`nected 1o the data inpuloutput reference signal input and
`output pin. In some emboditnents, the selectable output
`disàble;apability is provided by a severable ftise on each
`Reference will now be made in detail to preferred
`integrated circuit that can be severed to disconnect the embodimentsofthepresentinvention,anexampleofwhich
`o,ttpnt buf". ofthe data input/output relèrence signal input i0 is illsstrated in the accompanying drawings.
`and output buffer from the path to the data inpuloutput FIG. 2 il¡lstrates a block diagran of a semiconductor
`reference signal input and outptlt pin. In other embodirnents, menory device 200 in accordancã with an embodiment of
`the selectable output disable capability is provided by a
`the present invention. The semiconductor memory device
`control circuit that can prevent an internally generated data .. ¡u.1i¿es: a first integrated circuit 210-1 and a second inte-
`inpuVoutput reference signal frorn activating the outptlt " qratedcircuit2lg-2feachof whichmaybeasynchronous
`buffer of the data inpuloutput reference signal input and ónnRAU; adatastrobesignalinputandoutputpinll;and
`output bufer.
`data input and output pins 13-1 and 13-2. The first and
`In another aspect of the present invention, integrated second integrated circuits 210-L and 210-2 include data
`circuits for use in a semiconductor melnory device such as .^ strobe signal pads l2-l and l2-2, dara strobe signal input
`just described are described. For instance, such an integrated '" and output bufers 216-l and2l6-2, control circuits 20-1 and
`circuit can comprise an outprìt buffer to bufer an intemally 20-2, dafa input and output pads 14-1 and I4-2, and dala
`generated data input/output reference signal to be outpttt input and output buffers 18-1 and 1.8-2, respectively. The
`when the integrated circuit outputs data, and means fo¡
`data strobe signal input and output pin 11 is electrically and
`.. commonly connected to the data strobe signal input and
`disablingoutputoftheintemallygenerateddatainpuVoutput
`reference signal such that the intemally generated data " outputpads l2-1 andl2-2 inthefustandsecondintegrated
`inpuVoutput reference signal is not outprìt when the inte- circuits 210-1 and 210-2. The data input and output pins
`grated circuit outputs datâ. The disabling neans are exem- 1.3-1 and l3-2 are connected to the data input and output
`plified, e.g., by the selectable output disable capabilities pads 14-1 and'1,4-2, respectively.
`described above.
`30 The control circuits 20-1 and20-2 provided in the semi-
`In yet another aspect of the irvention, the described conductor mernory device shown in FIG. 2 are not present
`embodiments provide methods of outputting, out of the
`intheconventional semiconductormemorydevice shownin
`seniconductor memory device, a data input/output reference FIG. 1.
`signal, e.g., the data strobe signal generated from a DDR
`Functions and operations of each block with like refer-
`RAM. For instance, a method is disclosed for outputting â 3s ence in FIG. L and FlG. 2 are the same.
`data input/output reference signal in a serniconductor Thecontrolcircuits20-1 atd2,-Zcontrolthedatastrobe
`memory device having at least one data input/output refer- ,ig""i;p*";;J output buffers 216-. and 216-2, respec-
`ence inpnt and outpuf pin and a plurality of integrated ;ä),,,îå;y;;oi.oitirrgenablinganddisablingoftheàata
`circuits connected to that pin, the method comprising con- ;ì;;# ;i;;"ï. -
`-"-^"- :'' -:
`*u s.emi9ond.rylo1 memory device 200 generates one data
`trolling the integrated circuits stlch that when the sernicon- on
`ductor memory device is expected to otltput the data inpîl
`output reference signal, only one of the integrated circ'uTts strobe signal D-SQ by controlling the data strobe signal input
`and outplrt bufers 216-1 and 216-2 using the control ci¡cuits
`generates the data inpuloutput reference signal.
`20-l and20-2.
`BRIEF DESCRIPTION OF THE DRAWINGS ^5
`For example, in one configuration, the data strobe signal
`-' generated under the control ofthe cotrtrol circuit 20-1 from
`rhese and other features and advantages of the present ,i1ì?riåj;t;,i:,,iii JHåíffii,:îåt'åt,,'rtl;t;utì#t#å
`::.'":o.^ "'. ;'- -.-
`invention will be readily apparent to those of ordinary skrll
`inrheartuponreviewoithåãeraileddescriptio"tl'"trólåä ." 5#1.',1;tt";'"i:Ï'å:ifåL]"f;Jt.H:tt-ït;ili:
`when taken in conjunction with the accompanying drawingq tt äil;ö:;;;";i].,
`-:'.*.' -." - f^- -'
`DeSB 216_2 from outputting the data
`
`in which like reference nune¡als denote like parts, and ln 'rçrd¡ù uçuulç r¡Àç Parlr) auq ¡¡¡
`strobe signal generated from the second integrated circuit
`which:
`FrG. r. illustrates a brock diagrarn of a conventionar "l;ålî'iìli,il,î3,""'iHlï:r1i1of adatasrrobesignar
`semiconductor memory device;
`FrG. 2 ilustrares a block diagram of a semicondu",", " inili*:iTil *Tåitffi;T¡;ï3i?*ä1]|¿t,t T
`memory device in accordance with the present invention; DeSB 21ó-l comprises a data strobe signal input bufer 32
`FIG. 3 illustrates circuit diagrams ofa data strobe signal and a data strobe signal output bufer 34. Control circuit
`input and output bufer and a control circuit contained in the 20-l comprises a control signal generating circuit 22, invert-
`semiconductor memory device in accordance with the 6s ers I1, 12 and 13, a NOR gate NOR and a NAND gate NA.
`present invention;
`The data strobe signal input buffer 32 comprises a PMOS
`FIG. 4 illustrates a circuit diagram of a control signal transistor Pl and a NMOS transistor Nl. The data strobe
`generating circuit in accordance rith oo" example of the
`signal output bufler 34 comprises a PMOS transistor P2 and
`present invention;
`a NMOS transistor N2.
`FIG. 5 illustrate a circuit diagram of a control signal os The data strobe signal input buffer 32 buffers the exter-
`generating circuit in accordance with another example ofthe nally input data strobe signal DQS to genemte a data strobe
`present inventio¡; and
`input signal DSI as an input to the integrated circuits'
`NVIDIA Corp.
`Exhibit 1004
`Page 008
`
`Ex. 1012-0008
`
`

`
`us 7,173,871B2
`
`56
`Operation of the circuit in FIG. 3 is described be1ow.
`this time, the NMOS transistor N4 is turned on due to the
`úhen a control signal CON outpnt from the control signal logic "high" level outpttt signal ofthe inverter 15, so that the
`generating circuit2l is set to a tòg,ic "high" level and the node A maintains a logic "low" level. Then, when the
`ãata strote output signal DSO haì a logic "high" level, power-up signal PVCCH transitions to a logic'higlr" level,
`5 ihe inverter 14 inverts the logic level of the power-up signal
`operation of the circui in FIG. 3 is as fol-iows:
`The inverter 11 inverts the logic level ofthe control signal and generates a logic "high" level signal. Thus, the PMOS
`CON, thereby generating a signãl of logic "1ow" level. A first
`transistor P3 turns on and the NMOS transistor N3 ttns off,
`.o-priiing the-NOR gate ÑOR and inverter 12 so as to transmit the logic "higlt'' level to node A. The
`gene¡ates u iogi";high' level sìgnal in response to a logic inverters 15 and 16 bufler the logic "high' level signal
`"ir.uit
`:'higli' level aith" duìu stobe output signal DSO. A second 10 transnitted from the node A and generate a control signal of
`circuit comprising the NAND gate NA and inverter 13
`logic "high" level.
`genemtes a iogic;high" level signal in response to a logic With the ftise Fl cnt, when the power-up signal PVCCH
`;¡igh" level ul th" dãtu strobe output signal DSO and the has a logic "low" level, the inverter 14 inverts the logic level
`conìrol signal CON at a logic "high;' level. Trus, the PMOS of the power-up signal PVCCH and geuerates a logic "high"
`transistorÞ2 flims offand the NMOS transistor N2 turns on, 1s 1eve1. Tle PMOS t¡ansistor P3 is truned ofl and the NMOS
`thereby generating a data strobe signal DQS of logic "low"
`transistor N3 is tumed on to ffansmit a logic "low" level to
`level.
`node A. Thus the control signal CON with a logic "low"
`When the control signal CON maintains a logic "high" level is generated by the control signal generating circuit 22'
`level and the data strobé output signal DSO has logic "1ow" When the power-up signal PVCCH transitions to logic
`level, operation of the circuìt in ÈIC. : is as follows: 20 "ligh" level, howeve¡ the inverter 14 inverts the logic level
`The first circuit comprising the NOR gate NOR and the of the power-up signal PVCCH and transmits a logic "low"
`inverter 12 generates a logic ¿low" level signal in response level to P3 and N3, ttming on PMOS transistor P3. At this
`to a logic '1--ow" level at the output of the inverter llãnd a
`time, however, the node A maintains the logic "low" level
`logic "tw" level for the data strõbe otüput signal DSO. The because the ftise F is cut. Accordingly, the control sigual
`second circuit comprising the NAND gate NAND and the 25 CON maintains a logic "low" level with the ftise ctlt.
`inverter 13 generatei a loigic "low" levðl signal in response FIG. 5 illustrates a circuit diagran for the control signal
`to a logic "low" level at the d¿ta strobe output signal DSO. generating circuit in accordance with another example of the
`Then, ihe PMOS trarmistor P2 tums on and tñe NMOS present invention. The control signal generating circuit
`transistor N2 tums off, thereby generating a data strobe comprises a pad 40, two PMOS transistors P4 and P5 and
`signal DQS of logic "high" level.
`30 inverters 17 and I8.
`lurther, when ìhe coirtrol signal CON is set to a logic
`Operation of the circuit in FIG. 5 will be described below'
`"low" level and the data strobe outprü signal DSO has either When the pad 40 is open, the PMOS transistors P4 and P5
`a logic "low" level or a logic "higlr" level, operation of the are tnmed on, thereby transmitting a powe_r supply voltage
`circuit in FIG. 3 is as follõws:
`Vcc to a node B. The inverters 17 and I8 bufer the power
`The inverter I1. i¡verts the logic level ofthe control signal :s supply voltage at node B and generate the control signal
`CON and generates a logic "high" level signal. The first CON with a logic "high" level.
`circuit com-prising the NOR gatè NOR and ihe inverter 12
`When the pad 40 is connected to a ground voltage, the
`generates a^logiJ"high" levãl signal in response to logic node B is pulled to the grottnd voltage. lnverters I7 and I8
`;'l-righ' level on the data strobe output signal DSO. The bufer the ground voltage at node R and generate the control
`secónd circuit comprising the NAND gate NA and the +o signal CON ì¡/ith the logic "low" leve1.
`inverter'I3 generates a logic "low" level iignal in response That is, with the pad 40 being open, control signal CON
`to a logic "Iow" level on ihe control signal CON. Thus, the
`is set to a logic "high" level; with the pad 40 contrected to
`PMOS transistor P2 and the NMOS traÀsistor N2 are tumed ground voltage, control signal CON is set to a logic "low"
`off and the data strobe signal DQS is not generated.
`level'
`Surnmarizing, when the contròl signal CON ir set to a 4s FIG. 6 illustrates a circuit diagram for a data strobe signal
`logic "high" levet, logic "high" level õr a logic "low" level input and outpttt bttffer 216-1. in accordance with another
`foithe dà-ta strobe sig=nal DQS is generated dèpending upon example of the present invention. The data strobe signal
`thelogiclevelofthedatastrobeõutputsignai DSO.When input bttffer 50 comprises a PMOS transistor P6 and a
`the coltrol signal CON is set to logiC'1ow; level, however, NMOS transistorN5, and the data strobe sigrul output bufer
`the data strobé signal DQS is not gènerated regardless of the so 52 comprises a PMOS transistor P7, a NMOS transistor N6,
`data strobe output signal DSO logic level.
`and a fuse F2.
`FIG. 4 ill¡strates ã circuit diagram for the control signal Operation ofthe data strobe signal input and output buffer
`generating circlit 22 shown in FIG. 3. Tle control signal shown in FIG. 6 will be described below.
`leneratin! circtit22 comprises tluee inverters 14, 15 and 16,
`The data strobe signal input buffer 50 buffers the exter-
`ã ptf¡Os transistor P3, two NMOS tuansistors N3 and N4, ss nally input data strobe signal DQS to generate a data strobe
`and a ñrse Fl..
`input signal DSI as an input to the integrated circuits.
`Upon power-up, a power up signal PVCCH rises from a
`When the ftise F2 is intact, the data strobe signal output
`logió "low" levef to á logic "higli' level.
`bufer 52 buffers the internally generated data.strobe output
`the fuse Fl intact, the inverter 14 inverts the logic signal DSO to generate the data strobe signal DQS. When
`-With
`levelof thepower-up signalPVCCH,therebygeneratingan oo the fuse F2 is cut, the data strobe signal DQS is not
`inverted signal. That is initially, when the power-up signal generated'
`PVCCH hai logic "low" level, the inverter generates a logic
`The data strobe signal input and output b_ufe¡ shown in
`"high" level si-gna1. The PMOS transistor Þ3 is tu¡ned off
`FIG. 6 may control enabling and disabling of the data strobe
`and the NMOstransistor N3 is tumed on so as to transmit signal without additional control circtlits 20-l and20-2.
`alogic"low"leveltoanodeA.Theinverters15andl6buffer os As illustrated above, the present.inven_tion provides a
`the ]ogic "low" level signal transmitted via the node A and semiconductor memory device capable of generating and
`g"n"*1" a control signaì CON with a logic "low" level. At
`outputting, from one of several integrated circuits, a data
`NVIDIA Corp.
`Exhibit 1004
`Page 009
`
`Ex. 1012-0009
`
`

`
`us 7,173,871B2
`
`78
`strobe signal wlúle disabling the other data strobe bignals a first pull-down transisto¡ for pulling down the data
`o¡tput frãm the other integrated circuits contained in the
`output reference signal in response to a second drive
`seÁiconductor memory device. This single data strobe sig-
`signal generated by combining the control signal and
`nal is output tfuough the data strobe signal input and output
`the internally generated data inpuVoutpnt reference
`s
`pin of the semiconductor menory device.
`signal.
`Although the description above relates to a semiconductor 3. The semiconductor memory device of claim 2, wherein
`lnemory device containing two integrated circuit in one the control circuit comprises a control signal generating
`package, the present invention is also applicable to a semi- circuit generating the control signal, and a drive signal
`conductor tnemory device having more than two integrated generating means for tuming off the first pull-up transistor
`circuits in the same package.
`l0 and the first pull-dowr transistor by setting the first and
`While the invention has been particularly shown and seconddrivesignalstotumoffthefirstpull-uptransistorand
`described with reference to preferred embodiments thereof, first pull-down transistors in response to a fust state of the
`it will be unde¡stood by those skilled in the art that the control signal, and outputting the internally geuerated data
`foregoing and other changes in fonn and details may be
`output reference signal as the first and second drive signals
`made therein without departing from the spirit and scope of 15 in resporme to a second state of the control signal.
`the invention.
`4. The semiconductor memory device of clain 3, the
`What is claimed is:
`control signal generating circuit comprising:
`1. A semicondttctor rnemory device conprising:
`a first inverter to invert a logic level of a power-,p signal;
`at least one data input/output reference signal input and
`a second pull-'p transistor connected between a po,,¡r'er
`20
`output pin; and
`supply voltagà and a first node to p.ll up the first node
`a plurality of integrated circuits, each integrated circuit
`in'*.porrr" io an o'tput signal oithe fi-rst inverter;
`having a data input/output reference signal input and
`.--- l^-,-^.-,
`a fuse co*ected between the first node and a second
`output bufier with a selectable o'tput disable capai"ii
`ity,iach such bufer comected to the data inpuVoutput
`" .ääO oull_down t¡armistor connected between the
`reference signal irput and output pin, wherein eacll 25 - "-----. '-'l -'
`"
`t""onq llo|",-1"d a ground voltage to pull down the
`snchbuffercomprisesanoutputbufferhavingano.rtiii
`comrecred rhrough a ftrse to the data inp.,vo.,iiii
`::::)1j"d"inresponsetotheoutputsignalofthefirst
`tou:*"tt .. .,
`reference signal-input and output pin, wherein ihe
`second and third inverters connected in series to bnffer the
`selectable output disable capability on each integratä
`circuit has a disable state that depends oo *h"t¡"r"iirË ¡o
`at the second node and generate the
`signal
`,appearing
`fuse is cnt or intact, whereiu the fuses on all but one of
`control signal; and
`the integrated circuits are set to force the disable state
`a third pull-down transistor connected between the second
`node and the ground voltage to pull down the second
`on theiirespective integrated circuits.
`node in response to an output ofthe second inverter'
`2. A semiconductor memõry device comprising:
`at least one data input/outpit reference signal-input and :s 5. The ser¡iconductor rnemory device according to claim
`-
` ,wherein the power-up signal trattsitionslron the first state
`ontptrt pin; and
`a pnàtiÇ oi integrated circuits, each integrated circuit to the second state upon power-up of the semiconductor
`ïa.ri'g'u data iñp't/output reference sigial input ald
`lnemory device, and wherein the first state is a logic low
`outpfibufer with a seleitable o¡tput disãble capability level and the second state is a logic high level.
`in iesponse to a control signal and a control circuit +o 6.Thesemiconductornemorydeviceofclaim3,wherein
`generãting the control signal, each such bnffer con- the control signal generating circuit includes:
`nected to the data input/output reference signal input
`a pad;
`and ontput pin, wherein olt each integrated circuit, the
`one or more p'l1-up transistors connected between a
`data input/output teference signal input and output
`power supply voltage and the pad; and
`buffer comprises an output buffer, wherein the output 4s bufer
`to buffer a signal appearing at the pad and
`buffer buffe¡s an intemally generated data output ref-
`"i."uitry
`ro generare an output disãble cåitrol sig'al.
`erence signal to output it to the data inpuVoutptlt 7. Tñe semicondnctor menÌory device of claim 6,
`,.",-^*- """''.--
`reference signal input and output pin depeuding on a
`stateofthecontrol signal, audwhereintheoutputbufier *":'-"
`on one of the integrated circuits generat", ¿uto ouip,rt ,o
`the second. state of the cont¡ol signal is attained on at least
`one olthe integrated circuits by exlernally floating the
`relerence slgnar.
`pad on that integrated circuit or connecting the pad on
`wherein on each integrated circuit the output bufier
`that integrated circuit to the power supply voltage; and
`includes:
`a fust pull-up tuansistor for pulling up the data output
`the first state of the control signal is attained on at least
`^fust drive sig^nal ss
`one other of the integrated cjrcujts by connecting the
`refe¡-ence iignal in ."rponr" to"a
`generated b! cornbining the control signal and the
`pad on that other integrated circuit to a ground voltage'
`internally generated data inpuloutput reference signal;
`and*****
`
`NVIDIA Corp.
`Exhibit 1004
`Page 010
`
`Ex. 1012-0010
`
`

`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`PATENTNO. :7,173,81182
`APPLICATION NO. : 10/392582
`DATED
`: February 6,2007
`INVENTOR(S) : Eun-Youp Kong et al.
`
`Page 1 of 1
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is
`hereby corrected as shown below:
`
`Column 7,line 50, the words "generates data" should read -- generates a data --;
`Column 7, line 51, the word "signal." should read -- signal, --.
`
`Signed and Sealed this
`
`Second Day of September, 2008
`
`JON W. DUDAS
`Director ofthe [Jnited States Patent and Trcdemark Olfice
`
`NVIDIA Corp.
`Exhibit 1004
`Page 01 1
`
`Ex. 1012-0011