US007173871B2
`
`(12) United States Patent
`Kong et a].
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 7,173,871 B2
`Feb. 6, 2007
`
`(54) SEMICONDUCTOR MEMORY DEVICE AND
`METHOD OF OUTPUTTING DATA STROBE
`
`7/2002 Taruishi et a1. ...... .. 365/23008
`6,424,590 B1 *
`6,498,766 B2 * 12/2002 Lee et a1. ................. .. 365/233
`
`SIGNAL THEREOF
`
`6,519,188 B2* 2/2003 Ryoo et a1. .......... .. 365/18905
`
`(75) Inventors: Eun-Youp Kong Seoul
`Jun_Y0ung Jean: Seoul (KR):
`Jae_Hye0ng Lee’ Gyeonggi_do (KR)
`
`365/189.05
`6,807,108 B2 * 10/2004 Maruyama et a1.
`6,819,602 B2* 11/2004 S60 et a1. ............ .. 365/18905
`6,819,626 B2 * 11/2004 Okuda et a1. ............. .. 365/233
`
`(73) Assignee: Samsung Electronics Co., Ltd.,
`SuWon-si (KR)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U_S_C_ 154(b) by 268 days_
`
`(21) Appl. N0.: 10/392,582
`
`(22) Filed:
`
`Mar. 19, 2003
`
`(65)
`
`Prior Publication Data
`Us 2003/0179627 A1
`Sell 25’ 2003
`
`Foreign Application Priority Data
`(30)
`Mar. 20, 2002 (KR) ............................. .. 2002-15117
`(51) Int‘ Cl‘
`GH C 17/18
`G11 C 8/00
`
`(2006 01)
`(200601)
`'
`(52) U..S. Cl. ....... ...... .., ........... .. 365/225.7; 365/230.03
`(58) Field of Classi?cation Search ......... .. 365/ 189.05,
`365/230'08’ 233’ 52’ 230'03’ 23006’ 225'7’
`_
`_ 365/200
`_
`See apphcanon ?le for Complete Search hlstory'
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`
`* cited by examiner
`_
`_
`Prlmary ExammeriTrong Phal}
`(74) Attorney, Agent, or FzrmiMarger Johnson &
`McCollom, RC.
`
`(57)
`
`ABSTRACT
`
`A semiconductor memory device is disclosed. The device
`comprises at least one data input/output reference signal
`input and output pin and a plurality of integrated circuits,
`each With a data input/output reference signal input and
`out ut ad connected to the data in ut/out ut reference
`siggal 15pm and Output pm Each integrated 51mm further
`comprises a data input/output reference signal input and
`outputbuifer for buifermg a data mput/output reference
`s1gnal mput from the data mput/ output reference s1gnal mput
`and output pad When data is input. This buffer also buifers
`an internally generated data input/Output reference signal’
`and Outputs the buffered Signal When data is Output The
`internally generated data input/output reference signal out
`put can be disabled on each integrated circuit in response to
`a control signal, thus alloWing a single one of the plurality
`of integrated circuits to be selected to generate the reference
`signal.
`
`6,388,935 B1 *
`
`5/2002 Kawagoe et a1. ...... .. 365/225.7
`
`7 Claims, 5 Drawing Sheets
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`NVIDIA Corp.
`Exhibit 1004
`Page 001
`
`

`
`U.S. Patent
`
`Feb. 6, 2007
`
`Sheet 1 0f 5
`
`US 7,173,871 B2
`
`(CONVENTIONAL ART)
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`11
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`NVIDIA Corp.
`Exhibit 1004
`Page 002
`
`

`
`U.S. Patent
`
`Feb. 6, 2007
`
`Sheet 2 of 5
`
`US 7,173,871 B2
`
`FIG. 2
`
`NVIDIA Corp.
`Exhibit 1004
`Page 003
`
`NVIDIA Corp.
`Exhibit 1004
`Page 003
`
`

`
`U.S. Patent
`
`Feb. 6, 2007
`
`Sheet 3 0f 5
`
`US 7,173,871 B2
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`NVIDIA Corp.
`Exhibit 1004
`Page 004
`
`

`
`U.S. Patent
`
`Feb. 6, 2007
`
`Sheet 4 0f 5
`
`US 7,173,871 B2
`
`FIG. 4
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`NVIDIA Corp.
`Exhibit 1004
`Page 005
`
`

`
`U.S. Patent
`
`Feb. 6, 2007
`
`Sheet 5 0f 5
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`US 7,173,871 B2
`
`FIG. 6
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`NVIDIA Corp.
`Exhibit 1004
`Page 006
`
`

`
`US 7,173,871 B2
`
`1
`SEMICONDUCTOR MEMORY DEVICE AND
`METHOD OF OUTPUTTING DATA STROBE
`SIGNAL THEREOF
`
`BACKGROUND OF THE INVENTION
`
`This application claims the priority of Korean Patent
`Application No. 2002-0015117, ?led on Mar. 20, 2002, in
`the Korean Intellectual Property Of?ce.
`
`FIELD OF THE INVENTION
`
`The present invention relates to a semiconductor memory
`device and more particularly to the semiconductor memory
`device comprising at least tWo integrated circuits in Which
`data is input and output in association With a reference
`(called a data strobe signal) and a method for outputting the
`data strobe signal out of the semiconductor memory device.
`
`DESCRIPTION OF RELATED ART
`
`20
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`25
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`2
`110-2. For read operations, buffers 116-1 and 116-2 each
`receive and buffer output data strobe signal DSO internally
`generated to generate the data strobe signal DQS.
`The input data strobe signals DSI generated by the data
`strobe signal input/output buffers 116-1 and 116-2 are input
`to the data input/output buffers 18-1 and 18-2 in the inte
`grated circuits 110-1, 110-2, respectively. Each data strobe
`signal DSI is used as a reference signal for capturing the
`input data DI. In the same manner, the output data strobe
`signal DSO is used as a reference signal for capturing the
`output data DO.
`Data input and output operation of the semiconductor
`memory device shoWn in FIG. 1 Will be described beloW.
`For inputting four-bit or eight-bit data to the semiconduc
`tor memory device 100, the data strobe signal DQS is input
`through the data strobe signal input pin 11 and at the same
`time four bits or eight bits of data DQ are input to the
`semiconductor memory device via the data input/output pins
`13-1 and 13-2. Then, the data strobe signal input/output
`buffers 116-1 and 116-2 buffer the data strobe signal DQS,
`thereby generating the input data strobe signal DSI. The data
`input and output buffers 18-1 and 18-2 buffer the data DQ to
`be input to the semiconductor memory device, thereby
`generating the input data DI.
`For outputting four bits or eight bits of data DQ from the
`semiconductor memory device, a data strobe signal DQS is
`required to be output from the semiconductor memory
`device. Thus, the data strobe signal input/output buffers
`116-1 and 116-2 in the integrated circuits 110-1 and 110-2
`buffer, respectively, the output data strobe signals DSO,
`Which are internally generated, thereby generating the data
`strobe signals DQS to be output from the semiconductor
`memory device through the data strobe signal input/output
`pin 11. At the same time, the data input/output buffers 18-1
`and 18-2 buffer the output data DO read from the integrated
`circuits 10-1 and 10-2, thereby generating the data DQ to be
`output through the data input and output pins 13-1 and 13-2.
`Typically, the length of the signal line betWeen the data
`strobe signal pad 12-1 in the integrated circuit 110-1 and the
`data strobe signal pin 11 is different from that betWeen the
`data strobe signal pad 12-2 in the integrated circuit 110-2
`and the data strobe signal pin 11. Further, the data strobe
`signal DSO internally generated in the integrated circuit
`110-1 is not exactly synchronized With the data strobe signal
`DSO internally generated in the integrated circuit 110-2. As
`a result, the relative timing betWeen the data strobe signals
`generated from the integrated circuits 110-1 and 110-2 is
`skeWed. Accordingly, the data strobe signal DQS may not be
`synchroniZed to capture the data in time. That is, When the
`data is read out from the conventional semiconductor
`memory device shoWn in FIG. 1, even though tWo data
`strobe signals are generated from the tWo integrated circuits,
`only one data strobe signal may be output from the semi
`conductor memory device through the data strobe signal
`input and output pin 11 at a time. Accordingly, the timing for
`outputting the data strobe signal may not be synchroniZed
`With the timing for outputting the data.
`
`Generally, a double data rate (DDR) synchronous semi
`conductor memory device uses a data strobe signal as a
`reference signal to capture input data and output data.
`Accordingly, the data strobe signal is required to be gener
`ated in time for capturing the data.
`In conventional semiconductor memory devices, one data
`strobe signal is generated for inputting and outputting four
`bits or eight bits of data With one clock cycle to and from the
`semiconductor memory device, so that the conventional
`semiconductor memory device has one data strobe signal
`prn.
`Sometimes, the semiconductor memory device is formed
`by packaging tWo or more DDR synchronous semiconductor
`memory devices together. Each DDR synchronous semicon
`ductor memory device is referred to hereinafter as an inte
`grated circuit in the same package as a data strobe signal
`pad.
`FIG. 1 illustrates a block diagram of a conventional
`semiconductor memory device 100 comprising ?rst and
`second integrated circuits 110-1 and 110-2. The ?rst and
`second integrated circuits include data strobe signal pads
`12-1 and 12-2, data input and output pads 14-1 and 14-2,
`data strobe signal input and output buffers (DQSBs) 116-1
`and 116-2, and data input and output buffers (DIOBs) 18-1
`and 18-2, respectively.
`The semiconductor memory device includes a data strobe
`signal (DQS) pin 11, Which is commonly connected to the
`data strobe signal pads 12-1 and 12-2 formed in the ?rst and
`second integrated circuits 110-1 and 110-2, respectively. The
`semiconductor memory device further includes a plurality of
`data input and output (DQ) pins 13-1 and 13-2, connected to
`respective data input and output pads 14-1 and 14-2 in the
`integrated circuits 110-1 and 110-2.
`For Write operations, the data input and output buffers
`18-1 and 18-2 generate input data DI to be Written into the
`integrated circuits 110-1 or 110-2 by buffering data DQ that
`is externally input respectively through the data input and
`output pins 13-1 and 13-2. For read operations, the data
`input and output buffers 18-1 and 18-2 generate the data DQ
`by buffering output data DO read respectively from the
`integrated circuits 110-1 and 110-2.
`For Write operations, the data strobe signal input/output
`buffers 116-1 and 116-2 each receive and buffer the data
`strobe signal DQS externally input through the external data
`strobe signal input and output pin 11 to generate input data
`strobe signal DSI for respective integrated circuits 110-1 and
`
`40
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`SUMMARY OF THE INVENTION
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`60
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`In an effort to overcome the problems described above, in
`one embodiment of the present invention a semiconductor
`memory device having tWo, or more than tWo, integrated
`circuits in one package, is capable of eliminating skeWing of
`data strobe signals.
`In accordance With one aspect of the present invention,
`the present embodiments exemplify a semiconductor
`
`NVIDIA Corp.
`Exhibit 1004
`Page 007
`
`

`
`US 7,173,871 B2
`
`3
`memory device comprising at least one data input/output
`reference signal input and output pin, and a plurality of
`integrated circuits, each integrated circuit having a data
`input/output reference signal input and output buffer With a
`selectable output disable capability, each such buffer con
`nected to the data input/output reference signal input and
`output pin. In some embodiments, the selectable output
`disable capability is provided by a severable fuse on each
`integrated circuit that can be severed to disconnect the
`output buffer of the data input/output reference signal input
`and output buffer from the path to the data input/output
`reference signal input and output pin. In other embodiments,
`the selectable output disable capability is provided by a
`control circuit that can prevent an internally generated data
`input/output reference signal from activating the output
`buffer of the data input/output reference signal input and
`output buffer.
`In another aspect of the present invention, integrated
`circuits for use in a semiconductor memory device such as
`just described are described. For instance, such an integrated
`circuit can comprise an output buffer to buffer an internally
`generated data input/output reference signal to be output
`When the integrated circuit outputs data, and means for
`disabling output of the internally generated data input/ output
`reference signal such that the internally generated data
`input/output reference signal is not output When the inte
`grated circuit outputs data. The disabling means are exem
`pli?ed, e.g., by the selectable output disable capabilities
`described above.
`In yet another aspect of the invention, the described
`embodiments provide methods of outputting, out of the
`semiconductor memory device, a data input/ output reference
`signal, e.g., the data strobe signal generated from a DDR
`RAM. For instance, a method is disclosed for outputting a
`data input/output reference signal in a semiconductor
`memory device having at least one data input/output refer
`ence input and output pin and a plurality of integrated
`circuits connected to that pin, the method comprising con
`trolling the integrated circuits such that When the semicon
`ductor memory device is expected to output the data input/
`output reference signal, only one of the integrated circuits
`generates the data input/output reference signal.
`
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`BRIEF DESCRIPTION OF THE DRAWINGS
`
`These and other features and advantages of the present
`invention Will be readily apparent to those of ordinary skill
`in the art upon revieW of the detailed description that folloWs
`When taken in conjunction With the accompanying draWings,
`in Which like reference numerals denote like parts, and in
`Which:
`FIG. 1 illustrates a block diagram of a conventional
`semiconductor memory device;
`FIG. 2 illustrates a block diagram of a semiconductor
`memory device in accordance With the present invention;
`FIG. 3 illustrates circuit diagrams of a data strobe signal
`input and output buffer and a control circuit contained in the
`semiconductor memory device in accordance With the
`present invention;
`FIG. 4 illustrates a circuit diagram of a control signal
`generating circuit in accordance With one example of the
`present invention;
`FIG. 5 illustrate a circuit diagram of a control signal
`generating circuit in accordance With another example of the
`present invention; and
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`4
`FIG. 6 illustrates a circuit diagram of a data strobe signal
`input and output buffer in accordance With the present
`invention.
`
`DETAILED DESCRIPTION OF PREFFERED
`EMBODIMENTS
`
`Reference Will noW be made in detail to preferred
`embodiments of the present invention, an example of Which
`is illustrated in the accompanying draWings.
`FIG. 2 illustrates a block diagram of a semiconductor
`memory device 200 in accordance With an embodiment of
`the present invention. The semiconductor memory device
`includes: a ?rst integrated circuit 210-1 and a second inte
`grated circuit 210-2, each of Which may be a synchronous
`DDR RAM; a data strobe signal input and output pin 11; and
`data input and output pins 13-1 and 13-2. The ?rst and
`second integrated circuits 210-1 and 210-2 include data
`strobe signal pads 12-1 and 12-2, data strobe signal input
`and output buffers 216-1 and 216-2, control circuits 20-1 and
`20-2, data input and output pads 14-1 and 14-2, and data
`input and output buffers 18-1 and 18-2, respectively. The
`data strobe signal input and output pin 11 is electrically and
`commonly connected to the data strobe signal input and
`output pads 12-1 and 12-2 in the ?rst and second integrated
`circuits 210-1 and 210-2. The data input and output pins
`13-1 and 13-2 are connected to the data input and output
`pads 14-1 and 14-2, respectively.
`The control circuits 20-1 and 20-2 provided in the semi
`conductor memory device shoWn in FIG. 2 are not present
`in the conventional semiconductor memory device shoWn in
`FIG. 1.
`Functions and operations of each block With like refer
`ence in FIG. 1 and FIG. 2 are the same.
`The control circuits 20-1 and 20-2 control the data strobe
`signal input and output buffers 216-1 and 216-2, respec
`tively, thereby controlling enabling and disabling of the data
`strobe signals.
`Semiconductor memory device 200 generates one data
`strobe signal DSQ by controlling the data strobe signal input
`and output buffers 216-1 and 216-2 using the control circuits
`20-1 and 20-2.
`For example, in one con?guration, the data strobe signal
`generated under the control of the control circuit 20-1 from
`DQSB 216-1, in ?rst integrated circuit 210-1, is output
`through the data strobe signal input and output pad 12-1 and
`the data strobe signal input and output pin 11 out of the
`semiconductor memory device. At the same time, control
`circuit 20-2 prevents DQSB 216-2 from outputting the data
`strobe signal generated from the second integrated circuit
`210-2 to input and output pad 12-2.
`FIG. 3 illustrates circuit diagrams of a data strobe signal
`input and output buffer 216-1 and a control circuit 20-1 in
`accordance With an embodiment of the present invention.
`DQSB 216-1 comprises a data strobe signal input buffer 32
`and a data strobe signal output buffer 34. Control circuit
`20-1 comprises a control signal generating circuit 22, invert
`ers I1, I2 and I3, a NOR gate NOR and a NAND gate NA.
`The data strobe signal input buffer 32 comprises a PMOS
`transistor P1 and a NMOS transistor N1. The data strobe
`signal output buffer 34 comprises a PMOS transistor P2 and
`a NMOS transistor N2.
`The data strobe signal input buffer 32 buffers the exter
`nally input data strobe signal DQS to generate a data strobe
`input signal DSI as an input to the integrated circuits.
`
`NVIDIA Corp.
`Exhibit 1004
`Page 008
`
`

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`US 7,173,871 B2
`
`5
`Operation of the circuit in FIG. 3 is described below.
`When a control signal CON output from the control signal
`generating circuit 22 is set to a logic “high” level and the
`data strobe output signal DSO has a logic “high” level,
`operation of the circuit in FIG. 3 is as folloWs:
`The inverter 11 inverts the logic level of the control signal
`CON, thereby generating a signal of logic “loW” level. A?rst
`circuit comprising the NOR gate NOR and inverter 12
`generates a logic “high” level signal in response to a logic
`“high” level at the data strobe output signal DSO. A second
`circuit comprising the NAND gate NA and inverter 13
`generates a logic “high” level signal in response to a logic
`“high” level at the data strobe output signal DSO and the
`control signal CON at a logic “high” level. Thus, the PMOS
`transistor P2 turns oif and the NMOS transistor N2 turns on,
`thereby generating a data strobe signal DQS of logic “loW”
`level.
`When the control signal CON maintains a logic “high”
`level and the data strobe output signal DSO has logic “loW”
`level, operation of the circuit in FIG. 3 is as folloWs:
`The ?rst circuit comprising the NOR gate NOR and the
`inverter 12 generates a logic “loW” level signal in response
`to a logic “loW” level at the output of the inverter 11 and a
`logic “loW” level for the data strobe output signal DSO. The
`second circuit comprising the NAND gate NAND and the
`inverter 13 generates a logic “loW” level signal in response
`to a logic “loW” level at the data strobe output signal DSO.
`Then, the PMOS transistor P2 turns on and the NMOS
`transistor N2 turns off, thereby generating a data strobe
`signal DQS of logic “high” level.
`Further, When the control signal CON is set to a logic
`“loW” level and the data strobe output signal DSO has either
`a logic “loW” level or a logic “high” level, operation of the
`circuit in FIG. 3 is as folloWs:
`The inverter 11 inverts the logic level of the control signal
`CON and generates a logic “high” level signal. The ?rst
`circuit comprising the NOR gate NOR and the inverter 12
`generates a logic “high” level signal in response to logic
`“high” level on the data strobe output signal DSO. The
`second circuit comprising the NAND gate NA and the
`inverter 13 generates a logic “loW” level signal in response
`to a logic “loW” level on the control signal CON. Thus, the
`PMOS transistor P2 and the NMOS transistor N2 are turned
`oif and the data strobe signal DQS is not generated.
`Summarizing, When the control signal CON is set to a
`logic “high” level, logic “high” level or a logic “loW” level
`for the data strobe signal DQS is generated depending upon
`the logic level of the data strobe output signal DSO. When
`the control signal CON is set to logic “loW” level, hoWever,
`the data strobe signal DQS is not generated regardless of the
`data strobe output signal DSO logic level.
`FIG. 4 illustrates a circuit diagram for the control signal
`generating circuit 22 shoWn in FIG. 3. The control signal
`generating circuit 22 comprises three inverters l4, l5 and 16,
`a PMOS transistor P3, tWo NMOS transistors N3 and N4,
`and a fuse F1.
`Upon poWer-up, a poWer up signal PVCCH rises from a
`logic “loW” level to a logic “high” level.
`With the fuse F1 intact, the inverter 14 inverts the logic
`level of the poWer-up signal PVCCH, thereby generating an
`inverted signal. That is initially, When the poWer-up signal
`PVCCH has logic “loW” level, the inverter generates a logic
`“high” level signal. The PMOS transistor P3 is turned oif
`and the NMOS transistor N3 is turned on so as to transmit
`a logic “loW” level to a node A. The inverters l5 and I6 bulfer
`the logic “loW” level signal transmitted via the node A and
`generate a control signal CON With a logic “loW” level. At
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`this time, the NMOS transistor N4 is turned on due to the
`logic “high” level output signal of the inverter 15, so that the
`node A maintains a logic “loW” level. Then, When the
`poWer-up signal PVCCH transitions to a logic “high” level,
`the inverter 14 inverts the logic level of the poWer-up signal
`and generates a logic “high” level signal. Thus, the PMOS
`transistor P3 turns on and the NMOS transistor N3 turns olf,
`so as to transmit the logic “high” level to node A. The
`inverters l5 and I6 buffer the logic “high” level signal
`transmitted from the node A and generate a control signal of
`logic “high” level.
`With the fuse F1 cut, When the poWer-up signal PVCCH
`has a logic “loW” level, the inverter 14 inverts the logic level
`of the poWer-up signal PVCCH and generates a logic “high”
`level. The PMOS transistor P3 is turned olf and the NMOS
`transistor N3 is turned on to transmit a logic “loW” level to
`node A. Thus the control signal CON With a logic “loW”
`level is generated by the control signal generating circuit 22.
`When the poWer-up signal PVCCH transitions to logic
`“high” level, hoWever, the inverter 14 inverts the logic level
`of the poWer-up signal PVCCH and transmits a logic “loW”
`level to P3 and N3, turning on PMOS transistor P3. At this
`time, hoWever, the node A maintains the logic “loW” level
`because the fuse F is cut. Accordingly, the control signal
`CON maintains a logic “loW” level With the fuse cut.
`FIG. 5 illustrates a circuit diagram for the control signal
`generating circuit in accordance With another example of the
`present invention. The control signal generating circuit
`comprises a pad 40, tWo PMOS transistors P4 and P5 and
`inverters l7 and 18.
`Operation of the circuit in FIG. 5 Will be described beloW.
`When the pad 40 is open, the PMOS transistors P4 and P5
`are turned on, thereby transmitting a poWer supply voltage
`Vcc to a node B. The inverters l7 and I8 bulfer the poWer
`supply voltage at node B and generate the control signal
`CON With a logic “high” level.
`When the pad 40 is connected to a ground voltage, the
`node B is pulled to the ground voltage. Inverters l7 and I8
`bulfer the ground voltage at node B and generate the control
`signal CON With the logic “loW” level.
`That is, With the pad 40 being open, control signal CON
`is set to a logic “high” level; With the pad 40 connected to
`ground voltage, control signal CON is set to a logic “loW”
`level.
`FIG. 6 illustrates a circuit diagram for a data strobe signal
`input and output bulfer 216-1 in accordance With another
`example of the present invention. The data strobe signal
`input bulfer 50 comprises a PMOS transistor P6 and a
`NMOS transistor N5, and the data strobe signal output bulfer
`52 comprises a PMOS transistor P7, a NMOS transistor N6,
`and a fuse F2.
`Operation of the data strobe signal input and output bulfer
`shoWn in FIG. 6 Will be described beloW.
`The data strobe signal input bulfer 50 bulfers the exter
`nally input data strobe signal DQS to generate a data strobe
`input signal DSI as an input to the integrated circuits.
`When the fuse F2 is intact, the data strobe signal output
`bulfer 52 bulfers the internally generated data strobe output
`signal DSO to generate the data strobe signal DQS. When
`the fuse F2 is cut, the data strobe signal DQS is not
`generated.
`The data strobe signal input and output bulfer shoWn in
`FIG. 6 may control enabling and disabling of the data strobe
`signal Without additional control circuits 20-1 and 20-2.
`As illustrated above, the present invention provides a
`semiconductor memory device capable of generating and
`outputting, from one of several integrated circuits, a data
`
`NVIDIA Corp.
`Exhibit 1004
`Page 009
`
`

`
`US 7,173,871 B2
`
`7
`strobe signal While disabling the other data strobe signals
`output from the other integrated circuits contained in the
`semiconductor memory device. This single data strobe sig
`nal is output through the data strobe signal input and output
`pin of the semiconductor memory device.
`Although the description above relates to a semiconductor
`memory device containing tWo integrated circuit in one
`package, the present invention is also applicable to a semi
`conductor memory device having more than tWo integrated
`circuits in the same package.
`While the invention has been particularly shoWn and
`described With reference to preferred embodiments thereof,
`it Will be understood by those skilled in the art that the
`foregoing and other changes in form and details may be
`made therein Without departing from the spirit and scope of
`the invention.
`What is claimed is:
`1. A semiconductor memory device comprising:
`at least one data input/output reference signal input and
`output pin; and
`a plurality of integrated circuits, each integrated circuit
`having a data input/output reference signal input and
`output buffer With a selectable output disable capabil
`ity, each such buffer connected to the data input/ output
`reference signal input and output pin, Wherein each
`such buffer comprises an output buffer having an output
`connected through a fuse to the data input/output
`reference signal input and output pin, Wherein the
`selectable output disable capability on each integrated
`circuit has a disable state that depends on Whether the
`fuse is cut or intact, Wherein the fuses on all but one of
`the integrated circuits are set to force the disable state
`on their respective integrated circuits.
`2. A semiconductor memory device comprising:
`at least one data input/output reference signal input and
`output pin; and
`a plurality of integrated circuits, each integrated circuit
`having a data input/output reference signal input and
`output buffer With a selectable output disable capability
`in response to a control signal and a control circuit
`generating the control signal, each such buffer con
`nected to the data input/output reference signal input
`and output pin, Wherein on each integrated circuit, the
`data input/output reference signal input and output
`buffer comprises an output buffer, Wherein the output
`buffer buffers an internally generated data output ref
`erence signal to output it to the data input/output
`reference signal input and output pin depending on a
`state of the control signal, and Wherein the output buffer
`on one of the integrated circuits generates data output
`reference signal.
`Wherein on each integrated circuit the output buffer
`includes:
`a ?rst pull-up transistor for pulling up the data output
`reference signal in response to a ?rst drive signal
`generated by combining the control signal and the
`internally generated data input/ output reference signal;
`and
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`8
`a ?rst pull-doWn transistor for pulling doWn the data
`output reference signal in response to a second drive
`signal generated by combining the control signal and
`the internally generated data input/ output reference
`signal.
`3. The semiconductor memory device of claim 2, Wherein
`the control circuit comprises a control signal generating
`circuit generating the control signal, and a drive signal
`generating means for turning off the ?rst pull-up transistor
`and the ?rst pull-doWn transistor by setting the ?rst and
`second drive signals to turn off the ?rst pull-up transistor and
`?rst pull-doWn transistors in response to a ?rst state of the
`control signal, and outputting the internally generated data
`output reference signal as the ?rst and second drive signals
`in response to a second state of the control signal.
`4. The semiconductor memory device of claim 3, the
`control signal generating circuit comprising:
`a ?rst inverter to invert a logic level of a poWer-up signal;
`a second pull-up transistor connected betWeen a poWer
`supply voltage and a ?rst node to pull up the ?rst node
`in response to an output signal of the ?rst inverter;
`a fuse connected betWeen the ?rst node and a second
`node;
`a second pull-doWn transistor connected betWeen the
`second node and a ground voltage to pull doWn the
`second node in response to the output signal of the ?rst
`inverter;
`second and third inverters connected in series to buffer the
`signal appearing at the second node and generate the
`control signal; and
`a third pull-doWn transistor connected betWeen the second
`node and the ground voltage to pull doWn the second
`node in response to an output of the second inverter.
`5. The semiconductor memory device according to claim
`4, Wherein the poWer-up signal transitions from the ?rst state
`to the second state upon poWer-up of the semiconductor
`memory device, and Wherein the ?rst state is a logic loW
`level and the second state is a logic high level.
`6. The semiconductor memory device of claim 3, Wherein
`the control signal generating circuit includes:
`a pad;
`one or more pull-up transistors connected betWeen a
`poWer supply voltage and the pad; and
`buffer circuitry to buffer a signal appearing at the pad and
`to generate an output disable control signal.
`7. The semiconductor memory device of claim 6,
`Wherein:
`the second state of the control signal is attained on at least
`one of the integrated circuits by externally ?oating the
`pad on that integrated circuit or connecting the pad on
`that integrated circuit to the poWer supply voltage; and
`the ?rst state of the control signal is attained on at least
`one other of the integrated circuits by connecting the
`pad on that other integrated circuit to a ground voltage.
`
`NVIDIA Corp.
`Exhibit 1004
`Page 010
`
`

`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`: 7,173,871 B2
`PATENT NO.
`APPLICATION NO. : 10/392582
`DATED
`: February 6, 2007
`INVENTOR(S)
`: Eun-Youp Kong et a1.
`
`Page 1 of 1
`
`It is certified that error appears in the above-identi?ed patent and that said Letters Patent is
`hereby corrected as shown below:
`
`Column 7, line 50, the Words “generates data” should read -- generates a data --;
`Column 7, line 51, the Word “signal.” should read -- signal, --.
`
`Signed and Sealed this
`
`Second Day of September, 2008
`
`“W511,
`
`JON W. DUDAS
`Director afthe United States Patent and Trademark O?ice
`
`NVIDIA Corp.
`Exhibit 1004
`Page 011