US007032092B2
`
`(12) Ulllted States Patent
`Lai
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 7,032,092 B2
`Apr. 18, 2006
`
`(54) MEMORY CONTROLLER FOR
`SUPPORTING A PLURALITY 0E
`DIFFERENT MEMORY ACCESSE MODES
`
`(75) Inventor: Jiin Lai, Hsin-Tien (TW)
`_
`_
`_
`_
`(73) Ass1gnee: VIA Technologies, Inc., Ta1pe1 Hs1en
`(TW)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`Pawnt is extended Or adjusted under 35
`U-S-C- 154(1)) by 433 days-
`
`(21) Appl. N0.: 10/236,794
`
`(22) Filed:
`
`Sep. 6, 2002
`
`(52) US. Cl. ...................... .. 711/167;345/534;345/563
`(58) Field Of Classi?cation Search .............. .. 711/105,
`711/154, 167; 713/501, 502; 345/533, 534,
`345/563; 365/233, 194, 189.02, 230.02,
`365/23()_()3
`See application ?le for complete search history.
`
`(56)
`
`References Cited
`
`U-S~ PATENT DOCUMENTS
`4,523,309 A *
`6/1985 Piasecki et a1. ........... .. 370/286
`6,091,663 A *
`7/2000 Kim 6161. .......... ..
`365/233
`6,611,905 B1* 8/2003 Grundon et a1. .......... .. 711/167
`6,625,702 Bl* 9/2003 Rentschler et a1. ....... .. 711/154
`6,681,301 B1* 1/2004 Mehta et a1. ............. .. 711/154
`_
`_
`* c1ted by exammer
`
`(65)
`
`Prior Publication Data
`Us 2003/0070052 A1
`Apr' 10, 2003
`
`Primary ExamineriPierre M. Vital
`(74) Attorney, Agent, or FirmilC. Patents
`
`Related US. Application Data
`
`(57)
`
`ABSTRACT
`
`(60) Provisional application NO. 60/328,284, ?led O11 001.
`9, 2001-
`
`A common DRAM Controller is provided for supporting a
`plurality of memory types such as double data rate or quad
`data rate mode or types. The controller is adapted to use a
`_
`_
`_
`_
`_
`number of clock signals to process data. The controller can
`Forelgn APPhcatmn Prlorlty Data
`(30)
`Jun. 18 2002
`(TW) ............................. .. 91113215 A further delay the data for a Pr96191911111111?d time PeriOd and
`3
`capture the same.
`(51) Int. Cl.
`G06F 12/00
`
`(2006.01)
`
`14 Claims, 8 Drawing Sheets
`
`\ l
`E
`"
`
`QDR Read
`CLK
`
`CS(0.1)
`DOS
`DQM
`
`MD
`
`Reod
`
`I
`
`1
`
`\
`
`:
`
`/
`
`\
`
`F
`
`1
`E
`' rxfxfxifl
`flflflj
`
`1
`\
`
`\_.X__X__X_,_X__X__L,X__)——
`
`NVIDIA Corp.
`Exhibit 1003
`Page 001
`
`

`
`U.S. Patent
`
`Apr. 18, 2006
`
`Sheet 1 0f 8
`
`US 7,032,092 B2
`
`DDR Read
`CLK
`cs(o,1)
`DQS
`DQM
`MD
`
`DDR Write
`CLK
`cs(0,1)
`DQS
`DQM
`MD
`
`FIG. 1
`
`FIG. 2
`
`NVIDIA Corp.
`Exhibit 1003
`Page 002
`
`

`
`U.S. Patent
`
`Apr. 18, 2006
`
`Sheet 2 0f 8
`
`US 7,032,092 B2
`
`508%
`0:25
`5i
`
`Q59
`
`960mm
`
`305%
`1Com
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`56:58
`39:22
`
`92
`
`NVIDIA Corp.
`Exhibit 1003
`Page 003
`
`

`
`U.S. Patent
`
`Apr. 18, 2006
`
`Sheet 3 0f 8
`
`US 7,032,092 B2
`
`QDR Read
`CLK
`cs(0,1)
`DQS
`DQM
`MD
`
`QDR Write
`CLK
`cs(0,1)
`DQS
`DQM
`MD
`
`FIG. 4
`
`FIG. 5
`
`NVIDIA Corp.
`Exhibit 1003
`Page 004
`
`

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`U.S. Patent
`
`Apr. 18, 2006
`
`Sheet 4 0f 8
`
`US 7,032,092 B2
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`59:22
`
`NVIDIA Corp.
`Exhibit 1003
`Page 005
`
`

`
`U.S. Patent
`
`Apr. 18,2006
`
`Sheet 5 of 8
`
`US 7,032,092 B2
`
`QBM Read
`
`
`
`QBMWRITEA
`CLK
`
`
`
`NVIDIA Corp.
`Exhibit 1003
`Page 006
`
`NVIDIA Corp.
`Exhibit 1003
`Page 006
`
`

`
`U.S. Patent
`
`Apr. 18,2006
`
`Sheet 6 of 8
`
`US 7,032,092 B2
`
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`
`NVIDIA Corp.
`Exhibit 1003
`Page 007
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`NVIDIA Corp.
`Exhibit 1003
`Page 007
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`
`
`
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`
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`

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`U.S. Patent
`
`Apr. 18, 2006
`
`Sheet 7 0f 8
`
`US 7,032,092 B2
`
`MSEL
`
`906
`\ First Difference
`Output Signal
`
`<___—_- Multiplexer Second Difference
`DQSI
`Output Signal
`
`902
`
`V
`REF
`
`_DQ_S
`
`DQM
`
`904
`
`FIG. 1 0
`
`1004
`
`DQS I
`
`D05
`
`1002
`
`f’ VREF
`
`Multiplexer
`
`E
`
`DQM
`
`MSEL
`FIG. 1 1
`
`NVIDIA Corp.
`Exhibit 1003
`Page 008
`
`

`
`U.S. Patent
`
`Apr. 18, 2006
`
`Sheet 8 0f 8
`
`US 7,032,092 B2
`
`MSEL
`l
`
`f 1 102
`First Delay
`Circuit
`
`DQSI
`
`<_DQS_1I Multiplexer
`f
`1 106
`
`Second Delay
`Circuit
`
`L 1 104
`FIG. 12
`
`MSEL
`
`First Delay
`Selection Signal
`Multiplexer seconfj Dewy
`Selection Signal
`
`Programmable Delay Circuit
`
`NVIDIA Corp.
`Exhibit 1003
`Page 009
`
`

`
`US 7,032,092 B2
`
`1
`MEMORY CONTROLLER FOR
`SUPPORTING A PLURALITY OF
`DIFFERENT MEMORY ACCESSE MODES
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`This application claims the priority bene?t of US. pro
`visional application titled “COMMON DRAM CONTROL
`LER SUPPORTS DOUBLE-DATA-RATE AND QUAD
`DATA-RATE MEMOR ” ?led on Oct. 9, 2001, serial No.
`60/328,284. All disclosures of this application is incorpo
`rated herein by reference. This application also claims the
`priority bene?t of TaiWan application serial no. 91113215,
`?led Jun. 18, 2002.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a controller for supporting
`a plurality of different memory access.
`2. Description of the Background Art
`DRAM has evolved from asynchronous DRAM to syn
`chronous DRAM. For example, Fast-Page DRAM and
`Extended Data Output (EDO) DRAM have evolved to
`Synchronous Dynamic Random Access Memory (hereinaf
`ter abbreviated to SDRAM). Currently, high speed memory
`banks generally use synchronous source methods for achiev
`ing data transmission. By Way of an example, Double Data
`Rate dynamic random access (hereinafter abbreviated to
`DDR SDRAM) memory bank is one of the methods. In
`addition, these high speed memory banks require differential
`signals for data transmission. Therefore, real high access
`speed for DRAMs requires differential signaling. It is desir
`ous to combine source synchronization With differential
`signaling.
`Furthermore, DRAM market tends to be outpaced in
`bandWidth by such elements as processor, I/O devices, or
`graphic add-on devices. This de?ciency in bandWidth
`becomes especially signi?cant for high volume data transfer
`applications such as Internet applications.
`In order to further improve the bandWidth, schemes such
`as Double Data Rate (DDR), Quad Band Memory (QBM),
`and Quad Data Rate (QDR) are capable of transmitting four
`units of data as compared to a single unit for the baseline
`rate. Further, the above has the advantage of using existing
`loW-cost technology for increasing the bandWidth.
`Memory having different data rate or data types generally
`requires different and separated memory controllers for each
`and every data type. A number of memory controllers may
`be required for a single application. Further, more control
`lers complicate the system and can be space consuming and
`expensive.
`As can be seen, there is a need for a single memory
`controller Which controls different memory types or modes.
`
`SUMMARY OF THE INVENTION
`
`A common DRAM controller is provided for supporting
`a plurality of memory types such as double data rate or quad
`data rate mode or types. The controller is adapted to use a
`number of clock signals to process data. The controller can
`further delay the data for a predetermined time period and
`capture the same.
`Accordingly, a memory controller for supporting different
`memory modes is provided. The memory controller has a
`determining device, a memory Writing device, and a
`
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`memory reading device. The determining device used for
`determining a memory mode. The determining device gen
`erates a memory selection signal. A memory Writing device
`uses the memory selection signal to provide a data selection
`signal, Wherein the data selection signal is chosen from a
`?rst clock signal or a second clock signal. The memory
`Writing device further provides a data mask signal, Wherein
`the data mask signal is chosen among a byte mask signal, a
`third clock signal, or a fourth clock signal. The memory
`Writing device still further provides a memory data signal,
`Wherein multiunit data are adapted to be carried therein. The
`memory data signal is controlled by the fourth clock signal
`or a ?fth clock signal. A memory reading device for receiv
`ing the data selection signal, the data mask signal, and a
`reference voltage is provided. The memory device provides
`at least one differential signal and chooses the one differ
`ential signal based upon the memory selection signal and
`delay the one differential signal for a predetermined time
`period for locking data on the memory data signal.
`Accordingly, a memory controller for supporting different
`memory modes is provided. The memory controller has a
`determining device, a memory Writing device, and a
`memory reading device. The determining device used for
`determining a memory mode, and generates a memory
`selection signal. The memory Writing device uses the
`memory selection signal to provide a data selection signal,
`Wherein the data selection signal is a ?rst clock signal. The
`memory Writing device further provides a data mask signal,
`Wherein the data mask signal is chosen from a byte mask
`signal or a second clock signal. The memory Writing device
`still further provides a memory data signal, Wherein multi
`unit data are adapted to be carried therein. The memory data
`signal is controlled by the second clock signal or a third
`clock signal. The memory reading device is used for receiv
`ing the data selection signal, the data mask signal, and a
`reference voltage. The memory device provides a differen
`tial signal and chooses the differential signal based upon the
`memory selection signal. The memory device further delays
`the differential signal for a predetermined time period for
`locking data on the memory data signal.
`Accordingly, a receiver used in a memory controller
`disposed to use a plurality of clock signals for supporting
`different memory modes is provided. The receiver has a ?rst
`differential buffer, a second differential buffer, and a multi
`plexer. The ?rst differential buffer is used for comparing the
`data selection signal With the reference voltage and provides
`a ?rst differential output signal. The second differential
`buffer is used for comparing data selection signal With a data
`mask signal and provides a second differential output signal.
`The multiplexer is used for selecting an output thereof
`betWeen the ?rst differential output signal or the second
`differential output signal according to a memory selection
`signal.
`Accordingly, a receiver used in a memory controller
`disposed to use a plurality of clock signals for supporting
`different memory modes is provided. The receiver has a
`multiplexer and a differential buffer. The multiplexer is used
`for generating an output by selecting betWeen a reference
`voltage and a data mask signal as an output according to the
`memory selection signal. The differential buffer is used for
`comparing data selection signal With the output and provides
`a third differential signal.
`Accordingly, a data selection signal delay circuit adapted
`to be used in a memory controller for supporting different
`memory modes is provided. The data selection signal delay
`circuit has a ?rst delay circuit, a second delay circuit, and a
`multiplexer. The ?rst delay circuit is used for receiving a
`
`NVIDIA Corp.
`Exhibit 1003
`Page 010
`
`

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`US 7,032,092 B2
`
`3
`differential signal. After delaying the differential signal for a
`predetermined time period, the ?rst delay circuit providing
`a ?rst delay signal. The second delay circuit is used for
`receiving the differential signal. After delaying the differ
`ential signal for a predetermined time period, the second
`delay circuit provides a second delay signal. The multiplexer
`is used for providing an output, Wherein the output is based
`upon a selection betWeen the ?rst delay signal and the
`second delay signal. The selection based upon information
`carried by a memory selection signal.
`Accordingly, a data selection signal delay circuit adapted
`to be used in a memory controller disposed to use a plurality
`of clock signals for supporting different memory modes is
`provided. The data selection signal delay circuit has a
`multiplexer and a programmable delay circuit. The multi
`plexer is used for providing an output selected betWeen a
`?rst delay selection signal and a second delay selection
`signal. The selection is based upon information contained
`Within the memory selection signal. The programmable
`delay circuit is used for receiving the output and a differ
`ential signal, and provides a time delay, Wherein signal
`passing through the data selection signal delay circuit is
`delayed for a predetermined time period.
`These and other features, aspects and advantages of the
`present invention Will become better understood With refer
`ence to the folloWing draWings, description and claims.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a timing diagram of the present invention
`depicting a reading using DDR SDRAM;
`FIG. 2 is a timing diagram of the present invention
`depicting a Writing using DDR SDRAM;
`FIG. 3 is a block diagram of the present invention
`depicting a memory controller coupled to a QDR structure;
`FIG. 4 is a timing diagram of the present invention
`depicting a reading of the QDR structure;
`FIG. 5 is a timing diagram of the present invention
`depicting a Writing of the QDR structure;
`FIG. 6 is a block diagram of the present invention
`depicting the memory controller coupled to a QBM struc
`ture;
`FIG. 7 is a timing diagram of the present invention
`depicting a reading using QBM;
`FIG. 8 is a timing diagram of the present invention
`depicting a Writing using QBM;
`FIG. 9 is a preferred embodiment of the memory control
`ler, Wherein different memory modes are supported;
`FIG. 10 is a ?rst embodiment of a DOS receiver according
`to the present invention;
`FIG. 11 is a second embodiment of a DOS receiver
`according to the present invention;
`FIG. 12 is a ?rst embodiment of a delay circuit according
`to the present invention; and
`FIG. 13 is a second embodiment of a delay circuit
`according to the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The folloWing detailed description is of the best currently
`contemplated modes of carrying out the invention. The
`description is not to be taken in a limiting sense, but is made
`merely for the purpose of illustrating the general principles
`of the invention, since the scope of the invention is best
`de?ned by the appended claims.
`
`4
`Referring to FIG. 1, a timing diagram of the present
`invention depicting a reading process using DDR SDRAM
`is shoWn. CLK denotes a memory clock signal having a
`?xed frequency. When chip selection signal CS (0,1) is
`activated, the DDR SDRAM starts the reading process. As
`shoWn in FIG. 1, DDR SDRAM uses memory data signal
`(MD) to carry requisite data. The data segments correspond
`With the rising edges and the falling edges of data selective
`pass signal (DQS) respectively. As can be appreciated, in
`order to lock the memory data signal (MD), data selective
`pass signal (DQS) is required to have a time delay or a time
`lag. The time lag is usually one fourth of the clock CLK
`cycle.
`Referring to FIG. 2, a timing diagram of the present
`invention depicting a Writing process using DDR SDRAM is
`shoWn. CLK denotes a memory clock signal having a ?xed
`frequency. When chip selection signal CS (0,1) is activated,
`the DDR SDRAM starts a Writing process. As shoWn in FIG.
`2, data selective pass signal (DQS) from the memory con
`troller has the same frequency as CLK. Data mask signal
`(DQM) carries byte mask data, While memory data signal
`(MD) carries data for Writing. Apredeterrnined phase or time
`lag exists betWeen data selective pass signal (DOS) and data
`mask signal (DQM), as Well as betWeen memory data signal
`(MD). In other Words, data selective pass signal (DQS)
`possesses a time lag in relation to both data mask signal
`(DQM) and memory data signal (MD). The time lag may be
`expressed as one fourth of the memory clock cycle. Because
`of this time lag, DDR SDRAM can lock data of the data
`mask signal (DQM), and lock data of the memory data
`signal (MD).
`Furthermore, TaiWan patent number 89116720 ?led on
`Aug. 18, 2000, entitled “A Buffer for Altering Data Storage
`and Retrieval Rate and the System Therefore”, Which is
`hereby incorporated by reference in its entirety. Said TaiWan
`patent teaches a buffer chip capable of transmitting four
`units of data With a clock cycle (Quad Data Rate, “QDR”
`hereinafter) to increase the bandWidth of memory banks.
`The buffer chip is interposed betWeen DDR SDRAM and the
`memory control chip. In other Words, the inventive bulfer
`chip has a ?rst end coupled to the DDR SDRAM, and a
`second end coupled to the memory controller.
`Referring to FIG. 3, a block diagram depicting the rela
`tionship betWeen memory controller 102 and the QDR
`structure 10 is shoWn. Memory controller 102 resides Within
`control chip 100. QDR structure 10 comprises buffer chip
`108, Wherein a plurality of ?rst-in ?rst-out (FIFO) buffers
`are located. This doubles the data rate for reading and
`Writing of a ?rst data selection signal (DQSA), and a ?rst
`data signal (MDA) of a ?rst memory bank 104 of the DDR
`SDRAM structure. Similarly, the rate is also doubled for a
`second data selection signal (DQSB) and a second data
`signal (MDB) of a second memory bank 106.
`The signals betWeen memory controller 102 and buffer
`chip 108 operate and four times faster than a baseline rate.
`The signals comprises data selection signal (DQS), data
`mask signal (DQM), and memory data signal (MD). There
`fore, four units of data can be transmitted Within one
`memory clock cycle.
`Referring to FIG. 4, a timing diagram for a reading of the
`QDR structure is depicted. CLK denotes a memory clock
`signal. When chip selection signal CS (0,1) is active, the
`QDR structure starts its operation. According to the instant
`?gure, data selection signal (DQS) processes of frequency is
`tWice the frequency of memory clock signal (CLK). Fur
`thermore, memory data signal (MD), corresponds to the
`rising edges and the falling edges of data selection signal
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`Exhibit 1003
`Page 011
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`(DQS). Data mask signal (DQM) is the reverse of data
`selection signal (DQS). In other Words, a 180 degrees phase
`difference exists betWeen the tWo signals. As can be appre
`ciated, memory controller 102 needs to cause a predeter
`mined time lag in data selection signal (DQS) and in data
`mask signal (DQM) in order to lock the data contained in the
`memory data signal (MD). Usually, the time lag is about 1A
`of the memory clock CLK cycle.
`Referring to FIG. 5, a timing diagram for a Writing of the
`QDR structure is depicted. CLK denotes a memory clock
`signal. When chip selection signal CS (0,1) is active, the
`QDR structure starts its operation. According to the instant
`?gure, data selection signal (DQS) processes a frequency
`that is tWice the frequency of memory clock signal (CLK).
`Data mask signal (DQM) is the reverse of data selection
`signal (DQS). The memory data signal (MD) and the data
`selection signal (DQS) coming from the memory controller
`102 possess a predetermined phase difference, usually one
`quarter of the memory clock cycle. Therefore, buffer chip
`108 may lock data of the memory data signal (MD) and
`transmit the same to the tWo memory banks 104, 106
`respectively according to data selection signal (DQS) and
`the data mask signal (DQM).
`In addition, a commonly knoWn technology, Quad Band
`Memory (QBM) that may be controlled by memory con
`troller 112 is shoWn in FIG. 6. QBM structure includes ?eld
`effect transistor (FET) sWitch circuit 118, a ?rst memory
`bank DDR SDRAM 114, and a second memory bank DDR
`SDRAM 116. According to the instant ?gure, QBM struc
`ture 12 uses FET sWitch circuit 118 to double the transmis
`sion rate of the ?rst data selection signal (DQSA) and data
`selection signal (MDA) of the ?rst memory bank 114.
`Similarly, the transmission to the second memory bank 116
`is doubled as Well. Therefore, in a single memory clock
`cycle, four units of data are capable of being transmitted.
`Referring to FIG. 7, a timing diagram of QBM reading
`process is shoWn. CLK denotes a memory clock signal.
`Furthermore, a second memory clock signal CLK_90 Which
`possesses a 1A cycle phase difference With CLK is shoWn.
`When chip selection signal CS (0,1) is activated, QBM
`40
`structure starts a reading process. According to the instant
`?gure, QBM structure’s data selection signal (DQS) and
`data mark signal (DQM) possess a frequency that is tWice
`the frequency of memory clock signal (CLK). Furthermore,
`the memory data signal (MD), relating to FET sWitch circuit
`118, correspond With the rising and falling edges of data
`selection signal (DQS). Therefore, memory controller 112
`needs to delay the data selection signal (DQS) or data mask
`signal (DQM) for a predetermined time segment in order to
`lock data carried by memory data signal (MD). The locking
`of data is accomplished by the delay or time lag Working in
`combination With a reference voltage (not shoWn).
`Referring to FIG. 8, a timing diagram depicting the
`Writing process of QBM is shoWn. CLK denotes a memory
`clock signal. Furthermore, a second memory clock signal
`CLK_90 Which possesses a 1/4 cycle phase difference With
`CLK is shoWn. When chip selection signal CS (0,1) is
`activated, QBM structure starts the Writing process. Accord
`ing to the instant ?gure, memory controller 112 may output
`data selection signal (DQS) having a corresponding rela
`tionship With CLK. On the other hand, data mask signal
`(DQM) has a corresponding relationship With CLK_90.
`Memory data signal (MD) has a corresponding relationship
`With a memory clock signal having tWice the frequency of
`CLK With a time lag of usually 1A cycle. This memory clock
`signal is de?ned as CLK2X (not shoWn). The ?eld effect
`transistor sWitch circuit 118 is capable of sequentially lock
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`ing information or data carried by memory data signal (MD)
`according to data selection signal (DQS) and data mask
`signal (DQM). In addition, ?eld effect transistor sWitch
`circuit 118 transmits information carried by memory data
`signal (MD) to the tWo memory banks 114, 116 respectively.
`As can be appreciated, during the Writing process of the
`memory described supra, memory controller 112, 102 needs
`to provide the folloWing reference timing clock signals to
`DDR SDRAM. This is true in either QDR structure, or QBM
`structure. The reference timing clock signals are depicted in
`table 1.
`
`TABLE 1
`
`Various timing signals’ correlation With control and data signals
`
`DDR
`
`QDR
`
`QBM
`
`CLK
`CLKi9O
`CLKi90
`
`CLKZX
`CLK2X#
`CLK2Xi90
`
`CLK
`CLKi9O
`CLK2Xi90
`
`DQS generation
`DQM generation
`MC Write data
`control
`
`In order to let controller chip 100, 110 to simultaneously
`support all the DDR SDRAM structures described supra, the
`instant invention provide a memory controller 20 as shoWn
`in FIG. 9.
`Referring to FIG. 9, the memory controller 20 includes a
`determining device 22, a memory Writing device 24, and a
`memory reading device 26. A clock signal generator 220 is
`provided Which are capable of at least generating memory
`clock signal CLK; a second signal that possesses a 1/4 cycle
`delay in relation to CLK, i.e. CLK_90; a third signal that
`possesses tWice the frequency of CLK, i.e.CLK2X; a fourth
`signal that possesses a tWice reverse the frequency of CLK,
`i.e.CLK2X#, and a ?fth signal that possesses tWice the
`frequency of CLK combined With a 1A cycle delay, i.e.
`CLK2X_90.
`Determining device 22 includes memory structure infor
`mation device 202 and decoder circuit 204. Information on
`the structure or mode of the corresponding memory type is
`stored in the memory structure information device 202. The
`information includes information relating to the QDR struc
`ture and the QBM structure described supra. The decoder
`circuit 204 receives memory address information. Decoder
`circuit 204 further provides a memory selection signal
`(MSEL), Wherein information regarding memory type or
`mode is contained. The memory mode includes DDR
`SDRAM mode, QDR mode, and QBM mode.
`Memory Writing device 24 receives memory selection
`signal (MSEL) provided by memory determining device 22.
`The memory Writing device 24 includes a data selection
`(DQS) generator 206, a data mask (DQM) generator 208, a
`Writing process controller 210, and a Writing data buffer 212.
`When memory mode is DDR SDRAM, memory selection
`signal (MSEL) informs the same to memory Writing device
`24 thereby data selection (DQS) generator 206 may select a
`suitable memory clock signal among a plurality of clock
`signals as the data selection signal (DQS). In this case, CLK
`is selected. On the other hand, DQM generator 208 selects
`byte mask data as the data mask signal (DQM) Which is
`coordinated With CLK_90. Similarly, Writing process con
`troller 210 selects CLK_90 and transmits data Within the
`Writing data buffer 212 to memory data signal (MD).
`When memory mode is the QDR structure, memory
`selection signal (MSEL) noti?es memory Writing device 24.
`Accordingly, DQS generator 206 selects CLK2X as data
`selection signal (DQS). The DQM generator 208 selects
`
`NVIDIA Corp.
`Exhibit 1003
`Page 012
`
`

`
`US 7,032,092 B2
`
`7
`CLK2X# as data mask signal (DQM). The Writing process
`controller 210 selects CLK2X_90 as memory clock signal.
`Data Within Writing data buffer 212 is transmitted via data
`signal (MD) accordingly.
`When memory mode is the QBM structure, memory
`selection signal (MSEL) noti?es memory Writing device 24.
`DQS generator 206 selects CLK as data selection signal
`(DQS). The DQM generator 208 selects CLK2X_90 as data
`mask signal (DQM). The Writing process controller 210
`selects CLK2X_90 as memory clock signal. Data Within
`Writing data buffer 212 is transmitted via data signal (MD)
`accordingly.
`Memory reading device 26 receives memory selection
`signal (MSEL) provided by determining device 22. Memory
`reading device 26 includes DQS receiver 214, DQS delay
`circuit 216, and locking circuit 218.
`In addition, When memory mode is DDR SDRAM,
`memory selection signal (MSEL) noti?es memory reading
`device 26 thereby causing DQS receiver 214 to generate a
`locking signal. The locking signal comprises a differential
`input signal comprising the combination of data selection
`signal DQS and a reference voltage (VREF). The differential
`input signal is further delayed by DQS delay circuit 216 for
`a predetermined time segment Which is usually 1A cycle.
`Locking circuit 218 locks information transmitted via data
`signal (MD) accordingly.
`When memory mode is the QDR structure, memory
`selection signal (MSEL) noti?es the same to memory read
`ing device 26 thereby DQS receiver 214 selects a second
`differential input signal. The second differential input signal
`includes a combination of data selection signal (DQS) and
`data mask signal (DQM). The second differential input
`signal is further delayed on DQS delay circuit 216 for a
`predetermined time segment before locking circuit 218 locks
`the information on the data signal (MD). The delayed time
`segment has a length of about 1A cycle of the data selection
`signal according to the second differential input signal.
`When memory mode is the QBM structure, memory
`selection signal (MSEL) noti?es the same to memory read
`ing device 26 thereby DQS receiver 214 selects a third
`differential input signal. The third differential input signal
`includes a combination of data selection signal (DQS) and
`the reference voltage (V REF). The third differential input
`signal is further delayed on DQS delay circuit 216 by a
`predetermined time segment before locking circuit 218 locks
`the information on the data signal (MD). The delayed time
`segment has a length of about 1A cycle of the data selection
`signal according to the second differential input signal.
`DQS receiver 214 may be formed in various Ways includ
`ing the folloWing tWo Ways. For the ?rst of the tWo Ways of
`forming DQS receiver 214, refer to FIG. 10, Wherein a
`real-life example of a DQS receiver 214 is shoWn.
`Referring noW to FIG. 10, the DQS receiver 214 includes
`a ?rst differential buffer 902, a second differential buffer
`904, and a multiplexer 906. First differential buffer 902 is
`used for comparing data selection signal DQS and reference
`voltage (VREF). Based upon the comparison, a ?rst differ
`ential output signal is generated. Second differential buffer
`904 is used for comparing data selection signal DQS and
`data mask signal (DQM). Based upon the comparison, a
`second differential output signal is generated.
`Multiplexer 906 is used to receive the ?rst differential
`output signal and the second differential output signal. Based
`on the control of memory selection signal (MSEL), multi
`plexer 906 selectively permits either the ?rst differential
`output or the second differential output to pass therethrough.
`
`20
`
`25
`
`30
`
`40
`
`45
`
`55
`
`60
`
`65
`
`8
`The differential outputs that is permitted to pass through
`multiplexer 906 is de?ned as DQS I. DQS I is selected by
`the multiplexer to be the ?rst differential output signal When
`the memory modes are DDR SDRAM, or QBM structure.
`On the other hand, When the memory mode is QDR struc
`ture, multiplexer selects the ?rst differential output signal as
`DQS I.
`With regard to the second of the tWo Ways of forming
`DQS receiver 214, refer to FIG. 11, Wherein a real-life
`example of a DQS receiver 214 is shoWn. This receiver 214
`includes a buffer 1004, and a multiplexer 1002. Multiplexer
`1002 is used for receiving reference voltage VREF and data
`mask signal (DQM). Based on the control of memory
`selection signal (MSEL), multiplexer 906 selects either
`reference voltage VREF or data mask signal (DQM) for
`comparison With data selection signal (DQS). Upon com
`parison, bulfer 1004 generates differential output signal and
`de?ned the same as DQS I. If memory modes are DDR
`SDRAM or QBM structure, multiplexer 1002 selects refer
`ence voltage VREF to compare With data selection signal
`(DQS) for the generation of DQS I. If the memory mode is
`QDR structure, multiplexer 1002 selects memory selection
`signal (MSEL) for comparison With data selection signal
`(DQS) to generate DQS I.
`In addition, DQS delay circuit 216 may be formed in tWo
`different Ways. A ?rst Way of forming the delay circuit 216
`is shoWn in FIG. 12 Which is based on a practical applica
`tion. The delay circuit 216 includes a ?rst delay circuit 1102,
`a second delay circuit 1104, and a multiplexer 1106. First
`delay circuit 1102 is disposed to receive DQS I and delay the
`same for a predetermined time segment if required. For
`example, the predetermined time segment may be equal to
`1A cycle of a memory clock signal. Second delay circuit 1104
`is disposed to receive DQS I and introduce a delay based
`upon the four unit data transmission rate such as QDR or
`QBM structure. A second delay time segment is required
`before coupling With multiplexer 1106. For example, second
`delay time segment may be equal to 1/s cycle of a memory
`clock signal. The output DQS II of multiplexer 1106 is based
`upon a selection from either the output of the ?rst delay
`circuit 1102, or the output of the second delay circuit 1104.
`The selection depends upon memory selection signal
`(MSEL).
`A second Way of forming the delay circuit 216 is shoWn
`in FIG. 13 Which is based on a practical application. The
`delay circuit 216 includes multiplexer 1202, and a program
`mable delay circuit 1204. Multiplexer 1202 selectively
`outputs either a ?rst delay selection signal or a second delay
`selection signal according to memory selection signal
`(MSEL). The selected output is further conveyed to pro
`grammable delay circuit 1204. If memory mode is DDR
`SDRAM, multiplexer 1202 selects the ?rst delay selection
`signal and conveys the same to the programmable delay
`circuit 1204. Further, DQS I is delayed 1A cycle and out
`putted as DQS II. If memory mode is QDR or QBM
`structure, multiplexer 1202 selects the second delay selec
`tion signal and conveys the same to programmable delay
`circuit 1204. Further, DQS I is delayed 1/s cycle and out
`putted as. DQS II.
`Finally, locking circuit 218 may lock information carried
`on memory data signal (MD) according to DQS II signal.
`In summary, there are at least several advantages in the
`invention, Which are as followed. (1) The memory controller
`of the invention supports different memory modes by pro
`viding a determining device, a memory Writing device, and
`a memory reading device. (2) Motherboard manufacturing
`companies